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https://github.com/RPCS3/llvm-mirror.git
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[X86][AVX512] Added 512-bit integer vector non-temporal load tests
llvm-svn: 272016
This commit is contained in:
Simon Pilgrim
parent
c01451b548
commit
7ece42dd08
@ -989,6 +989,200 @@ entry:
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ret <8 x double> %0
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ret <8 x double> %0
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}
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}
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; TODO - 512-bit integer vector loads
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define <64 x i8> @test_load_nt64xi8(<64 x i8>* nocapture %ptr) {
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; SSE2-LABEL: test_load_nt64xi8:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movaps (%rdi), %xmm0
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; SSE2-NEXT: movaps 16(%rdi), %xmm1
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; SSE2-NEXT: movaps 32(%rdi), %xmm2
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; SSE2-NEXT: movaps 48(%rdi), %xmm3
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; SSE2-NEXT: retq
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;
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; SSE4A-LABEL: test_load_nt64xi8:
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; SSE4A: # BB#0: # %entry
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; SSE4A-NEXT: movaps (%rdi), %xmm0
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; SSE4A-NEXT: movaps 16(%rdi), %xmm1
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; SSE4A-NEXT: movaps 32(%rdi), %xmm2
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; SSE4A-NEXT: movaps 48(%rdi), %xmm3
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; SSE4A-NEXT: retq
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;
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; SSE41-LABEL: test_load_nt64xi8:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: movntdqa (%rdi), %xmm0
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; SSE41-NEXT: movntdqa 16(%rdi), %xmm1
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; SSE41-NEXT: movntdqa 32(%rdi), %xmm2
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; SSE41-NEXT: movntdqa 48(%rdi), %xmm3
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: test_load_nt64xi8:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vmovaps (%rdi), %ymm0
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; AVX1-NEXT: vmovaps 32(%rdi), %ymm1
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test_load_nt64xi8:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vmovntdqa (%rdi), %ymm0
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; AVX2-NEXT: vmovntdqa 32(%rdi), %ymm1
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: test_load_nt64xi8:
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; AVX512F: # BB#0: # %entry
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; AVX512F-NEXT: vmovntdqa (%rdi), %ymm0
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; AVX512F-NEXT: vmovntdqa 32(%rdi), %ymm1
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; AVX512F-NEXT: retq
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;
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; AVX512BW-LABEL: test_load_nt64xi8:
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; AVX512BW: # BB#0: # %entry
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; AVX512BW-NEXT: vmovntdqa (%rdi), %zmm0
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; AVX512BW-NEXT: retq
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entry:
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%0 = load <64 x i8>, <64 x i8>* %ptr, align 64, !nontemporal !1
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ret <64 x i8> %0
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}
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define <32 x i16> @test_load_nt32xi16(<32 x i16>* nocapture %ptr) {
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; SSE2-LABEL: test_load_nt32xi16:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movaps (%rdi), %xmm0
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; SSE2-NEXT: movaps 16(%rdi), %xmm1
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; SSE2-NEXT: movaps 32(%rdi), %xmm2
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; SSE2-NEXT: movaps 48(%rdi), %xmm3
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; SSE2-NEXT: retq
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;
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; SSE4A-LABEL: test_load_nt32xi16:
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; SSE4A: # BB#0: # %entry
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; SSE4A-NEXT: movaps (%rdi), %xmm0
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; SSE4A-NEXT: movaps 16(%rdi), %xmm1
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; SSE4A-NEXT: movaps 32(%rdi), %xmm2
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; SSE4A-NEXT: movaps 48(%rdi), %xmm3
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; SSE4A-NEXT: retq
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;
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; SSE41-LABEL: test_load_nt32xi16:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: movntdqa (%rdi), %xmm0
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; SSE41-NEXT: movntdqa 16(%rdi), %xmm1
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; SSE41-NEXT: movntdqa 32(%rdi), %xmm2
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; SSE41-NEXT: movntdqa 48(%rdi), %xmm3
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: test_load_nt32xi16:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vmovaps (%rdi), %ymm0
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; AVX1-NEXT: vmovaps 32(%rdi), %ymm1
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test_load_nt32xi16:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vmovntdqa (%rdi), %ymm0
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; AVX2-NEXT: vmovntdqa 32(%rdi), %ymm1
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: test_load_nt32xi16:
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; AVX512F: # BB#0: # %entry
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; AVX512F-NEXT: vmovntdqa (%rdi), %ymm0
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; AVX512F-NEXT: vmovntdqa 32(%rdi), %ymm1
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; AVX512F-NEXT: retq
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;
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; AVX512BW-LABEL: test_load_nt32xi16:
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; AVX512BW: # BB#0: # %entry
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; AVX512BW-NEXT: vmovntdqa (%rdi), %zmm0
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; AVX512BW-NEXT: retq
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entry:
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%0 = load <32 x i16>, <32 x i16>* %ptr, align 64, !nontemporal !1
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ret <32 x i16> %0
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}
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define <16 x i32> @test_load_nt16xi32(<16 x i32>* nocapture %ptr) {
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; SSE2-LABEL: test_load_nt16xi32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movaps (%rdi), %xmm0
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; SSE2-NEXT: movaps 16(%rdi), %xmm1
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; SSE2-NEXT: movaps 32(%rdi), %xmm2
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; SSE2-NEXT: movaps 48(%rdi), %xmm3
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; SSE2-NEXT: retq
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;
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; SSE4A-LABEL: test_load_nt16xi32:
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; SSE4A: # BB#0: # %entry
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; SSE4A-NEXT: movaps (%rdi), %xmm0
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; SSE4A-NEXT: movaps 16(%rdi), %xmm1
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; SSE4A-NEXT: movaps 32(%rdi), %xmm2
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; SSE4A-NEXT: movaps 48(%rdi), %xmm3
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; SSE4A-NEXT: retq
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;
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; SSE41-LABEL: test_load_nt16xi32:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: movntdqa (%rdi), %xmm0
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; SSE41-NEXT: movntdqa 16(%rdi), %xmm1
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; SSE41-NEXT: movntdqa 32(%rdi), %xmm2
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; SSE41-NEXT: movntdqa 48(%rdi), %xmm3
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: test_load_nt16xi32:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vmovaps (%rdi), %ymm0
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; AVX1-NEXT: vmovaps 32(%rdi), %ymm1
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test_load_nt16xi32:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vmovntdqa (%rdi), %ymm0
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; AVX2-NEXT: vmovntdqa 32(%rdi), %ymm1
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test_load_nt16xi32:
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; AVX512: # BB#0: # %entry
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; AVX512-NEXT: vmovntdqa (%rdi), %zmm0
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; AVX512-NEXT: retq
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entry:
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%0 = load <16 x i32>, <16 x i32>* %ptr, align 64, !nontemporal !1
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ret <16 x i32> %0
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}
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define <8 x i64> @test_load_nt8xi64(<8 x i64>* nocapture %ptr) {
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; SSE2-LABEL: test_load_nt8xi64:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movaps (%rdi), %xmm0
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; SSE2-NEXT: movaps 16(%rdi), %xmm1
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; SSE2-NEXT: movaps 32(%rdi), %xmm2
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; SSE2-NEXT: movaps 48(%rdi), %xmm3
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; SSE2-NEXT: retq
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;
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; SSE4A-LABEL: test_load_nt8xi64:
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; SSE4A: # BB#0: # %entry
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; SSE4A-NEXT: movaps (%rdi), %xmm0
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; SSE4A-NEXT: movaps 16(%rdi), %xmm1
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; SSE4A-NEXT: movaps 32(%rdi), %xmm2
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; SSE4A-NEXT: movaps 48(%rdi), %xmm3
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; SSE4A-NEXT: retq
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;
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; SSE41-LABEL: test_load_nt8xi64:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: movntdqa (%rdi), %xmm0
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; SSE41-NEXT: movntdqa 16(%rdi), %xmm1
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; SSE41-NEXT: movntdqa 32(%rdi), %xmm2
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; SSE41-NEXT: movntdqa 48(%rdi), %xmm3
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: test_load_nt8xi64:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vmovaps (%rdi), %ymm0
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; AVX1-NEXT: vmovaps 32(%rdi), %ymm1
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test_load_nt8xi64:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vmovntdqa (%rdi), %ymm0
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; AVX2-NEXT: vmovntdqa 32(%rdi), %ymm1
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test_load_nt8xi64:
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; AVX512: # BB#0: # %entry
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; AVX512-NEXT: vmovntdqa (%rdi), %zmm0
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; AVX512-NEXT: retq
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entry:
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%0 = load <8 x i64>, <8 x i64>* %ptr, align 64, !nontemporal !1
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ret <8 x i64> %0
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}
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!1 = !{i32 1}
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!1 = !{i32 1}
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