From 7ed143a4a1ddb96006df2a145d9fb512385e1f91 Mon Sep 17 00:00:00 2001 From: Jinsong Ji Date: Thu, 6 Feb 2020 16:12:10 +0000 Subject: [PATCH] [AsmPrinter] Print FP constant in hexadecimal form instead Printing floating point number in decimal is inconvenient for humans. Verbose asm output will print out floating point values in comments, it helps. But in lots of cases, users still need additional work to covert the decimal back to hex or binary to check the bit patterns, especially when there are small precision difference. Hexadecimal form is one of the supported form in LLVM IR, and easier for debugging. This patch try to print all FP constant in hex form instead. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D73566 --- include/llvm/MC/MCExpr.h | 9 +- include/llvm/MC/MCStreamer.h | 7 + lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 8 +- lib/MC/MCAsmStreamer.cpp | 6 + lib/MC/MCExpr.cpp | 24 ++- test/CodeGen/AArch64/arm64-fp-imm-size.ll | 4 +- test/CodeGen/AArch64/arm64-fp-imm.ll | 2 +- test/CodeGen/AArch64/f16-imm.ll | 14 +- test/CodeGen/AArch64/win_cst_pool.ll | 4 +- .../ARM/big-endian-neon-fp16-bitconv.ll | 168 +++++++++--------- test/CodeGen/ARM/constant-islands.ll | 2 +- test/CodeGen/ARM/constantfp.ll | 12 +- .../ARM/vecreduce-fadd-legalization-strict.ll | 8 +- .../ARM/vecreduce-fmul-legalization-strict.ll | 8 +- test/CodeGen/Mips/cconv/memory-layout.ll | 14 +- .../PowerPC/aix-lower-constant-pool-index.ll | 8 +- test/CodeGen/PowerPC/aix-xcoff-data.ll | 14 +- test/CodeGen/PowerPC/aix-xcoff-rodata.ll | 14 +- test/CodeGen/PowerPC/float-asmprint.ll | 10 +- test/CodeGen/PowerPC/mcm-12.ll | 6 +- test/CodeGen/PowerPC/mcm-4.ll | 12 +- test/CodeGen/PowerPC/ppcf128-endian.ll | 2 +- test/CodeGen/PowerPC/pr16573.ll | 2 +- test/CodeGen/SystemZ/fp-const-03.ll | 2 +- test/CodeGen/SystemZ/fp-const-04.ll | 2 +- test/CodeGen/SystemZ/fp-const-05.ll | 2 +- test/CodeGen/SystemZ/fp-const-06.ll | 2 +- test/CodeGen/SystemZ/fp-const-07.ll | 2 +- test/CodeGen/SystemZ/fp-const-08.ll | 4 +- test/CodeGen/SystemZ/fp-const-09.ll | 4 +- test/CodeGen/SystemZ/fp-const-10.ll | 2 +- test/CodeGen/SystemZ/fp-const-11.ll | 4 +- .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 4 +- .../LowOverheadLoops/mve-float-loops.ll | 6 +- test/CodeGen/Thumb2/aligned-constants.ll | 2 +- .../constant-islands-new-island-padding.ll | 2 +- test/CodeGen/Thumb2/mve-ctlz.ll | 4 +- test/CodeGen/Thumb2/mve-ctpop.ll | 2 +- test/CodeGen/Thumb2/mve-cttz.ll | 4 +- test/CodeGen/Thumb2/mve-phireg.ll | 4 +- test/CodeGen/Thumb2/mve-pred-build-var.ll | 4 +- test/CodeGen/Thumb2/mve-vecreduce-fadd.ll | 4 +- test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll | 16 +- test/CodeGen/WebAssembly/global.ll | 16 +- .../X86/broadcast-elm-cross-splat-vec.ll | 8 +- .../X86/copysign-constant-magnitude.ll | 56 +++--- test/CodeGen/X86/float-asmprint.ll | 34 ++-- test/CodeGen/X86/fp-immediate-shorten.ll | 2 +- test/CodeGen/X86/fp128-load.ll | 4 +- test/CodeGen/X86/pr13577.ll | 4 +- test/CodeGen/X86/pr40730.ll | 8 +- test/CodeGen/X86/vec-copysign.ll | 84 ++++----- test/CodeGen/X86/vec_uint_to_fp-fastmath.ll | 12 +- test/CodeGen/X86/vec_uint_to_fp.ll | 12 +- test/CodeGen/X86/win_cst_pool.ll | 12 +- .../X86/x86-setcc-int-to-fp-combine.ll | 16 +- 56 files changed, 370 insertions(+), 332 deletions(-) diff --git a/include/llvm/MC/MCExpr.h b/include/llvm/MC/MCExpr.h index eb2786501f8..a0b3e0ac097 100644 --- a/include/llvm/MC/MCExpr.h +++ b/include/llvm/MC/MCExpr.h @@ -131,6 +131,7 @@ inline raw_ostream &operator<<(raw_ostream &OS, const MCExpr &E) { class MCConstantExpr : public MCExpr { int64_t Value; bool PrintInHex = false; + unsigned SizeInBytes = 0; explicit MCConstantExpr(int64_t Value) : MCExpr(MCExpr::Constant, SMLoc()), Value(Value) {} @@ -139,18 +140,24 @@ class MCConstantExpr : public MCExpr { : MCExpr(MCExpr::Constant, SMLoc()), Value(Value), PrintInHex(PrintInHex) {} + MCConstantExpr(int64_t Value, bool PrintInHex, unsigned SizeInBytes) + : MCExpr(MCExpr::Constant, SMLoc()), Value(Value), PrintInHex(PrintInHex), + SizeInBytes(SizeInBytes) {} + public: /// \name Construction /// @{ static const MCConstantExpr *create(int64_t Value, MCContext &Ctx, - bool PrintInHex = false); + bool PrintInHex = false, + unsigned SizeInBytes = 0); /// @} /// \name Accessors /// @{ int64_t getValue() const { return Value; } + unsigned getSizeInBytes() const { return SizeInBytes; } bool useHexFormat() const { return PrintInHex; } diff --git a/include/llvm/MC/MCStreamer.h b/include/llvm/MC/MCStreamer.h index d8e8dce02e8..ff488f17fd8 100644 --- a/include/llvm/MC/MCStreamer.h +++ b/include/llvm/MC/MCStreamer.h @@ -663,6 +663,13 @@ public: EmitIntValue(Value, Size); } + /// Special case of EmitValue that avoids the client having to pass + /// in a MCExpr for constant integers & prints in Hex format for certain + /// modes, pads the field with leading zeros to Size width + virtual void EmitIntValueInHexWithPadding(uint64_t Value, unsigned Size) { + EmitIntValue(Value, Size); + } + virtual void EmitULEB128Value(const MCExpr *Value); virtual void EmitSLEB128Value(const MCExpr *Value); diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index d95baf9fae5..3881270cc5d 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -2563,17 +2563,17 @@ static void emitGlobalConstantFP(APFloat APF, Type *ET, AsmPrinter &AP) { int Chunk = API.getNumWords() - 1; if (TrailingBytes) - AP.OutStreamer->EmitIntValue(p[Chunk--], TrailingBytes); + AP.OutStreamer->EmitIntValueInHexWithPadding(p[Chunk--], TrailingBytes); for (; Chunk >= 0; --Chunk) - AP.OutStreamer->EmitIntValue(p[Chunk], sizeof(uint64_t)); + AP.OutStreamer->EmitIntValueInHexWithPadding(p[Chunk], sizeof(uint64_t)); } else { unsigned Chunk; for (Chunk = 0; Chunk < NumBytes / sizeof(uint64_t); ++Chunk) - AP.OutStreamer->EmitIntValue(p[Chunk], sizeof(uint64_t)); + AP.OutStreamer->EmitIntValueInHexWithPadding(p[Chunk], sizeof(uint64_t)); if (TrailingBytes) - AP.OutStreamer->EmitIntValue(p[Chunk], TrailingBytes); + AP.OutStreamer->EmitIntValueInHexWithPadding(p[Chunk], TrailingBytes); } // Emit the tail padding for the long double. diff --git a/lib/MC/MCAsmStreamer.cpp b/lib/MC/MCAsmStreamer.cpp index 0921cb8fe16..50d030f32c3 100644 --- a/lib/MC/MCAsmStreamer.cpp +++ b/lib/MC/MCAsmStreamer.cpp @@ -196,6 +196,7 @@ public: SMLoc Loc = SMLoc()) override; void EmitIntValue(uint64_t Value, unsigned Size) override; void EmitIntValueInHex(uint64_t Value, unsigned Size) override; + void EmitIntValueInHexWithPadding(uint64_t Value, unsigned Size) override; void EmitULEB128Value(const MCExpr *Value) override; @@ -973,6 +974,11 @@ void MCAsmStreamer::EmitIntValueInHex(uint64_t Value, unsigned Size) { EmitValue(MCConstantExpr::create(Value, getContext(), true), Size); } +void MCAsmStreamer::EmitIntValueInHexWithPadding(uint64_t Value, + unsigned Size) { + EmitValue(MCConstantExpr::create(Value, getContext(), true, Size), Size); +} + void MCAsmStreamer::EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) { assert(Size <= 8 && "Invalid size"); diff --git a/lib/MC/MCExpr.cpp b/lib/MC/MCExpr.cpp index 7f25fd4e90a..77c12c7d096 100644 --- a/lib/MC/MCExpr.cpp +++ b/lib/MC/MCExpr.cpp @@ -46,8 +46,25 @@ void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens) const { case MCExpr::Constant: { auto Value = cast(*this).getValue(); auto PrintInHex = cast(*this).useHexFormat(); + auto SizeInBytes = cast(*this).getSizeInBytes(); if (PrintInHex) - OS << "0x" << Twine::utohexstr(Value); + switch (SizeInBytes) { + default: + OS << "0x" << Twine::utohexstr(Value); + break; + case 1: + OS << format("0x%02" PRIx64, Value); + break; + case 2: + OS << format("0x%04" PRIx64, Value); + break; + case 4: + OS << format("0x%08" PRIx64, Value); + break; + case 8: + OS << format("0x%016" PRIx64, Value); + break; + } else OS << Value; return; @@ -167,8 +184,9 @@ const MCUnaryExpr *MCUnaryExpr::create(Opcode Opc, const MCExpr *Expr, } const MCConstantExpr *MCConstantExpr::create(int64_t Value, MCContext &Ctx, - bool PrintInHex) { - return new (Ctx) MCConstantExpr(Value, PrintInHex); + bool PrintInHex, + unsigned SizeInBytes) { + return new (Ctx) MCConstantExpr(Value, PrintInHex, SizeInBytes); } /* *** */ diff --git a/test/CodeGen/AArch64/arm64-fp-imm-size.ll b/test/CodeGen/AArch64/arm64-fp-imm-size.ll index c255537ee4c..5966fc65b0c 100644 --- a/test/CodeGen/AArch64/arm64-fp-imm-size.ll +++ b/test/CodeGen/AArch64/arm64-fp-imm-size.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s ; CHECK: literal8 -; CHECK: .quad 4614256656552045848 +; CHECK: .quad 0x400921fb54442d18 define double @foo() optsize { ; CHECK: _foo: ; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0@PAGE @@ -11,7 +11,7 @@ define double @foo() optsize { } ; CHECK: literal8 -; CHECK: .quad 137438953409 +; CHECK: .quad 0x0000001fffffffc define double @foo2() optsize { ; CHECK: _foo2: ; CHECK: adrp x[[REG:[0-9]+]], lCPI1_0@PAGE diff --git a/test/CodeGen/AArch64/arm64-fp-imm.ll b/test/CodeGen/AArch64/arm64-fp-imm.ll index 1921e9e1240..c50210c0b41 100644 --- a/test/CodeGen/AArch64/arm64-fp-imm.ll +++ b/test/CodeGen/AArch64/arm64-fp-imm.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s ; CHECK: literal8 -; CHECK: .quad 4614256656552045848 +; CHECK: .quad 0x400921fb54442d18 define double @foo() { ; CHECK: _foo: ; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0@PAGE diff --git a/test/CodeGen/AArch64/f16-imm.ll b/test/CodeGen/AArch64/f16-imm.ll index 84c27312d1e..edc070a1ea7 100644 --- a/test/CodeGen/AArch64/f16-imm.ll +++ b/test/CodeGen/AArch64/f16-imm.ll @@ -23,7 +23,7 @@ entry: ; CHECK-DAG-NEXT: ret ; CHECK-NOFP16: .[[LBL1:LCPI1_[0-9]]]: -; CHECK-NOFP16-NEXT: .hword 15360 // half 1 +; CHECK-NOFP16-NEXT: .hword 0x3c00 // half 1 ; CHECK-NOFP16-LABEL: Const1: ; CHECK-NOFP16: adrp x[[NUM:[0-9]+]], .[[LBL1]] ; CHECK-NOFP16-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL1]]] @@ -37,7 +37,7 @@ entry: ; CHECK-DAG-NEXT: ret ; CHECK-NOFP16: .[[LBL2:LCPI2_[0-9]]]: -; CHECK-NOFP16-NEXT: .hword 12288 // half 0.125 +; CHECK-NOFP16-NEXT: .hword 0x3000 // half 0.125 ; CHECK-NOFP16-LABEL: Const2: ; CHECK-NOFP16: adrp x[[NUM:[0-9]+]], .[[LBL2]] ; CHECK-NOFP16-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL2]]] @@ -51,7 +51,7 @@ entry: ; CHECK-DAG-NEXT: ret ; CHECK-NOFP16: .[[LBL3:LCPI3_[0-9]]]: -; CHECK-NOFP16-NEXT: .hword 20352 // half 30 +; CHECK-NOFP16-NEXT: .hword 0x4f80 // half 30 ; CHECK-NOFP16-LABEL: Const3: ; CHECK-NOFP16: adrp x[[NUM:[0-9]+]], .[[LBL3]] ; CHECK-NOFP16-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL3]]] @@ -66,7 +66,7 @@ entry: ; CHECK-DAG-NEXT: ret ; CHECK-NOFP16: .[[LBL4:LCPI4_[0-9]]]: -; CHECK-NOFP16-NEXT: .hword 20416 // half 31 +; CHECK-NOFP16-NEXT: .hword 0x4fc0 // half 31 ; CHECK-NOFP16-LABEL: Const4: ; CHECK-NOFP16: adrp x[[NUM:[0-9]+]], .[[LBL4]] ; CHECK-NOFP16-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL4]]] @@ -76,7 +76,7 @@ entry: ret half 0xH2FF0 } ; CHECK-ILLEGAL: .[[LBL5:LCPI5_[0-9]]]: -; CHECK-ILLEGAL-NEXT: .hword 12272 // half 0.12402 +; CHECK-ILLEGAL-NEXT: .hword 0x2ff0 // half 0.12402 ; CHECK-ILLEGAL-LABEL: Const5: ; CHECK-ILLEGAL: adrp x[[NUM:[0-9]+]], .[[LBL5]] ; CHECK-ILLEGAL-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL5]]] @@ -86,7 +86,7 @@ entry: ret half 0xH4FC1 } ; CHECK-ILLEGAL: .[[LBL6:LCPI6_[0-9]]]: -; CHECK-ILLEGAL-NEXT: .hword 20417 // half 31.016 +; CHECK-ILLEGAL-NEXT: .hword 0x4fc1 // half 31.016 ; CHECK-ILLEGAL-LABEL: Const6: ; CHECK-ILLEGAL: adrp x[[NUM:[0-9]+]], .[[LBL6]] ; CHECK-ILLEGAL-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL6]]] @@ -97,7 +97,7 @@ entry: ret half 0xH5000 } ; CHECK-ILLEGAL: .[[LBL7:LCPI7_[0-9]]]: -; CHECK-ILLEGAL-NEXT: .hword 20480 // half 32 +; CHECK-ILLEGAL-NEXT: .hword 0x5000 // half 32 ; CHECK-ILLEGAL-LABEL: Const7: ; CHECK-ILLEGAL: adrp x[[NUM:[0-9]+]], .[[LBL7]] ; CHECK-ILLEGAL-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL7]]] diff --git a/test/CodeGen/AArch64/win_cst_pool.ll b/test/CodeGen/AArch64/win_cst_pool.ll index c30ca4e6687..5d9eed408d4 100644 --- a/test/CodeGen/AArch64/win_cst_pool.ll +++ b/test/CodeGen/AArch64/win_cst_pool.ll @@ -8,7 +8,7 @@ define double @double() { ; CHECK-NEXT: .section .rdata,"dr",discard,__real@2000000000800001 ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: __real@2000000000800001: -; CHECK-NEXT: .xword 2305843009222082561 +; CHECK-NEXT: .xword 0x2000000000800001 ; CHECK: double: ; CHECK: adrp x8, __real@2000000000800001 ; CHECK-NEXT: ldr d0, [x8, __real@2000000000800001] @@ -17,7 +17,7 @@ define double @double() { ; MINGW: .section .rdata,"dr" ; MINGW-NEXT: .p2align 3 ; MINGW-NEXT: [[LABEL:\.LC.*]]: -; MINGW-NEXT: .xword 2305843009222082561 +; MINGW-NEXT: .xword 0x2000000000800001 ; MINGW: double: ; MINGW: adrp x8, [[LABEL]] ; MINGW-NEXT: ldr d0, [x8, [[LABEL]]] diff --git a/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll b/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll index b0674c0bbc1..86a69be5b4d 100644 --- a/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll +++ b/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll @@ -56,8 +56,8 @@ define void @conv_v2f32_to_v4f16( <2 x float> %a, <4 x half>* %store ) { ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI2_0: -; CHECK-NEXT: .long 3212836864 @ float -1 -; CHECK-NEXT: .long 1065353216 @ float 1 +; CHECK-NEXT: .long 0xbf800000 @ float -1 +; CHECK-NEXT: .long 0x3f800000 @ float 1 entry: %c = fadd <2 x float> %a, %v = bitcast <2 x float> %c to <4 x half> @@ -208,10 +208,10 @@ define void @conv_v4f32_to_v8f16( <4 x float> %a, <8 x half>* %store ) { ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI8_0: -; CHECK-NEXT: .long 3212836864 @ float -1 -; CHECK-NEXT: .long 1065353216 @ float 1 -; CHECK-NEXT: .long 3212836864 @ float -1 -; CHECK-NEXT: .long 1065353216 @ float 1 +; CHECK-NEXT: .long 0xbf800000 @ float -1 +; CHECK-NEXT: .long 0x3f800000 @ float 1 +; CHECK-NEXT: .long 0xbf800000 @ float -1 +; CHECK-NEXT: .long 0x3f800000 @ float 1 entry: %c = fadd <4 x float> %a, %v = bitcast <4 x float> %c to <8 x half> @@ -325,10 +325,10 @@ define void @conv_v4f16_to_i64( <4 x half> %a, i64* %store ) { ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI12_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 entry: %z = fadd <4 x half> %a, %y = bitcast <4 x half> %z to i64 @@ -352,10 +352,10 @@ define void @conv_v4f16_to_f64( <4 x half> %a, double* %store ) { ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI13_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 entry: %z = fadd <4 x half> %a, %y = bitcast <4 x half> %z to double @@ -381,10 +381,10 @@ define void @conv_v4f16_to_v2i32( <4 x half> %a, <2 x i32>* %store ) { ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI14_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 ; CHECK-NEXT: .LCPI14_1: ; CHECK-NEXT: .long 4294967295 @ 0xffffffff ; CHECK-NEXT: .long 1 @ 0x1 @@ -413,13 +413,13 @@ define void @conv_v4f16_to_v2f32( <4 x half> %a, <2 x float>* %store ) { ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI15_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 ; CHECK-NEXT: .LCPI15_1: -; CHECK-NEXT: .long 3212836864 @ float -1 -; CHECK-NEXT: .long 1065353216 @ float 1 +; CHECK-NEXT: .long 0xbf800000 @ float -1 +; CHECK-NEXT: .long 0x3f800000 @ float 1 entry: %z = fadd <4 x half> %a, %y = bitcast <4 x half> %z to <2 x float> @@ -444,10 +444,10 @@ define void @conv_v4f16_to_v4i16( <4 x half> %a, <4 x i16>* %store ) { ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI16_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 ; CHECK-NEXT: .LCPI16_1: ; CHECK-NEXT: .short 65535 @ 0xffff ; CHECK-NEXT: .short 1 @ 0x1 @@ -477,10 +477,10 @@ define void @conv_v4f16_to_v8f8( <4 x half> %a, <8 x i8>* %store ) { ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI17_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 entry: %z = fadd <4 x half> %a, %y = bitcast <4 x half> %z to <8 x i8> @@ -513,14 +513,14 @@ define void @conv_v8f16_to_i128( <8 x half> %a, i128* %store ) { ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI18_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 entry: %z = fadd <8 x half> %a, %y = bitcast <8 x half> %z to i128 @@ -547,14 +547,14 @@ define void @conv_v8f16_to_v2f64( <8 x half> %a, <2 x double>* %store ) { ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI19_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 entry: %z = fadd <8 x half> %a, %y = bitcast <8 x half> %z to <2 x double> @@ -582,14 +582,14 @@ define void @conv_v8f16_to_v4i32( <8 x half> %a, <4 x i32>* %store ) { ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI20_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 ; CHECK-NEXT: .LCPI20_1: ; CHECK-NEXT: .long 4294967295 @ 0xffffffff ; CHECK-NEXT: .long 1 @ 0x1 @@ -622,19 +622,19 @@ define void @conv_v8f16_to_v4f32( <8 x half> %a, <4 x float>* %store ) { ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI21_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 ; CHECK-NEXT: .LCPI21_1: -; CHECK-NEXT: .long 3212836864 @ float -1 -; CHECK-NEXT: .long 1065353216 @ float 1 -; CHECK-NEXT: .long 3212836864 @ float -1 -; CHECK-NEXT: .long 1065353216 @ float 1 +; CHECK-NEXT: .long 0xbf800000 @ float -1 +; CHECK-NEXT: .long 0x3f800000 @ float 1 +; CHECK-NEXT: .long 0xbf800000 @ float -1 +; CHECK-NEXT: .long 0x3f800000 @ float 1 entry: %z = fadd <8 x half> %a, %y = bitcast <8 x half> %z to <4 x float> @@ -661,14 +661,14 @@ define void @conv_v8f16_to_v8i16( <8 x half> %a, <8 x i16>* %store ) { ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI22_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 ; CHECK-NEXT: .LCPI22_1: ; CHECK-NEXT: .short 65535 @ 0xffff ; CHECK-NEXT: .short 1 @ 0x1 @@ -703,14 +703,14 @@ define void @conv_v8f16_to_v8f8( <8 x half> %a, <16 x i8>* %store ) { ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI23_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 entry: %z = fadd <8 x half> %a, %y = bitcast <8 x half> %z to <16 x i8> diff --git a/test/CodeGen/ARM/constant-islands.ll b/test/CodeGen/ARM/constant-islands.ll index afa4b85ff64..d530b0f42a4 100644 --- a/test/CodeGen/ARM/constant-islands.ll +++ b/test/CodeGen/ARM/constant-islands.ll @@ -6,7 +6,7 @@ define void @test_no_duplicate_branches(float %in) { ; CHECK: b .LBB ; CHECK-NOT: b .LBB ; CHECK: [[CONST]]: -; CHECK-NEXT: .long 1150963712 +; CHECK-NEXT: .long 0x449a5000 %tst = fcmp oeq float %in, 1234.5 diff --git a/test/CodeGen/ARM/constantfp.ll b/test/CodeGen/ARM/constantfp.ll index f825061d116..d45d3dcfc1b 100644 --- a/test/CodeGen/ARM/constantfp.ll +++ b/test/CodeGen/ARM/constantfp.ll @@ -198,8 +198,8 @@ define arm_aapcs_vfpcc float @lower_fpconst_select(float %f) { ; CHECK-NO-XO: vldr {{s[0-9]+}}, {{[[]}}[[REG]]{{[]]}} ; CHECK-NO-XO-NOT: .rodata ; CHECK-NO-XO: [[LABEL]]: -; CHECK-NO-XO: .long 1335165689 -; CHECK-NO-XO: .long 1307470632 +; CHECK-NO-XO: .long 0x4f9502f9 +; CHECK-NO-XO: .long 0x4dee6b28 ; CHECK-XO-FLOAT-LABEL: lower_fpconst_select ; CHECK-XO-FLOAT: movw [[REG:r[0-9]+]], :lower16:[[LABEL:.?LCP[0-9]+_[0-9]+]] @@ -208,8 +208,8 @@ define arm_aapcs_vfpcc float @lower_fpconst_select(float %f) { ; CHECK-XO-FLOAT: .rodata ; CHECK-XO-FLOAT-NOT: .text ; CHECK-XO-FLOAT: [[LABEL]]: -; CHECK-XO-FLOAT: .long 1335165689 -; CHECK-XO-FLOAT: .long 1307470632 +; CHECK-XO-FLOAT: .long 0x4f9502f9 +; CHECK-XO-FLOAT: .long 0x4dee6b28 ; CHECK-XO-ROPI-LABEL: lower_fpconst_select ; CHECK-XO-ROPI: movw [[REG:r[0-9]+]], :lower16:([[LABEL1:.?LCP[0-9]+_[0-9]+]]-([[LABEL2:.?LPC[0-9]+_[0-9]+]]+4)) @@ -219,8 +219,8 @@ define arm_aapcs_vfpcc float @lower_fpconst_select(float %f) { ; CHECK-XO-ROPI: .rodata ; CHECK-XO-ROPI-NOT: .text ; CHECK-XO-ROPI: [[LABEL1]]: -; CHECK-XO-ROPI: .long 1335165689 -; CHECK-XO-ROPI: .long 1307470632 +; CHECK-XO-ROPI: .long 0x4f9502f9 +; CHECK-XO-ROPI: .long 0x4dee6b28 %cmp = fcmp nnan oeq float %f, 0.000000e+00 %sel = select i1 %cmp, float 5.000000e+08, float 5.000000e+09 diff --git a/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll b/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll index f2f4ee28966..28a6fef7d7b 100644 --- a/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll +++ b/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll @@ -26,7 +26,7 @@ define half @test_v1f16(<1 x half> %a) nounwind { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half 0.0, <1 x half> %a) ret half %b } @@ -42,7 +42,7 @@ define float @test_v1f32(<1 x float> %a) nounwind { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI1_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float 0.0, <1 x float> %a) ret float %b } @@ -93,7 +93,7 @@ define float @test_v3f32(<3 x float> %a) nounwind { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI4_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float 0.0, <3 x float> %a) ret float %b } @@ -160,7 +160,7 @@ define float @test_v16f32(<16 x float> %a) nounwind { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI6_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float 0.0, <16 x float> %a) ret float %b } diff --git a/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll b/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll index 396cbc806e5..9d595b9a296 100644 --- a/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll +++ b/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll @@ -26,7 +26,7 @@ define half @test_v1f16(<1 x half> %a) nounwind { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call half @llvm.experimental.vector.reduce.v2.fmul.f16.v1f16(half 0.0, <1 x half> %a) ret half %b } @@ -42,7 +42,7 @@ define float @test_v1f32(<1 x float> %a) nounwind { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI1_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v1f32(float 0.0, <1 x float> %a) ret float %b } @@ -93,7 +93,7 @@ define float @test_v3f32(<3 x float> %a) nounwind { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI4_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v3f32(float 0.0, <3 x float> %a) ret float %b } @@ -160,7 +160,7 @@ define float @test_v16f32(<16 x float> %a) nounwind { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI6_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v16f32(float 0.0, <16 x float> %a) ret float %b } diff --git a/test/CodeGen/Mips/cconv/memory-layout.ll b/test/CodeGen/Mips/cconv/memory-layout.ll index e992169f6b6..2c7a19764aa 100644 --- a/test/CodeGen/Mips/cconv/memory-layout.ll +++ b/test/CodeGen/Mips/cconv/memory-layout.ll @@ -44,7 +44,7 @@ ; ALL: .p2align 2 ; ALL-LABEL: float: -; ALL: .4byte 1065353216 +; ALL: .4byte 0x3f800000 ; ALL: .size float, 4 ; ALL: .p2align 3 @@ -54,7 +54,7 @@ ; ALL: .p2align 3 ; ALL-LABEL: double: -; ALL: .8byte 4607182418800017408 +; ALL: .8byte 0x3ff0000000000000 ; ALL: .size double, 8 ; O32: .p2align 2 @@ -95,8 +95,8 @@ ; ALL: .p2align 2 ; ALL-LABEL: float_array: -; ALL: .4byte 1065353216 -; ALL: .4byte 1073741824 +; ALL: .4byte 0x3f800000 +; ALL: .4byte 0x40000000 ; ALL: .size float_array, 8 ; ALL: .p2align 3 @@ -107,8 +107,8 @@ ; ALL: .p2align 3 ; ALL-LABEL: double_array: -; ALL: .8byte 4607182418800017408 -; ALL: .8byte 4611686018427387904 +; ALL: .8byte 0x3ff0000000000000 +; ALL: .8byte 0x4000000000000000 ; ALL: .size double_array, 16 ; O32: .p2align 2 @@ -132,7 +132,7 @@ ; ALL-LABEL: mixed: ; ALL: .byte 1 ; ALL: .space 7 -; ALL: .8byte 4607182418800017408 +; ALL: .8byte 0x3ff0000000000000 ; ALL: .2byte 515 ; ALL: .space 6 ; ALL: .size mixed, 24 diff --git a/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll b/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll index 1db8a55fb28..a054eabd187 100644 --- a/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll +++ b/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll @@ -48,7 +48,7 @@ entry: ; 32SMALL-ASM: .csect .rodata[RO] ; 32SMALL-ASM: .align 2 ; 32SMALL-ASM: .LCPI0_0: -; 32SMALL-ASM: .long 1085276160 +; 32SMALL-ASM: .long 0x40b00000 ; 32SMALL-ASM: .test_float: ; 32SMALL-ASM: lwz [[REG1:[0-9]+]], LC0(2) ; 32SMALL-ASM: lfs 1, 0([[REG1]]) @@ -57,7 +57,7 @@ entry: ; 32LARGE-ASM: .csect .rodata[RO] ; 32LARGE-ASM: .align 2 ; 32LARGE-ASM: .LCPI0_0: -; 32LARGE-ASM: .long 1085276160 +; 32LARGE-ASM: .long 0x40b00000 ; 32LARGE-ASM: .test_float: ; 32LARGE-ASM: addis [[REG1:[0-9]+]], LC0@u(2) ; 32LARGE-ASM: lwz [[REG2:[0-9]+]], LC0@l([[REG1]]) @@ -67,7 +67,7 @@ entry: ; 64SMALL-ASM: .csect .rodata[RO] ; 64SMALL-ASM: .align 2 ; 64SMALL-ASM: .LCPI0_0: -; 64SMALL-ASM: .long 1085276160 +; 64SMALL-ASM: .long 0x40b00000 ; 64SMALL-ASM: .test_float: ; 64SMALL-ASM: ld [[REG1:[0-9]+]], LC0(2) ; 64SMALL-ASM: lfs 1, 0([[REG1]]) @@ -76,7 +76,7 @@ entry: ; 64LARGE-ASM: .csect .rodata[RO] ; 64LARGE-ASM: .align 2 ; 64LARGE-ASM: .LCPI0_0: -; 64LARGE-ASM: .long 1085276160 +; 64LARGE-ASM: .long 0x40b00000 ; 64LARGE-ASM: .test_float: ; 64LARGE-ASM: addis [[REG1:[0-9]+]], LC0@u(2) ; 64LARGE-ASM: ld [[REG2:[0-9]+]], LC0@l([[REG1]]) diff --git a/test/CodeGen/PowerPC/aix-xcoff-data.ll b/test/CodeGen/PowerPC/aix-xcoff-data.ll index c6a31ae8078..d911383dcff 100644 --- a/test/CodeGen/PowerPC/aix-xcoff-data.ll +++ b/test/CodeGen/PowerPC/aix-xcoff-data.ll @@ -60,17 +60,17 @@ ; CHECK: .globl fvar ; CHECK-NEXT: .align 2 ; CHECK-NEXT: fvar: -; CHECK-NEXT: .long 1145569280 +; CHECK-NEXT: .long 0x44480000 ; CHECK: .globl dvar ; CHECK-NEXT: .align 3 ; CHECK-NEXT: dvar: -; CHECK-NEXT: .llong 4651127699538968576 +; CHECK-NEXT: .llong 0x408c200000000000 ; CHECK: .globl over_aligned ; CHECK-NEXT: .align 5 ; CHECK-NEXT: over_aligned: -; CHECK-NEXT: .llong 4651127699538968576 +; CHECK-NEXT: .llong 0x408c200000000000 ; CHECK: .globl chrarray ; CHECK-NEXT: chrarray: @@ -82,10 +82,10 @@ ; CHECK: .globl dblarr ; CHECK-NEXT: .align 3 ; CHECK-NEXT: dblarr: -; CHECK-NEXT: .llong 4607182418800017408 -; CHECK-NEXT: .llong 4611686018427387904 -; CHECK-NEXT: .llong 4613937818241073152 -; CHECK-NEXT: .llong 4616189618054758400 +; CHECK-NEXT: .llong 0x3ff0000000000000 +; CHECK-NEXT: .llong 0x4000000000000000 +; CHECK-NEXT: .llong 0x4008000000000000 +; CHECK-NEXT: .llong 0x4010000000000000 ; CHECK: .globl d_0 ; CHECK-NEXT: .align 3 diff --git a/test/CodeGen/PowerPC/aix-xcoff-rodata.ll b/test/CodeGen/PowerPC/aix-xcoff-rodata.ll index 769a9c2cc46..e846b39f07c 100644 --- a/test/CodeGen/PowerPC/aix-xcoff-rodata.ll +++ b/test/CodeGen/PowerPC/aix-xcoff-rodata.ll @@ -36,15 +36,15 @@ ; CHECK-NEXT: .globl const_fvar ; CHECK-NEXT: .align 2 ; CHECK-NEXT: const_fvar: -; CHECK-NEXT: .long 1145569280 +; CHECK-NEXT: .long 0x44480000 ; CHECK-NEXT: .globl const_dvar ; CHECK-NEXT: .align 3 ; CHECK-NEXT: const_dvar: -; CHECK-NEXT: .llong 4651127699538968576 +; CHECK-NEXT: .llong 0x408c200000000000 ; CHECK-NEXT: .globl const_over_aligned ; CHECK-NEXT: .align 5 ; CHECK-NEXT: const_over_aligned: -; CHECK-NEXT: .llong 4651127699538968576 +; CHECK-NEXT: .llong 0x408c200000000000 ; CHECK-NEXT: .globl const_chrarray ; CHECK-NEXT: const_chrarray: ; CHECK-NEXT: .byte 97 @@ -54,10 +54,10 @@ ; CHECK-NEXT: .globl const_dblarr ; CHECK-NEXT: .align 3 ; CHECK-NEXT: const_dblarr: -; CHECK-NEXT: .llong 4607182418800017408 -; CHECK-NEXT: .llong 4611686018427387904 -; CHECK-NEXT: .llong 4613937818241073152 -; CHECK-NEXT: .llong 4616189618054758400 +; CHECK-NEXT: .llong 0x3ff0000000000000 +; CHECK-NEXT: .llong 0x4000000000000000 +; CHECK-NEXT: .llong 0x4008000000000000 +; CHECK-NEXT: .llong 0x4010000000000000 ; OBJ: File: {{.*}}aix-xcoff-rodata.ll.tmp.o diff --git a/test/CodeGen/PowerPC/float-asmprint.ll b/test/CodeGen/PowerPC/float-asmprint.ll index f4643d6eafb..bdbca29369c 100644 --- a/test/CodeGen/PowerPC/float-asmprint.ll +++ b/test/CodeGen/PowerPC/float-asmprint.ll @@ -11,24 +11,24 @@ @var16 = global half -0.0, align 2 ; CHECK: var128: -; CHECK-NEXT: .quad -9223372036854775808 # fp128 -0 +; CHECK-NEXT: .quad 0x8000000000000000 # fp128 -0 ; CHECK-NEXT: .quad 0 ; CHECK-NEXT: .size ; CHECK: varppc128: -; CHECK-NEXT: .quad -9223372036854775808 # ppc_fp128 -0 +; CHECK-NEXT: .quad 0x8000000000000000 # ppc_fp128 -0 ; CHECK-NEXT: .quad 0 ; CHECK-NEXT: .size ; CHECK: var64: -; CHECK-NEXT: .quad -9223372036854775808 # double -0 +; CHECK-NEXT: .quad 0x8000000000000000 # double -0 ; CHECK-NEXT: .size ; CHECK: var32: -; CHECK-NEXT: .long 2147483648 # float -0 +; CHECK-NEXT: .long 0x80000000 # float -0 ; CHECK-NEXT: .size ; CHECK: var16: -; CHECK-NEXT: .short 32768 # half -0 +; CHECK-NEXT: .short 0x8000 # half -0 ; CHECK-NEXT: .size diff --git a/test/CodeGen/PowerPC/mcm-12.ll b/test/CodeGen/PowerPC/mcm-12.ll index f64b62ee412..576051cff36 100644 --- a/test/CodeGen/PowerPC/mcm-12.ll +++ b/test/CodeGen/PowerPC/mcm-12.ll @@ -17,19 +17,19 @@ entry: } ; CHECK: [[VAR:[a-z0-9A-Z_.]+]]: -; CHECK: .quad 4562098671269285104 +; CHECK: .quad 0x3f4fd4920b498cf0 ; CHECK-LABEL: test_double_const: ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) ; CHECK-VSX: [[VAR:[a-z0-9A-Z_.]+]]: -; CHECK-VSX: .quad 4562098671269285104 +; CHECK-VSX: .quad 0x3f4fd4920b498cf0 ; CHECK-VSX-LABEL: test_double_const: ; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; CHECK-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l({{[0-9]+}}) ; CHECK-P9: [[VAR:[a-z0-9A-Z_.]+]]: -; CHECK-P9: .quad 4562098671269285104 +; CHECK-P9: .quad 0x3f4fd4920b498cf0 ; CHECK-P9-LABEL: test_double_const: ; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; CHECK-P9: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) diff --git a/test/CodeGen/PowerPC/mcm-4.ll b/test/CodeGen/PowerPC/mcm-4.ll index 9173e1fceec..96e90e0e4ff 100644 --- a/test/CodeGen/PowerPC/mcm-4.ll +++ b/test/CodeGen/PowerPC/mcm-4.ll @@ -23,41 +23,41 @@ entry: } ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]: -; MEDIUM: .quad 4562098671269285104 +; MEDIUM: .quad 0x3f4fd4920b498cf0 ; MEDIUM-LABEL: test_double_const: ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]]) ; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]: -; MEDIUM-VSX: .quad 4562098671269285104 +; MEDIUM-VSX: .quad 0x3f4fd4920b498cf0 ; MEDIUM-VSX-LABEL: test_double_const: ; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]: -; LARGE: .quad 4562098671269285104 +; LARGE: .quad 0x3f4fd4920b498cf0 ; LARGE-LABEL: test_double_const: ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE: lfd {{[0-9]+}}, 0([[REG2]]) ; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]: -; LARGE-VSX: .quad 4562098671269285104 +; LARGE-VSX: .quad 0x3f4fd4920b498cf0 ; LARGE-VSX-LABEL: test_double_const: ; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE-VSX: lfdx {{[0-9]+}}, 0, [[REG2]] ; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]: -; MEDIUM-P9: .quad 4562098671269285104 +; MEDIUM-P9: .quad 0x3f4fd4920b498cf0 ; MEDIUM-P9-LABEL: test_double_const: ; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]]) ; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]: -; LARGE-P9: .quad 4562098671269285104 +; LARGE-P9: .quad 0x3f4fd4920b498cf0 ; LARGE-P9-LABEL: test_double_const: ; LARGE-P9: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE-P9: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) diff --git a/test/CodeGen/PowerPC/ppcf128-endian.ll b/test/CodeGen/PowerPC/ppcf128-endian.ll index 851942caf4c..c48ba256094 100644 --- a/test/CodeGen/PowerPC/ppcf128-endian.ll +++ b/test/CodeGen/PowerPC/ppcf128-endian.ll @@ -39,7 +39,7 @@ entry: ret void } ; CHECK: .LCPI[[LC:[0-9]+]]_0: -; CHECK: .long 1065353216 +; CHECK: .long 0x3f800000 ; CHECK: .LCPI[[LC]]_1: ; CHECK: .long 0 ; CHECK: @caller_const diff --git a/test/CodeGen/PowerPC/pr16573.ll b/test/CodeGen/PowerPC/pr16573.ll index aab903d2684..a5538fc8b8e 100644 --- a/test/CodeGen/PowerPC/pr16573.ll +++ b/test/CodeGen/PowerPC/pr16573.ll @@ -7,5 +7,5 @@ define double @test() { ret double %1 } -; CHECK: .quad -9111018957755033591 +; CHECK: .quad 0x818f2887b9295809 diff --git a/test/CodeGen/SystemZ/fp-const-03.ll b/test/CodeGen/SystemZ/fp-const-03.ll index b2ae94db0b7..b2c709f8490 100644 --- a/test/CodeGen/SystemZ/fp-const-03.ll +++ b/test/CodeGen/SystemZ/fp-const-03.ll @@ -9,6 +9,6 @@ define float @f1() { ; CHECK: le %f0, 0([[REGISTER]]) ; CHECK: br %r14 ; -; CONST: .long 1065353217 +; CONST: .long 0x3f800001 ret float 0x3ff0000020000000 } diff --git a/test/CodeGen/SystemZ/fp-const-04.ll b/test/CodeGen/SystemZ/fp-const-04.ll index d5526884dc6..44817c2c67e 100644 --- a/test/CodeGen/SystemZ/fp-const-04.ll +++ b/test/CodeGen/SystemZ/fp-const-04.ll @@ -10,6 +10,6 @@ define double @f1() { ; CHECK: ldeb %f0, 0([[REGISTER]]) ; CHECK: br %r14 ; -; CONST: .long 1065353217 +; CONST: .long 0x3f800001 ret double 0x3ff0000020000000 } diff --git a/test/CodeGen/SystemZ/fp-const-05.ll b/test/CodeGen/SystemZ/fp-const-05.ll index d81e3db91f4..c7e3d124a37 100644 --- a/test/CodeGen/SystemZ/fp-const-05.ll +++ b/test/CodeGen/SystemZ/fp-const-05.ll @@ -12,7 +12,7 @@ define void @f1(fp128 *%x) { ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 ; -; CONST: .long 1065353217 +; CONST: .long 0x3f800001 store fp128 0xL00000000000000003fff000002000000, fp128 *%x ret void } diff --git a/test/CodeGen/SystemZ/fp-const-06.ll b/test/CodeGen/SystemZ/fp-const-06.ll index 088810ba8e4..5c97ac88964 100644 --- a/test/CodeGen/SystemZ/fp-const-06.ll +++ b/test/CodeGen/SystemZ/fp-const-06.ll @@ -9,6 +9,6 @@ define double @f1() { ; CHECK: ld %f0, 0([[REGISTER]]) ; CHECK: br %r14 ; -; CONST: .quad 4607182419068452864 +; CONST: .quad 0x3ff0000010000000 ret double 0x3ff0000010000000 } diff --git a/test/CodeGen/SystemZ/fp-const-07.ll b/test/CodeGen/SystemZ/fp-const-07.ll index 87e8f68b372..85f50b5a75a 100644 --- a/test/CodeGen/SystemZ/fp-const-07.ll +++ b/test/CodeGen/SystemZ/fp-const-07.ll @@ -12,7 +12,7 @@ define void @f1(fp128 *%x) { ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 ; -; CONST: .quad 4607182419068452864 +; CONST: .quad 0x3ff0000010000000 store fp128 0xL00000000000000003fff000001000000, fp128 *%x ret void } diff --git a/test/CodeGen/SystemZ/fp-const-08.ll b/test/CodeGen/SystemZ/fp-const-08.ll index 8845adbebc5..5ae94cd116f 100644 --- a/test/CodeGen/SystemZ/fp-const-08.ll +++ b/test/CodeGen/SystemZ/fp-const-08.ll @@ -14,8 +14,8 @@ define void @f1(fp128 *%x) { ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 ; -; CONST: .quad 4611404543450677248 -; CONST: .quad 576460752303423488 +; CONST: .quad 0x3fff000000000000 +; CONST: .quad 0x0800000000000000 store fp128 0xL08000000000000003fff000000000000, fp128 *%x ret void } diff --git a/test/CodeGen/SystemZ/fp-const-09.ll b/test/CodeGen/SystemZ/fp-const-09.ll index 0c7d726e9d0..940c2c5db4d 100644 --- a/test/CodeGen/SystemZ/fp-const-09.ll +++ b/test/CodeGen/SystemZ/fp-const-09.ll @@ -13,8 +13,8 @@ define void @f1(fp128 *%x) { ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 ; -; CONST: .quad 4611404543450677248 -; CONST: .quad 1 +; CONST: .quad 0x3fff000000000000 +; CONST: .quad 0x0000000000000001 store fp128 0xL00000000000000013fff000000000000, fp128 *%x ret void } diff --git a/test/CodeGen/SystemZ/fp-const-10.ll b/test/CodeGen/SystemZ/fp-const-10.ll index cb00eb64a0d..f8c88d0551d 100644 --- a/test/CodeGen/SystemZ/fp-const-10.ll +++ b/test/CodeGen/SystemZ/fp-const-10.ll @@ -6,7 +6,7 @@ ; converstion to QNaN. define double @f1() { ; CHECK-LABEL: .LCPI0_0 -; CHECK: .quad 9219994337134247936 +; CHECK: .quad 0x7ff4000000000000 ; CHECK-LABEL: f1: ; CHECK: larl %r1, .LCPI0_0 ; CHECK-NOT: ldeb %f0, 0(%r1) diff --git a/test/CodeGen/SystemZ/fp-const-11.ll b/test/CodeGen/SystemZ/fp-const-11.ll index ff8289d4fad..7ca225e6f1c 100644 --- a/test/CodeGen/SystemZ/fp-const-11.ll +++ b/test/CodeGen/SystemZ/fp-const-11.ll @@ -33,8 +33,8 @@ define void @f3(fp128 *%x) { ; CHECK: vl [[REG:%v[0-9]+]], 0([[REGISTER]]) ; CHECK: vst [[REG]], 0(%r2) ; CHECK: br %r14 -; CONST: .quad 4611404543484231680 -; CONST: .quad 0 +; CONST: .quad 0x3fff000002000000 +; CONST: .quad 0x0 store fp128 0xL00000000000000003fff000002000000, fp128 *%x ret void } diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll b/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll index b1d2accf507..3a17b3de228 100644 --- a/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll +++ b/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll @@ -255,7 +255,7 @@ define arm_aapcs_vfpcc float @fast_float_mac(float* nocapture readonly %b, float ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.5: ; CHECK-NEXT: .LCPI1_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %cmp8 = icmp eq i32 %N, 0 br i1 %cmp8, label %for.cond.cleanup, label %vector.ph @@ -532,7 +532,7 @@ define arm_aapcs_vfpcc float @fast_float_half_mac(half* nocapture readonly %b, h ; CHECK-NEXT: .long 2 @ 0x2 ; CHECK-NEXT: .long 3 @ 0x3 ; CHECK-NEXT: .LCPI2_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %cmp8 = icmp eq i32 %N, 0 br i1 %cmp8, label %for.cond.cleanup, label %vector.ph diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll b/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll index a71dbd8dac9..ebd93db9bdb 100644 --- a/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll +++ b/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll @@ -1535,7 +1535,7 @@ define arm_aapcs_vfpcc float @half_half_mac(half* nocapture readonly %a, half* n ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.10: ; CHECK-NEXT: .LCPI9_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %cmp8 = icmp eq i32 %N, 0 br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader @@ -1692,7 +1692,7 @@ define arm_aapcs_vfpcc float @half_half_acc(half* nocapture readonly %a, half* n ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.10: ; CHECK-NEXT: .LCPI10_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %cmp9 = icmp eq i32 %N, 0 br i1 %cmp9, label %for.cond.cleanup, label %for.body.preheader @@ -1858,7 +1858,7 @@ define arm_aapcs_vfpcc float @half_short_mac(half* nocapture readonly %a, i16* n ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.10: ; CHECK-NEXT: .LCPI11_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %cmp10 = icmp eq i32 %N, 0 br i1 %cmp10, label %for.cond.cleanup, label %for.body.preheader diff --git a/test/CodeGen/Thumb2/aligned-constants.ll b/test/CodeGen/Thumb2/aligned-constants.ll index df3b19dbb5c..27eaf4744be 100644 --- a/test/CodeGen/Thumb2/aligned-constants.ll +++ b/test/CodeGen/Thumb2/aligned-constants.ll @@ -13,7 +13,7 @@ target triple = "thumbv7-apple-ios" ; CHECK: .long 2370821947 ; CHECK: .long 1080815255 ; CHECK: LCPI -; CHECK: .long 1123477881 +; CHECK: .long 0x42f6e979 define void @func(float* nocapture %x, double* nocapture %y) nounwind ssp { entry: %0 = load float, float* %x, align 4 diff --git a/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll b/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll index c2a2c068ca4..428ef739558 100644 --- a/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll +++ b/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll @@ -10,7 +10,7 @@ declare i32 @llvm.arm.space(i32, i32) ; Check that the constant island pass moves the float constant pool entry inside ; the function. -; CHECK: .long 1067320814 @ float 1.23455596 +; CHECK: .long 0x3f9e05ee @ float 1.23455596 ; CHECK: {{.*}} %do.end define i32 @testpadding(i32 %a) { diff --git a/test/CodeGen/Thumb2/mve-ctlz.ll b/test/CodeGen/Thumb2/mve-ctlz.ll index 0645fadd2c6..5e866a1b0b8 100644 --- a/test/CodeGen/Thumb2/mve-ctlz.ll +++ b/test/CodeGen/Thumb2/mve-ctlz.ll @@ -31,7 +31,7 @@ define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 0) ret <2 x i64> %0 @@ -97,7 +97,7 @@ define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_1_t(<2 x i64> %src){ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI4_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 1) ret <2 x i64> %0 diff --git a/test/CodeGen/Thumb2/mve-ctpop.ll b/test/CodeGen/Thumb2/mve-ctpop.ll index d289d371223..d6d215cc7ed 100644 --- a/test/CodeGen/Thumb2/mve-ctpop.ll +++ b/test/CodeGen/Thumb2/mve-ctpop.ll @@ -58,7 +58,7 @@ define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %0 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %src) ret <2 x i64> %0 diff --git a/test/CodeGen/Thumb2/mve-cttz.ll b/test/CodeGen/Thumb2/mve-cttz.ll index d1034fb2aac..3a77883babf 100644 --- a/test/CodeGen/Thumb2/mve-cttz.ll +++ b/test/CodeGen/Thumb2/mve-cttz.ll @@ -35,7 +35,7 @@ define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_0_t(<2 x i64> %src){ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 0) ret <2 x i64> %0 @@ -111,7 +111,7 @@ define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_1_t(<2 x i64> %src){ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI4_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 1) ret <2 x i64> %0 diff --git a/test/CodeGen/Thumb2/mve-phireg.ll b/test/CodeGen/Thumb2/mve-phireg.ll index dde14da7e75..955e72c77a5 100644 --- a/test/CodeGen/Thumb2/mve-phireg.ll +++ b/test/CodeGen/Thumb2/mve-phireg.ll @@ -227,9 +227,9 @@ define dso_local i32 @e() #0 { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.2: ; CHECK-NEXT: .LCPI1_0: -; CHECK-NEXT: .long 4 @ float 5.60519386E-45 +; CHECK-NEXT: .long 0x00000004 @ float 5.60519386E-45 ; CHECK-NEXT: .LCPI1_1: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %f = alloca i16, align 2 %g = alloca [3 x [8 x [4 x i16*]]], align 4 diff --git a/test/CodeGen/Thumb2/mve-pred-build-var.ll b/test/CodeGen/Thumb2/mve-pred-build-var.ll index 46b418daf3b..ae2ee6a94e1 100644 --- a/test/CodeGen/Thumb2/mve-pred-build-var.ll +++ b/test/CodeGen/Thumb2/mve-pred-build-var.ll @@ -191,7 +191,7 @@ define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a, ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI9_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %c = icmp ult i32 %s, %t %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 0 @@ -217,7 +217,7 @@ define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI10_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %c = icmp ult i32 %s, %t %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 1 diff --git a/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll b/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll index 21c2299b116..9d02a1c817c 100644 --- a/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll +++ b/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll @@ -14,7 +14,7 @@ define arm_aapcs_vfpcc float @fadd_v2f32(<2 x float> %x, float %y) { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %z = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v2f32(float %y, <2 x float> %x) ret float %z @@ -79,7 +79,7 @@ define arm_aapcs_vfpcc void @fadd_v4f16(<4 x half> %x, half* %yy) { ; CHECK-NEXT: .p2align 1 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI3_0: -; CHECK-NEXT: .short 0 @ half 0 +; CHECK-NEXT: .short 0x0000 @ half 0 entry: %y = load half, half* %yy %z = call fast half @llvm.experimental.vector.reduce.v2.fadd.f16.v4f16(half %y, <4 x half> %x) diff --git a/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll b/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll index 26541e6ec2b..0b6f18d28d4 100644 --- a/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll +++ b/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll @@ -14,7 +14,7 @@ define arm_aapcs_vfpcc float @fmin_v2f32(<2 x float> %x) { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 2139095040 @ float +Inf +; CHECK-NEXT: .long 0x7f800000 @ float +Inf entry: %z = call fast float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x) ret float %z @@ -83,7 +83,7 @@ define arm_aapcs_vfpcc half @fmin_v4f16(<4 x half> %x) { ; CHECK-NEXT: .p2align 1 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI3_0: -; CHECK-NEXT: .short 31744 @ half +Inf +; CHECK-NEXT: .short 0x7c00 @ half +Inf entry: %z = call fast half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x) ret half %z @@ -522,7 +522,7 @@ define arm_aapcs_vfpcc float @fmin_v2f32_acc(<2 x float> %x, float %y) { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI18_0: -; CHECK-NEXT: .long 2139095040 @ float +Inf +; CHECK-NEXT: .long 0x7f800000 @ float +Inf entry: %z = call fast float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x) %c = fcmp fast olt float %y, %z @@ -601,7 +601,7 @@ define arm_aapcs_vfpcc void @fmin_v4f16_acc(<4 x half> %x, half* %yy) { ; CHECK-NEXT: .p2align 1 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI21_0: -; CHECK-NEXT: .short 31744 @ half +Inf +; CHECK-NEXT: .short 0x7c00 @ half +Inf entry: %y = load half, half* %yy %z = call fast half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x) @@ -1136,7 +1136,7 @@ define arm_aapcs_vfpcc float @fmax_v2f32(<2 x float> %x) { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI36_0: -; CHECK-NEXT: .long 4286578688 @ float -Inf +; CHECK-NEXT: .long 0xff800000 @ float -Inf entry: %z = call fast float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x) ret float %z @@ -1204,7 +1204,7 @@ define arm_aapcs_vfpcc half @fmax_v4f16(<4 x half> %x) { ; CHECK-NEXT: .p2align 1 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI39_0: -; CHECK-NEXT: .short 64512 @ half -Inf +; CHECK-NEXT: .short 0xfc00 @ half -Inf entry: %z = call fast half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half> %x) ret half %z @@ -1641,7 +1641,7 @@ define arm_aapcs_vfpcc float @fmax_v2f32_acc(<2 x float> %x, float %y) { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI54_0: -; CHECK-NEXT: .long 4286578688 @ float -Inf +; CHECK-NEXT: .long 0xff800000 @ float -Inf entry: %z = call fast float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x) %c = fcmp fast ogt float %y, %z @@ -1720,7 +1720,7 @@ define arm_aapcs_vfpcc void @fmax_v4f16_acc(<4 x half> %x, half* %yy) { ; CHECK-NEXT: .p2align 1 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI57_0: -; CHECK-NEXT: .short 64512 @ half -Inf +; CHECK-NEXT: .short 0xfc00 @ half -Inf entry: %y = load half, half* %yy %z = call fast half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half> %x) diff --git a/test/CodeGen/WebAssembly/global.ll b/test/CodeGen/WebAssembly/global.ll index 12f4db43f38..a4bd8ef922a 100644 --- a/test/CodeGen/WebAssembly/global.ll +++ b/test/CodeGen/WebAssembly/global.ll @@ -121,28 +121,28 @@ define i8* @call_memcpy(i8* %p, i8* nocapture readonly %q, i32 %n) { ; CHECK: .type f32nil,@object ; CHECK: .p2align 2{{$}} ; CHECK-NEXT: f32nil: -; CHECK-NEXT: .int32 0{{$}} +; CHECK-NEXT: .int32 0x00000000{{$}} ; CHECK-NEXT: .size f32nil, 4{{$}} @f32nil = internal global float zeroinitializer ; CHECK: .type f32z,@object ; CHECK: .p2align 2{{$}} ; CHECK-NEXT: f32z: -; CHECK-NEXT: .int32 0{{$}} +; CHECK-NEXT: .int32 0x00000000{{$}} ; CHECK-NEXT: .size f32z, 4{{$}} @f32z = internal global float 0.0 ; CHECK: .type f32nz,@object ; CHECK: .p2align 2{{$}} ; CHECK: f32nz: -; CHECK: .int32 2147483648{{$}} +; CHECK: .int32 0x80000000{{$}} ; CHECK: .size f32nz, 4{{$}} @f32nz = internal global float -0.0 ; CHECK: .type f32two,@object ; CHECK: .p2align 2{{$}} ; CHECK-NEXT: f32two: -; CHECK-NEXT: .int32 1073741824{{$}} +; CHECK-NEXT: .int32 0x40000000{{$}} ; CHECK-NEXT: .size f32two, 4{{$}} @f32two = internal global float 2.0 @@ -156,28 +156,28 @@ define i8* @call_memcpy(i8* %p, i8* nocapture readonly %q, i32 %n) { ; CHECK: .type f64nil,@object ; CHECK: .p2align 3{{$}} ; CHECK-NEXT: f64nil: -; CHECK-NEXT: .int64 0{{$}} +; CHECK-NEXT: .int64 0x0000000000000000{{$}} ; CHECK-NEXT: .size f64nil, 8{{$}} @f64nil = internal global double zeroinitializer ; CHECK: .type f64z,@object ; CHECK: .p2align 3{{$}} ; CHECK-NEXT: f64z: -; CHECK-NEXT: .int64 0{{$}} +; CHECK-NEXT: .int64 0x0000000000000000{{$}} ; CHECK-NEXT: .size f64z, 8{{$}} @f64z = internal global double 0.0 ; CHECK: .type f64nz,@object ; CHECK: .p2align 3{{$}} ; CHECK-NEXT: f64nz: -; CHECK-NEXT: .int64 -9223372036854775808{{$}} +; CHECK-NEXT: .int64 0x8000000000000000{{$}} ; CHECK-NEXT: .size f64nz, 8{{$}} @f64nz = internal global double -0.0 ; CHECK: .type f64two,@object ; CHECK: .p2align 3{{$}} ; CHECK-NEXT: f64two: -; CHECK-NEXT: .int64 4611686018427387904{{$}} +; CHECK-NEXT: .int64 0x4000000000000000{{$}} ; CHECK-NEXT: .size f64two, 8{{$}} @f64two = internal global double 2.0 diff --git a/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll b/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll index d4726f50a3a..82ff94e868d 100644 --- a/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll +++ b/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll @@ -1956,10 +1956,10 @@ define <8 x double> @f8xf64_f128(<8 x double> %a) { ; AVX512: .LCPI37 -; AVX512-NEXT: .quad 4616189618054758400 # double 4 -; AVX512-NEXT: .quad 4607182418800017408 # double 1 -; AVX512-NEXT: .quad 4611686018427387904 # double 2 -; AVX512-NEXT: .quad 4613937818241073152 # double 3 +; AVX512-NEXT: .quad 0x4010000000000000 # double 4 +; AVX512-NEXT: .quad 0x3ff0000000000000 # double 1 +; AVX512-NEXT: .quad 0x4000000000000000 # double 2 +; AVX512-NEXT: .quad 0x4008000000000000 # double 3 ; AVX512-NOT: .quad define <8 x double> @f8xf64_f256(<8 x double> %a) { diff --git a/test/CodeGen/X86/copysign-constant-magnitude.ll b/test/CodeGen/X86/copysign-constant-magnitude.ll index aca23b03270..c147c2919f8 100644 --- a/test/CodeGen/X86/copysign-constant-magnitude.ll +++ b/test/CodeGen/X86/copysign-constant-magnitude.ll @@ -7,8 +7,8 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" ; the constant load values because those are important. ; CHECK: [[SIGNMASK1:L.+]]: -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 define double @mag_pos0_double(double %x) nounwind { ; CHECK-LABEL: mag_pos0_double: @@ -20,7 +20,7 @@ define double @mag_pos0_double(double %x) nounwind { } ; CHECK: [[SIGNMASK2:L.+]]: -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 define double @mag_neg0_double(double %x) nounwind { ; CHECK-LABEL: mag_neg0_double: @@ -33,10 +33,10 @@ define double @mag_neg0_double(double %x) nounwind { } ; CHECK: [[SIGNMASK3:L.+]]: -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 ; CHECK: [[ONE3:L.+]]: -; CHECK-NEXT: .quad 4607182418800017408 ## double 1 +; CHECK-NEXT: .quad 0x3ff0000000000000 ## double 1 define double @mag_pos1_double(double %x) nounwind { ; CHECK-LABEL: mag_pos1_double: @@ -50,11 +50,11 @@ define double @mag_pos1_double(double %x) nounwind { } ; CHECK: [[SIGNMASK4:L.+]]: -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 ; CHECK: [[ONE4:L.+]]: -; CHECK-NEXT: .quad 4607182418800017408 ## double 1 -; CHECK-NEXT: .quad 4607182418800017408 ## double 1 +; CHECK-NEXT: .quad 0x3ff0000000000000 ## double 1 +; CHECK-NEXT: .quad 0x3ff0000000000000 ## double 1 define double @mag_neg1_double(double %x) nounwind { ; CHECK-LABEL: mag_neg1_double: @@ -67,10 +67,10 @@ define double @mag_neg1_double(double %x) nounwind { } ; CHECK: [[SIGNMASK5:L.+]]: -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 define float @mag_pos0_float(float %x) nounwind { ; CHECK-LABEL: mag_pos0_float: @@ -82,7 +82,7 @@ define float @mag_pos0_float(float %x) nounwind { } ; CHECK: [[SIGNMASK6:L.+]]: -; CHECK-NEXT: .long 2147483648 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 define float @mag_neg0_float(float %x) nounwind { ; CHECK-LABEL: mag_neg0_float: @@ -95,12 +95,12 @@ define float @mag_neg0_float(float %x) nounwind { } ; CHECK: [[SIGNMASK7:L.+]]: -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 ; CHECK: [[ONE7:L.+]]: -; CHECK-NEXT: .long 1065353216 ## float 1 +; CHECK-NEXT: .long 0x3f800000 ## float 1 define float @mag_pos1_float(float %x) nounwind { ; CHECK-LABEL: mag_pos1_float: @@ -114,15 +114,15 @@ define float @mag_pos1_float(float %x) nounwind { } ; CHECK: [[SIGNMASK8:L.+]]: -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 ; CHECK: [[ONE8:L.+]]: -; CHECK-NEXT: .long 1065353216 ## float 1 -; CHECK-NEXT: .long 1065353216 ## float 1 -; CHECK-NEXT: .long 1065353216 ## float 1 -; CHECK-NEXT: .long 1065353216 ## float 1 +; CHECK-NEXT: .long 0x3f800000 ## float 1 +; CHECK-NEXT: .long 0x3f800000 ## float 1 +; CHECK-NEXT: .long 0x3f800000 ## float 1 +; CHECK-NEXT: .long 0x3f800000 ## float 1 define float @mag_neg1_float(float %x) nounwind { ; CHECK-LABEL: mag_neg1_float: diff --git a/test/CodeGen/X86/float-asmprint.ll b/test/CodeGen/X86/float-asmprint.ll index 0108430ee93..879bcf39e59 100644 --- a/test/CodeGen/X86/float-asmprint.ll +++ b/test/CodeGen/X86/float-asmprint.ll @@ -13,44 +13,44 @@ @var4f16 = global <4 x half> ; CHECK: var128: -; CHECK-NEXT: .quad 0 # fp128 -0 -; CHECK-NEXT: .quad -9223372036854775808 +; CHECK-NEXT: .quad 0x0000000000000000 # fp128 -0 +; CHECK-NEXT: .quad 0x8000000000000000 ; CHECK-NEXT: .size ; CHECK: varppc128: ; For ppc_fp128, the high double always comes first. -; CHECK-NEXT: .quad -9223372036854775808 # ppc_fp128 -0 -; CHECK-NEXT: .quad 0 +; CHECK-NEXT: .quad 0x8000000000000000 # ppc_fp128 -0 +; CHECK-NEXT: .quad 0x0000000000000000 ; CHECK-NEXT: .size ; CHECK: var80: -; CHECK-NEXT: .quad 0 # x86_fp80 -0 -; CHECK-NEXT: .short 32768 +; CHECK-NEXT: .quad 0x0000000000000000 # x86_fp80 -0 +; CHECK-NEXT: .short 0x8000 ; CHECK-NEXT: .zero 6 ; CHECK-NEXT: .size ; CHECK: var64: -; CHECK-NEXT: .quad -9223372036854775808 # double -0 +; CHECK-NEXT: .quad 0x8000000000000000 # double -0 ; CHECK-NEXT: .size ; CHECK: var32: -; CHECK-NEXT: .long 2147483648 # float -0 +; CHECK-NEXT: .long 0x80000000 # float -0 ; CHECK-NEXT: .size ; CHECK: var16: -; CHECK-NEXT: .short 32768 # half -0 +; CHECK-NEXT: .short 0x8000 # half -0 ; CHECK-NEXT: .size ; CHECK: var4f32: -; CHECK-NEXT: .long 2147483648 # float -0 -; CHECK-NEXT: .long 0 # float 0 -; CHECK-NEXT: .long 1065353216 # float 1 -; CHECK-NEXT: .long 1073741824 # float 2 +; CHECK-NEXT: .long 0x80000000 # float -0 +; CHECK-NEXT: .long 0x00000000 # float 0 +; CHECK-NEXT: .long 0x3f800000 # float 1 +; CHECK-NEXT: .long 0x40000000 # float 2 ; CHECK-NEXT: .size ; CHECK: var4f16: -; CHECK-NEXT: .short 32768 # half -0 -; CHECK-NEXT: .short 0 # half 0 -; CHECK-NEXT: .short 15360 # half 1 -; CHECK-NEXT: .short 16384 # half 2 +; CHECK-NEXT: .short 0x8000 # half -0 +; CHECK-NEXT: .short 0x0000 # half 0 +; CHECK-NEXT: .short 0x3c00 # half 1 +; CHECK-NEXT: .short 0x4000 # half 2 ; CHECK-NEXT: .size diff --git a/test/CodeGen/X86/fp-immediate-shorten.ll b/test/CodeGen/X86/fp-immediate-shorten.ll index 49e3b1014be..d400419c45b 100644 --- a/test/CodeGen/X86/fp-immediate-shorten.ll +++ b/test/CodeGen/X86/fp-immediate-shorten.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=i686-- -mattr=-sse2,-sse3 | FileCheck %s -; CHECK: {{.long.1123418112}} +; CHECK: {{.long.0x42f60000}} define double @D() { ret double 1.230000e+02 diff --git a/test/CodeGen/X86/fp128-load.ll b/test/CodeGen/X86/fp128-load.ll index bd70ab5a1ac..254bbebef46 100644 --- a/test/CodeGen/X86/fp128-load.ll +++ b/test/CodeGen/X86/fp128-load.ll @@ -32,6 +32,6 @@ entry: } ; CHECK-LABEL: my_fp128: -; CHECK-NEXT: .quad 0 -; CHECK-NEXT: .quad 4611404543450677248 +; CHECK-NEXT: .quad 0x0 +; CHECK-NEXT: .quad 0x3fff000000000000 ; CHECK-NEXT: .size my_fp128, 16 diff --git a/test/CodeGen/X86/pr13577.ll b/test/CodeGen/X86/pr13577.ll index 3f9e2f953ba..f70f6f7739d 100644 --- a/test/CodeGen/X86/pr13577.ll +++ b/test/CodeGen/X86/pr13577.ll @@ -2,9 +2,9 @@ ; RUN: llc < %s -mtriple=x86_64-darwin | FileCheck %s ; CHECK-LABEL: LCPI0_0: -; CHECK-NEXT: .long 4286578688 +; CHECK-NEXT: .long 0xff800000 ; CHECK-LABEL: LCPI0_1: -; CHECK-NEXT: .long 2139095040 +; CHECK-NEXT: .long 0x7f800000 define x86_fp80 @foo(x86_fp80 %a) { ; CHECK-LABEL: foo: diff --git a/test/CodeGen/X86/pr40730.ll b/test/CodeGen/X86/pr40730.ll index 12b372dea33..55adeb2fc19 100644 --- a/test/CodeGen/X86/pr40730.ll +++ b/test/CodeGen/X86/pr40730.ll @@ -17,10 +17,10 @@ define <8 x i32> @shuffle_v8i32_0dcd3f14(<8 x i32> %a, <8 x i32> %b) { } ; CHECK: .LCPI1_0: -; CHECK-NEXT: .quad 60129542157 -; CHECK-NEXT: .quad 60129542157 -; CHECK-NEXT: .quad 68719476736 -; CHECK-NEXT: .quad 60129542157 +; CHECK-NEXT: .quad 0x0000000e0000000d +; CHECK-NEXT: .quad 0x0000000e0000000d +; CHECK-NEXT: .quad 0x0000001000000000 +; CHECK-NEXT: .quad 0x0000000e0000000d define <8 x i32> @shuffle_v8i32_0dcd3f14_constant(<8 x i32> %a0) { ; CHECK-LABEL: shuffle_v8i32_0dcd3f14_constant: diff --git a/test/CodeGen/X86/vec-copysign.ll b/test/CodeGen/X86/vec-copysign.ll index 78ceb52db54..c6a0a0b4def 100644 --- a/test/CodeGen/X86/vec-copysign.ll +++ b/test/CodeGen/X86/vec-copysign.ll @@ -5,16 +5,16 @@ ; Use a macosx triple to make sure the format of those constant strings is exact. ; CHECK: [[SIGNMASK1:L.+]]: -; CHECK-NEXT: .long 2147483648 -; CHECK-NEXT: .long 2147483648 -; CHECK-NEXT: .long 2147483648 -; CHECK-NEXT: .long 2147483648 +; CHECK-NEXT: .long 0x80000000 +; CHECK-NEXT: .long 0x80000000 +; CHECK-NEXT: .long 0x80000000 +; CHECK-NEXT: .long 0x80000000 ; CHECK: [[MAGMASK1:L.+]]: -; CHECK-NEXT: .long 2147483647 -; CHECK-NEXT: .long 2147483647 -; CHECK-NEXT: .long 2147483647 -; CHECK-NEXT: .long 2147483647 +; CHECK-NEXT: .long 0x7fffffff +; CHECK-NEXT: .long 0x7fffffff +; CHECK-NEXT: .long 0x7fffffff +; CHECK-NEXT: .long 0x7fffffff define <4 x float> @v4f32(<4 x float> %a, <4 x float> %b) nounwind { ; SSE2-LABEL: v4f32: @@ -36,30 +36,30 @@ define <4 x float> @v4f32(<4 x float> %a, <4 x float> %b) nounwind { } ; SSE2: [[MAGMASK2:L.+]]: -; SSE2-NEXT: .long 2147483647 -; SSE2-NEXT: .long 2147483647 -; SSE2-NEXT: .long 2147483647 -; SSE2-NEXT: .long 2147483647 +; SSE2-NEXT: .long 0x7fffffff +; SSE2-NEXT: .long 0x7fffffff +; SSE2-NEXT: .long 0x7fffffff +; SSE2-NEXT: .long 0x7fffffff ; AVX: [[SIGNMASK2:L.+]]: -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 ; AVX: [[MAGMASK2:L.+]]: -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind { ; SSE2-LABEL: v8f32: @@ -86,12 +86,12 @@ define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind { } ; CHECK: [[SIGNMASK3:L.+]]: -; CHECK-NEXT: .quad -9223372036854775808 -; CHECK-NEXT: .quad -9223372036854775808 +; CHECK-NEXT: .quad 0x8000000000000000 +; CHECK-NEXT: .quad 0x8000000000000000 ; CHECK: [[MAGMASK3:L.+]]: -; CHECK-NEXT: .quad 9223372036854775807 -; CHECK-NEXT: .quad 9223372036854775807 +; CHECK-NEXT: .quad 0x7fffffffffffffff +; CHECK-NEXT: .quad 0x7fffffffffffffff define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind { ; SSE2-LABEL: v2f64: @@ -113,20 +113,20 @@ define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind { } ; SSE2: [[MAGMASK4:L.+]]: -; SSE2-NEXT: .quad 9223372036854775807 -; SSE2-NEXT: .quad 9223372036854775807 +; SSE2-NEXT: .quad 0x7fffffffffffffff +; SSE2-NEXT: .quad 0x7fffffffffffffff ; AVX: [[SIGNMASK4:L.+]]: -; AVX-NEXT: .quad -9223372036854775808 -; AVX-NEXT: .quad -9223372036854775808 -; AVX-NEXT: .quad -9223372036854775808 -; AVX-NEXT: .quad -9223372036854775808 +; AVX-NEXT: .quad 0x8000000000000000 +; AVX-NEXT: .quad 0x8000000000000000 +; AVX-NEXT: .quad 0x8000000000000000 +; AVX-NEXT: .quad 0x8000000000000000 ; AVX: [[MAGMASK4:L.+]]: -; AVX-NEXT: .quad 9223372036854775807 -; AVX-NEXT: .quad 9223372036854775807 -; AVX-NEXT: .quad 9223372036854775807 -; AVX-NEXT: .quad 9223372036854775807 +; AVX-NEXT: .quad 0x7fffffffffffffff +; AVX-NEXT: .quad 0x7fffffffffffffff +; AVX-NEXT: .quad 0x7fffffffffffffff +; AVX-NEXT: .quad 0x7fffffffffffffff define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind { ; SSE2-LABEL: v4f64: diff --git a/test/CodeGen/X86/vec_uint_to_fp-fastmath.ll b/test/CodeGen/X86/vec_uint_to_fp-fastmath.ll index cccd1d739f8..bff605c0e56 100644 --- a/test/CodeGen/X86/vec_uint_to_fp-fastmath.ll +++ b/test/CodeGen/X86/vec_uint_to_fp-fastmath.ll @@ -31,10 +31,10 @@ ; CST-NEXT: .long 1392508928 # 0x53000000 ; CST: [[MAGICCSTADDR:.LCPI[0-9_]+]]: -; CST-NEXT: .long 1392509056 # float 5.49764202E+11 -; CST-NEXT: .long 1392509056 # float 5.49764202E+11 -; CST-NEXT: .long 1392509056 # float 5.49764202E+11 -; CST-NEXT: .long 1392509056 # float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 # float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 # float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 # float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 # float 5.49764202E+11 ; AVX2: [[LOWCSTADDR:.LCPI[0-9_]+]]: ; AVX2-NEXT: .long 1258291200 # 0x4b000000 @@ -43,7 +43,7 @@ ; AVX2-NEXT: .long 1392508928 # 0x53000000 ; AVX2: [[MAGICCSTADDR:.LCPI[0-9_]+]]: -; AVX2-NEXT: .long 1392509056 # float 5.49764202E+11 +; AVX2-NEXT: .long 0x53000080 # float 5.49764202E+11 define <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) { ; SSE2-LABEL: test_uitofp_v4i32_to_v4f32: @@ -114,7 +114,7 @@ define <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) { ; AVX2-NEXT: .long 1392508928 # 0x53000000 ; AVX2: [[MAGICCSTADDR:.LCPI[0-9_]+]]: -; AVX2-NEXT: .long 1392509056 # float 5.49764202E+11 +; AVX2-NEXT: .long 0x53000080 # float 5.49764202E+11 define <8 x float> @test_uitofp_v8i32_to_v8f32(<8 x i32> %arg) { ; Legalization will break the thing is 2 x <4 x i32> on anthing prior AVX. diff --git a/test/CodeGen/X86/vec_uint_to_fp.ll b/test/CodeGen/X86/vec_uint_to_fp.ll index 4dd5223f000..63feb77c915 100644 --- a/test/CodeGen/X86/vec_uint_to_fp.ll +++ b/test/CodeGen/X86/vec_uint_to_fp.ll @@ -23,10 +23,10 @@ ; CST-NEXT: .long 1392508928 ## 0x53000000 ; CST: [[MAGICCSTADDR:LCPI0_[0-9]+]]: -; CST-NEXT: .long 1392509056 ## float 5.49764202E+11 -; CST-NEXT: .long 1392509056 ## float 5.49764202E+11 -; CST-NEXT: .long 1392509056 ## float 5.49764202E+11 -; CST-NEXT: .long 1392509056 ## float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 ## float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 ## float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 ## float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 ## float 5.49764202E+11 ; AVX2: [[LOWCSTADDR:LCPI0_[0-9]+]]: ; AVX2-NEXT: .long 1258291200 ## 0x4b000000 @@ -35,7 +35,7 @@ ; AVX2-NEXT: .long 1392508928 ## 0x53000000 ; AVX2: [[MAGICCSTADDR:LCPI0_[0-9]+]]: -; AVX2-NEXT: .long 1392509056 ## float 5.49764202E+11 +; AVX2-NEXT: .long 0x53000080 ## float 5.49764202E+11 define <4 x float> @test1(<4 x i32> %A) nounwind { ; CHECK-LABEL: test1: @@ -91,7 +91,7 @@ define <4 x float> @test1(<4 x i32> %A) nounwind { ; AVX2-NEXT: .long 1392508928 ## 0x53000000 ; AVX2: [[MAGICCSTADDR:LCPI1_[0-9]+]]: -; AVX2-NEXT: .long 1392509056 ## float 5.49764202E+11 +; AVX2-NEXT: .long 0x53000080 ## float 5.49764202E+11 define <8 x float> @test2(<8 x i32> %A) nounwind { ; CHECK-LABEL: test2: diff --git a/test/CodeGen/X86/win_cst_pool.ll b/test/CodeGen/X86/win_cst_pool.ll index 59d4fe18204..5bc9d34e4b3 100644 --- a/test/CodeGen/X86/win_cst_pool.ll +++ b/test/CodeGen/X86/win_cst_pool.ll @@ -14,7 +14,7 @@ define double @double() { ; CHECK-NEXT: .section .rdata,"dr",discard,__real@0000000000800000 ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: __real@0000000000800000: -; CHECK-NEXT: .quad 8388608 +; CHECK-NEXT: .quad 0x0000000000800000 ; CHECK: double: ; CHECK: movsd __real@0000000000800000(%rip), %xmm0 ; CHECK-NEXT: ret @@ -22,7 +22,7 @@ define double @double() { ; MINGW: .section .rdata,"dr" ; MINGW-NEXT: .p2align 3 ; MINGW-NEXT: [[LABEL:\.LC.*]]: -; MINGW-NEXT: .quad 8388608 +; MINGW-NEXT: .quad 0x0000000000800000 ; MINGW: double: ; MINGW: movsd [[LABEL]](%rip), %xmm0 ; MINGW-NEXT: ret @@ -69,8 +69,8 @@ define <4 x float> @undef1() { ; CHECK-NEXT: .section .rdata,"dr",discard,__xmm@00000000000000003f8000003f800000 ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: __xmm@00000000000000003f8000003f800000: -; CHECK-NEXT: .long 1065353216 # float 1 -; CHECK-NEXT: .long 1065353216 # float 1 +; CHECK-NEXT: .long 0x3f800000 # float 1 +; CHECK-NEXT: .long 0x3f800000 # float 1 ; CHECK-NEXT: .zero 4 ; CHECK-NEXT: .zero 4 ; CHECK: undef1: @@ -88,8 +88,8 @@ define float @pr23966(i32 %a) { ; CHECK-NEXT: .section .rdata,"dr",discard,__real@bf8000003f800000 ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: __real@bf8000003f800000: -; CHECK-NEXT: .long 1065353216 -; CHECK-NEXT: .long 3212836864 +; CHECK-NEXT: .long 0x3f800000 +; CHECK-NEXT: .long 0xbf800000 define <4 x i64> @ymm() { entry: diff --git a/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll b/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll index 70a72e7ee1a..2e756e15744 100644 --- a/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll +++ b/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll @@ -46,10 +46,10 @@ define void @foo1(<4 x float> %val, <4 x float> %test, <4 x double>* %p) nounwin ; Also test the general purpose constant folding of int->fp. define void @foo2(<4 x float>* noalias %result) nounwind { ; CHECK-LABEL: LCPI2_0: -; CHECK-NEXT: .long 1082130432 ## float 4 -; CHECK-NEXT: .long 1084227584 ## float 5 -; CHECK-NEXT: .long 1086324736 ## float 6 -; CHECK-NEXT: .long 1088421888 ## float 7 +; CHECK-NEXT: .long 0x40800000 ## float 4 +; CHECK-NEXT: .long 0x40a00000 ## float 5 +; CHECK-NEXT: .long 0x40c00000 ## float 6 +; CHECK-NEXT: .long 0x40e00000 ## float 7 ; CHECK-LABEL: foo2: ; CHECK: ## %bb.0: ; CHECK-NEXT: movaps {{.*#+}} xmm0 = [4.0E+0,5.0E+0,6.0E+0,7.0E+0] @@ -83,10 +83,10 @@ define <4 x float> @foo3(<4 x float> %val, <4 x float> %test) nounwind { ; Test the general purpose constant folding of uint->fp. define void @foo4(<4 x float>* noalias %result) nounwind { ; CHECK-LABEL: LCPI4_0: -; CHECK-NEXT: .long 1065353216 ## float 1 -; CHECK-NEXT: .long 1123942400 ## float 127 -; CHECK-NEXT: .long 1124073472 ## float 128 -; CHECK-NEXT: .long 1132396544 ## float 255 +; CHECK-NEXT: .long 0x3f800000 ## float 1 +; CHECK-NEXT: .long 0x42fe0000 ## float 127 +; CHECK-NEXT: .long 0x43000000 ## float 128 +; CHECK-NEXT: .long 0x437f0000 ## float 255 ; CHECK-LABEL: foo4: ; CHECK: ## %bb.0: ; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,1.27E+2,1.28E+2,2.55E+2]