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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 11:42:57 +01:00

Rename UpdateRegAllocHint to match style guidelines.

llvm-svn: 230357
This commit is contained in:
Eric Christopher 2015-02-24 19:10:57 +00:00
parent 45ead6c770
commit 7ee6f3d6c2
4 changed files with 5 additions and 5 deletions

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@ -694,13 +694,13 @@ public:
return false;
}
/// UpdateRegAllocHint - A callback to allow target a chance to update
/// updateRegAllocHint - A callback to allow target a chance to update
/// register allocation hints when a register is "changed" (e.g. coalesced)
/// to another register. e.g. On ARM, some virtual registers should target
/// register pairs, if one of pair is coalesced to another register, the
/// allocation hint of the other half of the pair should be changed to point
/// to the new register.
virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
MachineFunction &MF) const {
// Do nothing.
}

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@ -1393,7 +1393,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
LIS->removeInterval(CP.getSrcReg());
// Update regalloc hint.
TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
DEBUG({
dbgs() << "\tSuccess: " << PrintReg(CP.getSrcReg(), TRI, CP.getSrcIdx())

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@ -264,7 +264,7 @@ ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
}
void
ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
MachineFunction &MF) const {
MachineRegisterInfo *MRI = &MF.getRegInfo();
std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);

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@ -135,7 +135,7 @@ public:
const MachineFunction &MF,
const VirtRegMap *VRM) const override;
void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
void updateRegAllocHint(unsigned Reg, unsigned NewReg,
MachineFunction &MF) const override;
bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const override;