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[mips] Rewrite MipsAsmParser and MipsOperand.

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Summary:
Highlights:
- Registers are resolved much later (by the render method).
  Prior to that point, GPR32's/GPR64's are GPR's regardless of register
  size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
  size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
  symbol aliasing)
  - One consequence is that all registers can be specified numerically
    almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
    but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
  standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
  xfailed now work:
    ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
    c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
  by the predicate and renderer.

Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
  MipsOperand::isReg() will return true for a k_RegisterIndex token
  with Index == 0 and getReg() will return ZERO for this case. Note that it
  doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
  Some more of the generic parser could be removed too (integers and relocs
  for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
  was needed to make it parse correctly. The difficulty was that the matcher
  expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

llvm-svn: 205292
This commit is contained in:
Daniel Sanders 2014-04-01 10:35:28 +00:00
parent 52000bde25
commit 7eeb50777d
23 changed files with 954 additions and 1094 deletions
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1684
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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File diff suppressed because it is too large Load Diff

52
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@ -263,6 +263,11 @@ static DecodeStatus DecodeExtSize(MCInst &Inst,
uint64_t Address,
const void *Decoder);
/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
/// handle.
template <typename InsnType>
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
namespace llvm {
extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
TheMips64elTarget;
@ -304,9 +309,54 @@ extern "C" void LLVMInitializeMipsDisassembler() {
createMips64elDisassembler);
}
#include "MipsGenDisassemblerTables.inc"
template <typename InsnType>
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder) {
typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
// The size of the n field depends on the element size
// The register class also depends on this.
InsnType tmp = fieldFromInstruction(insn, 17, 5);
unsigned NSize = 0;
DecodeFN RegDecoder = nullptr;
if ((tmp & 0x18) == 0x00) { // INSVE_B
NSize = 4;
RegDecoder = DecodeMSA128BRegisterClass;
} else if ((tmp & 0x1c) == 0x10) { // INSVE_H
NSize = 3;
RegDecoder = DecodeMSA128HRegisterClass;
} else if ((tmp & 0x1e) == 0x18) { // INSVE_W
NSize = 2;
RegDecoder = DecodeMSA128WRegisterClass;
} else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
NSize = 1;
RegDecoder = DecodeMSA128DRegisterClass;
} else
llvm_unreachable("Invalid encoding");
assert(NSize != 0 && RegDecoder != nullptr);
// $wd
tmp = fieldFromInstruction(insn, 6, 5);
if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
// $wd_in
if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
// $n
tmp = fieldFromInstruction(insn, 16, NSize);
MI.addOperand(MCOperand::CreateImm(tmp));
// $ws
tmp = fieldFromInstruction(insn, 11, 5);
if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
// $n2
MI.addOperand(MCOperand::CreateImm(0));
return MCDisassembler::Success;
}
/// readInstruction - read four bytes from the MemoryObject
/// and return 32 bit word sorted according to the given endianess
static DecodeStatus readInstruction32(const MemoryObject &region,

1
lib/Target/Mips/MipsISelLowering.cpp
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@ -197,6 +197,7 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
case MipsISD::ILVR: return "MipsISD::ILVR";
case MipsISD::PCKEV: return "MipsISD::PCKEV";
case MipsISD::PCKOD: return "MipsISD::PCKOD";
case MipsISD::INSVE: return "MipsISD::INSVE";
default: return NULL;
}
}

3
lib/Target/Mips/MipsISelLowering.h
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@ -184,6 +184,9 @@ namespace llvm {
PCKEV, // Pack even elements
PCKOD, // Pack odd elements
// Vector Lane Copy
INSVE, // Copy element from one vector to another
// Combined (XOR (OR $a, $b), -1)
VNOR,

26
lib/Target/Mips/MipsInstrInfo.td
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@ -236,17 +236,27 @@ include "MipsInstrFormats.td"
// Mips Operand, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//
def MipsJumpTargetAsmOperand : AsmOperandClass {
let Name = "JumpTarget";
let ParserMethod = "ParseJumpTarget";
let PredicateMethod = "isImm";
let RenderMethod = "addImmOperands";
}
// Instruction operand types
def jmptarget : Operand<OtherVT> {
let EncoderMethod = "getJumpTargetOpValue";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def brtarget : Operand<OtherVT> {
let EncoderMethod = "getBranchTargetOpValue";
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def calltarget : Operand<iPTR> {
let EncoderMethod = "getJumpTargetOpValue";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def simm10 : Operand<i32>;
@ -268,6 +278,11 @@ def simm16_64 : Operand<i64> {
let DecoderMethod = "DecodeSimm16";
}
// Zero
def uimmz : Operand<i32> {
let PrintMethod = "printUnsignedImm";
}
// Unsigned Operand
def uimm5 : Operand<i32> {
let PrintMethod = "printUnsignedImm";
@ -295,12 +310,6 @@ def MipsInvertedImmoperand : AsmOperandClass {
let ParserMethod = "parseInvNum";
}
def PtrRegAsmOperand : AsmOperandClass {
let Name = "PtrReg";
let ParserMethod = "parsePtrReg";
}
def InvertedImOperand : Operand<i32> {
let ParserMatchClass = MipsInvertedImmoperand;
}
@ -332,7 +341,7 @@ def mem_ea : Operand<iPTR> {
def PtrRC : Operand<iPTR> {
let MIOperandInfo = (ops ptr_rc);
let DecoderMethod = "DecodePtrRegisterClass";
let ParserMatchClass = PtrRegAsmOperand;
let ParserMatchClass = GPR32AsmOperand;
}
// size operand of ext instruction
@ -360,6 +369,9 @@ def HI16 : SDNodeXForm<imm, [{
// Plus 1.
def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
// Node immediate is zero (e.g. insve.d)
def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
// Node immediate fits as 16-bit sign extended on target immediate.
// e.g. addi, andi
def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;

50
lib/Target/Mips/MipsMSAInstrInfo.td
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@ -27,6 +27,9 @@ def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
SDTCisVT<2, i32>, SDTCisSameAs<0, 3>,
SDTCisVT<4, i32>]>;
def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
@ -50,6 +53,7 @@ def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
@ -69,7 +73,7 @@ def uimm2 : Operand<i32> {
// as the encoded value should be subtracted by one.
def uimm2LSAAsmOperand : AsmOperandClass {
let Name = "LSAImm";
let ParserMethod = "parseLSAImm";
let ParserMethod = "ParseLSAImm";
let RenderMethod = "addImmOperands";
}
@ -156,6 +160,15 @@ def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx),
(v2i64 (vector_insert node:$vec, node:$val, node:$idx))>;
def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
(v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
(v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
(v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
(v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
PatFrag<(ops node:$lhs, node:$rhs),
(ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
@ -1402,9 +1415,9 @@ class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, GPR32:$rt);
dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32:$rt))];
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))];
InstrItinClass Itinerary = itin;
}
@ -1425,10 +1438,10 @@ class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32:$rt);
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
GPR32:$rt))];
GPR32Opnd:$rt))];
InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in";
}
@ -1496,11 +1509,12 @@ class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws);
string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[0]");
dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws, uimmz:$n2);
string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
immZExt6:$n,
ROWS:$ws))];
ROWS:$ws,
immz:$n2))];
InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in";
}
@ -2291,13 +2305,13 @@ class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
MSA128DOpnd, FGR64Opnd>;
class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b,
class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8,
MSA128BOpnd>;
class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h,
class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16,
MSA128HOpnd>;
class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w,
class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32,
MSA128WOpnd>;
class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d,
class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64,
MSA128DOpnd>;
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@ -3188,10 +3202,14 @@ def INSERT_D : INSERT_D_ENC, INSERT_D_DESC;
// INSERT_FW_PSEUDO defined after INSVE_W
// INSERT_FD_PSEUDO defined after INSVE_D
def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
// There is a fourth operand that is not present in the encoding. Use a
// custom decoder to get a chance to add it.
let DecoderMethod = "DecodeINSVE_DF" in {
def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
}
def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;

102
lib/Target/Mips/MipsRegisterInfo.td
View File

@ -209,7 +209,8 @@ let Namespace = "Mips" in {
def PC : Register<"pc">;
// Hardware register $29
def HWR29 : MipsReg<29, "29">;
foreach I = 0-31 in
def HWR#I : MipsReg<#I, ""#I>;
// Accum registers
foreach I = 0-3 in
@ -364,7 +365,8 @@ def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>;
def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>;
// Hardware registers
def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>,
Unallocatable;
// Accumulator Registers
def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
@ -394,86 +396,68 @@ def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>,
// Register Operands.
class MipsAsmRegOperand : AsmOperandClass {
let RenderMethod = "addRegAsmOperands";
}
def GPR32AsmOperand : MipsAsmRegOperand {
let Name = "GPR32Asm";
let ParserMethod = "parseGPR32";
let ParserMethod = "ParseAnyRegister";
}
def GPR64AsmOperand : MipsAsmRegOperand {
let Name = "GPR64Asm";
let ParserMethod = "parseGPR64";
let Name = "GPR64AsmReg";
let PredicateMethod = "isGPRAsmReg";
}
def GPR32AsmOperand : MipsAsmRegOperand {
let Name = "GPR32AsmReg";
let PredicateMethod = "isGPRAsmReg";
}
def ACC64DSPAsmOperand : MipsAsmRegOperand {
let Name = "ACC64DSPAsm";
let ParserMethod = "parseACC64DSP";
}
def LO32DSPAsmOperand : MipsAsmRegOperand {
let Name = "LO32DSPAsm";
let ParserMethod = "parseLO32DSP";
let Name = "ACC64DSPAsmReg";
let PredicateMethod = "isACCAsmReg";
}
def HI32DSPAsmOperand : MipsAsmRegOperand {
let Name = "HI32DSPAsm";
let ParserMethod = "parseHI32DSP";
let Name = "HI32DSPAsmReg";
let PredicateMethod = "isACCAsmReg";
}
def LO32DSPAsmOperand : MipsAsmRegOperand {
let Name = "LO32DSPAsmReg";
let PredicateMethod = "isACCAsmReg";
}
def CCRAsmOperand : MipsAsmRegOperand {
let Name = "CCRAsm";
let ParserMethod = "parseCCRRegs";
let Name = "CCRAsmReg";
}
def AFGR64AsmOperand : MipsAsmRegOperand {
let Name = "AFGR64Asm";
let ParserMethod = "parseAFGR64Regs";
let Name = "AFGR64AsmReg";
let PredicateMethod = "isFGRAsmReg";
}
def FGR64AsmOperand : MipsAsmRegOperand {
let Name = "FGR64Asm";
let ParserMethod = "parseFGR64Regs";
let Name = "FGR64AsmReg";
let PredicateMethod = "isFGRAsmReg";
}
def FGR32AsmOperand : MipsAsmRegOperand {
let Name = "FGR32Asm";
let ParserMethod = "parseFGR32Regs";
let Name = "FGR32AsmReg";
let PredicateMethod = "isFGRAsmReg";
}
def FGRH32AsmOperand : MipsAsmRegOperand {
let Name = "FGRH32Asm";
let ParserMethod = "parseFGRH32Regs";
let Name = "FGRH32AsmReg";
let PredicateMethod = "isFGRAsmReg";
}
def FCCRegsAsmOperand : MipsAsmRegOperand {
let Name = "FCCRegsAsm";
let ParserMethod = "parseFCCRegs";
let Name = "FCCAsmReg";
}
def MSA128BAsmOperand : MipsAsmRegOperand {
let Name = "MSA128BAsm";
let ParserMethod = "parseMSA128BRegs";
def MSA128AsmOperand : MipsAsmRegOperand {
let Name = "MSA128AsmReg";
}
def MSA128HAsmOperand : MipsAsmRegOperand {
let Name = "MSA128HAsm";
let ParserMethod = "parseMSA128HRegs";
}
def MSA128WAsmOperand : MipsAsmRegOperand {
let Name = "MSA128WAsm";
let ParserMethod = "parseMSA128WRegs";
}
def MSA128DAsmOperand : MipsAsmRegOperand {
let Name = "MSA128DAsm";
let ParserMethod = "parseMSA128DRegs";
}
def MSA128CRAsmOperand : MipsAsmRegOperand {
let Name = "MSA128CRAsm";
let ParserMethod = "parseMSA128CtrlRegs";
def MSACtrlAsmOperand : MipsAsmRegOperand {
let Name = "MSACtrlAsmReg";
}
def GPR32Opnd : RegisterOperand<GPR32> {
@ -493,13 +477,11 @@ def CCROpnd : RegisterOperand<CCR> {
}
def HWRegsAsmOperand : MipsAsmRegOperand {
let Name = "HWRegsAsm";
let ParserMethod = "parseHWRegs";
let Name = "HWRegsAsmReg";
}
def COP2AsmOperand : MipsAsmRegOperand {
let Name = "COP2Asm";
let ParserMethod = "parseCOP2";
let Name = "COP2AsmReg";
}
def HWRegsOpnd : RegisterOperand<HWRegs> {
@ -543,22 +525,22 @@ def COP2Opnd : RegisterOperand<COP2> {
}
def MSA128BOpnd : RegisterOperand<MSA128B> {
let ParserMatchClass = MSA128BAsmOperand;
let ParserMatchClass = MSA128AsmOperand;
}
def MSA128HOpnd : RegisterOperand<MSA128H> {
let ParserMatchClass = MSA128HAsmOperand;
let ParserMatchClass = MSA128AsmOperand;
}
def MSA128WOpnd : RegisterOperand<MSA128W> {
let ParserMatchClass = MSA128WAsmOperand;
let ParserMatchClass = MSA128AsmOperand;
}
def MSA128DOpnd : RegisterOperand<MSA128D> {
let ParserMatchClass = MSA128DAsmOperand;
let ParserMatchClass = MSA128AsmOperand;
}
def MSA128CROpnd : RegisterOperand<MSACtrl> {
let ParserMatchClass = MSA128CRAsmOperand;
let ParserMatchClass = MSACtrlAsmOperand;
}

13
lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -1810,6 +1810,13 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::mips_insert_d:
return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
case Intrinsic::mips_insve_b:
case Intrinsic::mips_insve_h:
case Intrinsic::mips_insve_w:
case Intrinsic::mips_insve_d:
return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
DAG.getConstant(0, MVT::i32));
case Intrinsic::mips_ldi_b:
case Intrinsic::mips_ldi_h:
case Intrinsic::mips_ldi_w:
@ -2837,7 +2844,8 @@ MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
.addReg(Wd_in)
.addImm(Lane)
.addReg(Wt);
.addReg(Wt)
.addImm(0);
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
@ -2870,7 +2878,8 @@ MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
.addReg(Wd_in)
.addImm(Lane)
.addReg(Wt);
.addReg(Wt)
.addImm(0);
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;

13
test/MC/Mips/cfi.s Normal file
View File

@ -0,0 +1,13 @@
# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32 | \
# RUN: FileCheck %s
# RUN: llvm-mc %s -triple=mips64-unknown-unknown -show-encoding -mcpu=mips64 | \
# RUN: FileCheck %s
# Check that we can accept register names in CFI directives and that they are
# canonicalised to their DWARF register numbers.
.cfi_startproc # CHECK: .cfi_startproc
.cfi_register $6, $5 # CHECK: .cfi_register 6, 5
.cfi_def_cfa $fp, 8 # CHECK: .cfi_def_cfa 30, 8
.cfi_def_cfa $2, 16 # CHECK: .cfi_def_cfa 2, 16
.cfi_endproc # CHECK: .cfi_endproc

2
test/MC/Mips/mips-register-names-invalid.s
View File

@ -4,5 +4,5 @@
# $32 used to trigger an assertion instead of the usual error message due to
# an off-by-one bug.
# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
add $32, $0, $0

4
test/MC/Mips/mips3/valid-xfail.s
View File

@ -8,10 +8,6 @@
# XFAIL: *
.set noat
ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1
div $zero,$t9,$t3
divu $zero,$t9,$t7
ehb
lwc3 $10,-32265($k0)
ssnop

4
test/MC/Mips/mips3/valid.s
View File

@ -35,8 +35,12 @@
dadd $s3,$at,$ra
daddi $sp,$s4,-27705
daddiu $k0,$s6,-4586
ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1
div $zero,$t9,$t3
div.d $f29,$f20,$f27
div.s $f4,$f5,$f15
divu $zero,$t9,$t7
dmfc1 $t4,$f13
dmtc1 $s0,$f14
dmult $s7,$t1

16
test/MC/Mips/mips32r2/valid-xfail.s
View File

@ -2,7 +2,7 @@
# they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding.
#
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | not FileCheck %s
# CHECK-NOT: encoding
# XFAIL: *
@ -48,7 +48,6 @@
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.d $f29,$f29
c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20
@ -66,7 +65,6 @@
c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6
c.sf.s $f14,$f22
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
@ -96,14 +94,10 @@
cmpu.lt.qb $at,$a3
ctcmsa $31,$s7
cvt.d.l $f4,$f16
cvt.l.d $f24,$f15
cvt.l.s $f11,$f29
cvt.ps.s $f3,$f18,$f19
cvt.s.l $f15,$f30
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
div $zero,$t9,$t3
divu $zero,$t9,$t7
dmt $k0
dpa.w.ph $ac1,$s7,$k0
dpaq_s.w.ph $ac2,$a0,$t5
@ -152,8 +146,6 @@
flog2.w $w19,$w23
floor.l.d $f26,$f7
floor.l.s $f12,$f5
floor.w.d $f14,$f11
floor.w.s $f8,$f9
fork $s2,$t0,$a0
frcp.d $w12,$w4
frcp.w $w30,$w8
@ -228,12 +220,8 @@
nlzc.d $w14,$w14
nlzc.h $w24,$w24
nlzc.w $w10,$w4
nmadd.d $f18,$f9,$f14,$f19
nmadd.ps $f27,$f4,$f9,$f25
nmadd.s $f0,$f5,$f25,$f12
nmsub.d $f30,$f8,$f16,$f30
nmsub.ps $f6,$f12,$f14,$f17
nmsub.s $f1,$f24,$f19,$f4
nor.v $w20,$w20,$w15
or.v $w13,$w23,$w12
packrl.ph $ra,$t8,$t6
@ -264,7 +252,6 @@
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
raddu.w.qb $t9,$s3
rdhwr $sp,$11
rdpgpr $s3,$t1
recip.d $f19,$f6
recip.s $f3,$f30
@ -311,7 +298,6 @@
swe $t8,94($k0)
swle $v1,-209($gp)
swre $k0,-202($s2)
swxc1 $f19,$t4($k0)
synci 20023($s0)
tlbginv
tlbginvf

14
test/MC/Mips/mips32r2/valid.s
View File

@ -11,8 +11,10 @@
addi $t5,$t1,26322
addu $t1,$a0,$a2
and $s7,$v0,$t4
c.ngl.d $f29,$f29
c.ngle.d $f0,$f16
c.sf.d $f30,$f0
c.sf.s $f14,$f22
ceil.w.d $f11,$f25
ceil.w.s $f6,$f20
cfc1 $s1,$21
@ -21,16 +23,22 @@
ctc1 $a2,$26
cvt.d.s $f22,$f28
cvt.d.w $f26,$f11
cvt.l.d $f24,$f15
cvt.l.s $f11,$f29
cvt.s.d $f26,$f8
cvt.s.w $f22,$f15
cvt.w.d $f20,$f14
cvt.w.s $f20,$f24
deret
di $s8
div $zero,$t9,$t3
div.d $f29,$f20,$f27
div.s $f4,$f5,$f15
divu $zero,$t9,$t7
ei $t6
eret
floor.w.d $f14,$f11
floor.w.s $f8,$f9
lb $t8,-14515($t2)
lbu $t0,30195($v1)
ldc1 $f11,16391($s0)
@ -94,9 +102,14 @@
multu $t1,$s2
neg.d $f27,$f18
neg.s $f1,$f15
nmadd.d $f18,$f9,$f14,$f19
nmadd.s $f0,$f5,$f25,$f12
nmsub.d $f30,$f8,$f16,$f30
nmsub.s $f1,$f24,$f19,$f4
nop
nor $a3,$zero,$a3
or $t4,$s0,$sp
rdhwr $sp,$11
round.w.d $f6,$f4
round.w.s $f27,$f28
sb $s6,-19857($t6)
@ -126,6 +139,7 @@
swc2 $25,24880($s0)
swl $t7,13694($s3)
swr $s1,-26590($t6)
swxc1 $f19,$t4($k0)
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621

4
test/MC/Mips/mips4/valid-xfail.s
View File

@ -36,10 +36,6 @@
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1
div $zero,$t9,$t3
divu $zero,$t9,$t7
ehb
madd.d $f18,$f19,$f26,$f20
madd.s $f1,$f31,$f19,$f25

4
test/MC/Mips/mips4/valid.s
View File

@ -35,8 +35,12 @@
dadd $s3,$at,$ra
daddi $sp,$s4,-27705
daddiu $k0,$s6,-4586
ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1
div $zero,$t9,$t3
div.d $f29,$f20,$f27
div.s $f4,$f5,$f15
divu $zero,$t9,$t7
dmfc1 $t4,$f13
dmtc1 $s0,$f14
dmult $s7,$t1

4
test/MC/Mips/mips5/valid-xfail.s
View File

@ -58,10 +58,6 @@
cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1
div $zero,$t9,$t3
divu $zero,$t9,$t7
ehb
madd.d $f18,$f19,$f26,$f20
madd.ps $f22,$f3,$f14,$f3

4
test/MC/Mips/mips5/valid.s
View File

@ -35,8 +35,12 @@
dadd $s3,$at,$ra
daddi $sp,$s4,-27705
daddiu $k0,$s6,-4586
ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1
div $zero,$t9,$t3
div.d $f29,$f20,$f27
div.s $f4,$f5,$f15
divu $zero,$t9,$t7
dmfc1 $t4,$f13
dmtc1 $s0,$f14
dmult $s7,$t1

4
test/MC/Mips/mips64/valid-xfail.s
View File

@ -60,10 +60,6 @@
cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1
div $zero,$t9,$t3
divu $zero,$t9,$t7
dmfc0 $t2,c0_watchhi,2
dmtc0 $t7,c0_datalo
ehb

4
test/MC/Mips/mips64/valid.s
View File

@ -39,8 +39,12 @@
dclo $s2,$a2
dclz $s0,$t9
deret
ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1
div $zero,$t9,$t3
div.d $f29,$f20,$f27
div.s $f4,$f5,$f15
divu $zero,$t9,$t7
dmfc1 $t4,$f13
dmtc1 $s0,$f14
dmult $s7,$t1

16
test/MC/Mips/mips64r2/valid-xfail.s
View File

@ -52,7 +52,6 @@
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.d $f29,$f29
c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20
@ -70,7 +69,6 @@
c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6
c.sf.s $f14,$f22
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
@ -98,10 +96,6 @@
cmpu.lt.qb $at,$a3
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1
div $zero,$t9,$t3
divu $zero,$t9,$t7
dmfc0 $t2,c0_watchhi,2
dmfgc0 $gp,c0_perfcnt,6
dmt $k0
@ -124,8 +118,6 @@
dpsu.h.qbr $ac2,$a1,$s6
dpsx.w.ph $ac0,$s7,$gp
drorv $at,$a1,$s7
dsbh $v1,$t6
dshd $v0,$sp
dvpe $s6
ehb
emt $t0
@ -188,7 +180,6 @@
lwx $t4,$t4($s4)
madd.d $f18,$f19,$f26,$f20
madd.ps $f22,$f3,$f14,$f3
madd.s $f1,$f31,$f19,$f25
maq_s.w.phl $ac2,$t9,$t3
maq_s.w.phr $ac0,$t2,$t9
maq_sa.w.phl $ac3,$a1,$v1
@ -206,7 +197,6 @@
msub $ac2,$sp,$t6
msub.d $f10,$f1,$f31,$f18
msub.ps $f12,$f14,$f29,$f17
msub.s $f12,$f19,$f10,$f16
msubu $ac2,$a1,$t8
mtc0 $t1,c0_datahi1
mtgc0 $s4,$21,7
@ -236,10 +226,8 @@
nlzc.w $w10,$w4
nmadd.d $f18,$f9,$f14,$f19
nmadd.ps $f27,$f4,$f9,$f25
nmadd.s $f0,$f5,$f25,$f12
nmsub.d $f30,$f8,$f16,$f30
nmsub.ps $f6,$f12,$f14,$f17
nmsub.s $f1,$f24,$f19,$f4
nor.v $w20,$w20,$w15
or.v $w13,$w23,$w12
packrl.ph $ra,$t8,$t6
@ -270,7 +258,6 @@
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
raddu.w.qb $t9,$s3
rdhwr $sp,$11
rdpgpr $s3,$t1
recip.d $f19,$f6
recip.s $f3,$f30
@ -282,8 +269,6 @@
rsqrt.s $f4,$f8
sbe $s7,33($s1)
sce $sp,189($t2)
seb $t9,$t7
seh $v1,$t4
she $t8,105($v0)
shilo $ac1,26
shilov $ac2,$t2
@ -330,6 +315,5 @@
tlbwi
tlbwr
wrpgpr $zero,$t5
wsbh $k1,$t1
xor.v $w20,$w21,$w30
yield $v1,$s0

16
test/MC/Mips/mips64r2/valid.s
View File

@ -11,8 +11,10 @@
addi $t5,$t1,26322
addu $t1,$a0,$a2
and $s7,$v0,$t4
c.ngl.d $f29,$f29
c.ngle.d $f0,$f16
c.sf.d $f30,$f0
c.sf.s $f14,$f22
ceil.l.d $f1,$f3
ceil.l.s $f18,$f13
ceil.w.d $f11,$f25
@ -38,12 +40,18 @@
dclz $s0,$t9
deret
di $s8
ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1
div $zero,$t9,$t3
div.d $f29,$f20,$f27
div.s $f4,$f5,$f15
divu $zero,$t9,$t7
dmfc1 $t4,$f13
dmtc1 $s0,$f14
dmult $s7,$t1
dmultu $a1,$a2
dsbh $v1,$t6
dshd $v0,$sp
dsllv $zero,$s4,$t4
dsrav $gp,$s2,$s3
dsrlv $s3,$t6,$s4
@ -79,6 +87,7 @@
lwxc1 $f12,$s1($s8)
madd $s6,$t5
madd $zero,$t1
madd.s $f1,$f31,$f19,$f25
maddu $s3,$gp
maddu $t8,$s2
mfc0 $a2,$14,1
@ -106,6 +115,7 @@
movz.d $f12,$f29,$t1
movz.s $f25,$f7,$v1
msub $s7,$k1
msub.s $f12,$f19,$f10,$f16
msubu $t7,$a1
mtc1 $s8,$f9
mthc1 $zero,$f16
@ -121,9 +131,12 @@
multu $t1,$s2
neg.d $f27,$f18
neg.s $f1,$f15
nmadd.s $f0,$f5,$f25,$f12
nmsub.s $f1,$f24,$f19,$f4
nop
nor $a3,$zero,$a3
or $t4,$s0,$sp
rdhwr $sp,$11
round.l.d $f12,$f1
round.l.s $f25,$f5
round.w.d $f6,$f4
@ -137,6 +150,8 @@
sdl $a3,-20961($s8)
sdr $t3,-20423($t4)
sdxc1 $f11,$t2($t6)
seb $t9,$t7
seh $v1,$t4
sh $t6,-6704($t7)
sllv $a3,$zero,$t1
slt $s7,$t3,$k1
@ -169,3 +184,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
wsbh $k1,$t1

8
test/MC/Mips/set-at-directive-explicit-at.s
View File

@ -7,12 +7,12 @@
.text
foo:
# CHECK: jr $1 # encoding: [0x08,0x00,0x20,0x00]
# WARNINGS: :[[@LINE+2]]:12: warning: Used $at without ".set noat"
# WARNINGS: :[[@LINE+2]]:11: warning: Used $at without ".set noat"
.set at=$1
jr $at
# CHECK: jr $1 # encoding: [0x08,0x00,0x20,0x00]
# WARNINGS: :[[@LINE+2]]:12: warning: Used $at without ".set noat"
# WARNINGS: :[[@LINE+2]]:11: warning: Used $at without ".set noat"
.set at=$1
jr $1
# WARNINGS-NOT: warning: Used $at without ".set noat"
@ -31,12 +31,12 @@ foo:
jr $at
# CHECK: jr $16 # encoding: [0x08,0x00,0x00,0x02]
# WARNINGS: :[[@LINE+2]]:12: warning: Used $16 with ".set at=$16"
# WARNINGS: :[[@LINE+2]]:11: warning: Used $16 with ".set at=$16"
.set at=$16
jr $s0
# CHECK: jr $16 # encoding: [0x08,0x00,0x00,0x02]
# WARNINGS: :[[@LINE+2]]:12: warning: Used $16 with ".set at=$16"
# WARNINGS: :[[@LINE+2]]:11: warning: Used $16 with ".set at=$16"
.set at=$16
jr $16
# WARNINGS-NOT: warning