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[AMDGPU] [CodeGen] Fold negate llvm.amdgcn.class into test mask
Implemented the transformation of xor (llvm.amdgcn.class x, mask), -1 into llvm.amdgcn.class(x, ~mask). Added LIT tests as well. Differential Revision: https://reviews.llvm.org/D104049
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@ -201,6 +201,7 @@ public:
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AMDGPUCodeGenPrepare() : FunctionPass(ID) {}
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bool visitFDiv(BinaryOperator &I);
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bool visitXor(BinaryOperator &I);
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bool visitInstruction(Instruction &I) { return false; }
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bool visitBinaryOperator(BinaryOperator &I);
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@ -808,6 +809,31 @@ bool AMDGPUCodeGenPrepare::visitFDiv(BinaryOperator &FDiv) {
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return !!NewFDiv;
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}
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bool AMDGPUCodeGenPrepare::visitXor(BinaryOperator &I) {
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// Match the Xor instruction, its type and its operands
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IntrinsicInst *IntrinsicCall = dyn_cast<IntrinsicInst>(I.getOperand(0));
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ConstantInt *RHS = dyn_cast<ConstantInt>(I.getOperand(1));
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if (!RHS || !IntrinsicCall || RHS->getSExtValue() != -1)
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return visitBinaryOperator(I);
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// Check if the Call is an intrinsic intruction to amdgcn_class intrinsic
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// has only one use
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if (IntrinsicCall->getIntrinsicID() != Intrinsic::amdgcn_class ||
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!IntrinsicCall->hasOneUse())
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return visitBinaryOperator(I);
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// "Not" the second argument of the intrinsic call
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ConstantInt *Arg = dyn_cast<ConstantInt>(IntrinsicCall->getOperand(1));
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if (!Arg)
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return visitBinaryOperator(I);
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IntrinsicCall->setOperand(
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1, ConstantInt::get(Arg->getType(), Arg->getZExtValue() ^ 0x3ff));
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I.replaceAllUsesWith(IntrinsicCall);
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I.eraseFromParent();
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return true;
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}
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static bool hasUnsafeFPMath(const Function &F) {
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Attribute Attr = F.getFnAttribute("unsafe-fp-math");
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return Attr.getValueAsBool();
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66
test/CodeGen/AMDGPU/amdgpu-codegenprepare-foldnegate.ll
Normal file
66
test/CodeGen/AMDGPU/amdgpu-codegenprepare-foldnegate.ll
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@ -0,0 +1,66 @@
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -amdgpu-codegenprepare -verify -S %s -o - | FileCheck %s
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declare i1 @llvm.amdgcn.class.f32(float, i32) nounwind readnone
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declare i1 @llvm.amdgcn.class.f64(double, i32) nounwind readnone
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; Trivial case, xor instruction should be removed and
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; the second argument of the intrinsic call should be
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; bitwise-negated
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; CHECK: @fold_negate_intrinsic_test_mask
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; CHECK: %1 = call i1 @llvm.amdgcn.class.f32(float %x, i32 1018)
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define i1 @fold_negate_intrinsic_test_mask(float %x) nounwind {
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%1 = call i1 @llvm.amdgcn.class.f32(float %x, i32 5)
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%2 = xor i1 %1, -1
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ret i1 %2
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}
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; Trivial case, xor instruction should be removed and
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; the second argument of the intrinsic call should be
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; bitwise-negated
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; CHECK: @fold_negate_intrinsic_test_mask_dbl
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; CHECK: %1 = call i1 @llvm.amdgcn.class.f64(double %x, i32 1018)
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define i1 @fold_negate_intrinsic_test_mask_dbl(double %x) nounwind {
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%1 = call i1 @llvm.amdgcn.class.f64(double %x, i32 5)
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%2 = xor i1 %1, -1
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ret i1 %2
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}
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; Negative test: should not transform for variable test masks
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; CHECK: @fold_negate_intrinsic_test_mask_neg_var
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; CHECK: %[[X0:.*]] = alloca i32
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; CHECK: %[[X1:.*]] = load i32, i32* %[[X0]]
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; CHECK: call i1 @llvm.amdgcn.class.f32(float %x, i32 %[[X1]])
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; CHECK: xor
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define i1 @fold_negate_intrinsic_test_mask_neg_var(float %x) nounwind {
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%1 = alloca i32
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store i32 7, i32* %1
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%2 = load i32, i32* %1
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%3 = call i1 @llvm.amdgcn.class.f32(float %x, i32 %2)
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%4 = xor i1 %3, -1
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ret i1 %4
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}
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; Negative test: should not transform for multiple uses of the
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; intrinsic returned value
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; CHECK: @fold_negate_intrinsic_test_mask_neg_multiple_uses
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; CHECK: %[[X1:.*]] = call i1 @llvm.amdgcn.class.f32(float %x, i32 7)
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; CHECK: store i1 %[[X1]]
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; CHECK: %[[X2:.*]] = xor i1 %[[X1]]
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define i1 @fold_negate_intrinsic_test_mask_neg_multiple_uses(float %x) nounwind {
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%y = alloca i1
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%1 = call i1 @llvm.amdgcn.class.f32(float %x, i32 7)
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%2 = xor i1 %1, -1
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store i1 %1, i1* %y
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%3 = xor i1 %1, -1
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ret i1 %2
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}
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; Negative test: should not transform for a xor with no operand equal to -1
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; CHECK: @fold_negate_intrinsic_test_mask_neg_one
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; CHECK: %[[X0:.*]] = call i1 @llvm.amdgcn.class.f32(float %x, i32 7)
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; CHECK: xor i1 %[[X0]], false
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define i1 @fold_negate_intrinsic_test_mask_neg_one(float %x) nounwind {
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%1 = call i1 @llvm.amdgcn.class.f32(float %x, i32 7)
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%2 = xor i1 %1, false
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ret i1 %2
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}
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