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Added for disassembly only the variants of DMB, DSB, and ISB.

llvm-svn: 96540
This commit is contained in:
Johnny Chen 2010-02-18 00:19:08 +00:00
parent 88fe6775de
commit 7f0bf276c2

View File

@ -1868,6 +1868,7 @@ def Int_MemBarrierV7 : AInoP<(outs), (ins),
Requires<[IsARM, HasV7]> {
let Inst{31-4} = 0xf57ff05;
// FIXME: add support for options other than a full system DMB
// See DMB disassembly-only variants below.
let Inst{3-0} = 0b1111;
}
@ -1878,6 +1879,7 @@ def Int_SyncBarrierV7 : AInoP<(outs), (ins),
Requires<[IsARM, HasV7]> {
let Inst{31-4} = 0xf57ff04;
// FIXME: add support for options other than a full system DSB
// See DSB disassembly-only variants below.
let Inst{3-0} = 0b1111;
}
@ -1900,6 +1902,64 @@ def Int_SyncBarrierV6 : AInoP<(outs), (ins GPR:$zero),
}
}
// Helper class for multiclass MemB -- for disassembly only
class AMBI<string opc, string asm>
: AInoP<(outs), (ins), MiscFrm, NoItinerary, opc, asm,
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV7]> {
let Inst{31-20} = 0xf57;
}
multiclass MemB<bits<4> op7_4, string opc> {
def st : AMBI<opc, "\tst"> {
let Inst{7-4} = op7_4;
let Inst{3-0} = 0b1110;
}
def ish : AMBI<opc, "\tish"> {
let Inst{7-4} = op7_4;
let Inst{3-0} = 0b1011;
}
def ishst : AMBI<opc, "\tishst"> {
let Inst{7-4} = op7_4;
let Inst{3-0} = 0b1010;
}
def nsh : AMBI<opc, "\tnsh"> {
let Inst{7-4} = op7_4;
let Inst{3-0} = 0b0111;
}
def nshst : AMBI<opc, "\tnshst"> {
let Inst{7-4} = op7_4;
let Inst{3-0} = 0b0110;
}
def osh : AMBI<opc, "\tosh"> {
let Inst{7-4} = op7_4;
let Inst{3-0} = 0b0011;
}
def oshst : AMBI<opc, "\toshst"> {
let Inst{7-4} = op7_4;
let Inst{3-0} = 0b0010;
}
}
// These DMB variants are for disassembly only.
defm DMB : MemB<0b0101, "dmb">;
// These DSB variants are for disassembly only.
defm DSB : MemB<0b0100, "dsb">;
// ISB has only full system option -- for disassembly only
def ISBsy : AMBI<"isb", ""> {
let Inst{7-4} = 0b0110;
let Inst{3-0} = 0b1111;
}
let usesCustomInserter = 1 in {
let Uses = [CPSR] in {
def ATOMIC_LOAD_ADD_I8 : PseudoInst<