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[Hexagon] Split vector pairs for ISD::SIGN_EXTEND and ISD::ZERO_EXTEND

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llvm-svn: 354473
This commit is contained in:
Krzysztof Parzyszek 2019-02-20 15:05:19 +00:00
parent 6a150a1049
commit 7f71bd4f06
3 changed files with 23 additions and 0 deletions
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5
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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@ -848,6 +848,9 @@ void HexagonDAGToDAGISel::SelectD2P(SDNode *N) {
void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) {
const SDLoc &dl(N);
MVT ResTy = N->getValueType(0).getSimpleVT();
// The argument to V2Q should be a single vector.
MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy;
assert(HST->getVectorLength() * 8 == OpTy.getSizeInBits());
SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32);
SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C);
@ -859,6 +862,8 @@ void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) {
void HexagonDAGToDAGISel::SelectQ2V(SDNode *N) {
const SDLoc &dl(N);
MVT ResTy = N->getValueType(0).getSimpleVT();
// The result of V2Q should be a single vector.
assert(HST->getVectorLength() * 8 == ResTy.getSizeInBits());
SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32);
SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C);

2
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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@ -1541,6 +1541,8 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::SRL:
case ISD::SETCC:
case ISD::VSELECT:
case ISD::SIGN_EXTEND:
case ISD::ZERO_EXTEND:
case ISD::SIGN_EXTEND_INREG:
return SplitHvxPairOp(Op, DAG);
}

16
test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll Normal file
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@ -0,0 +1,16 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Make sure that this doesn't crash.
; CHECK: vadd
define void @foo(<64 x i32>* %a0, <64 x i32>* %a1) #0 {
%v0 = load <64 x i32>, <64 x i32>* %a0, align 128
%v1 = load <64 x i32>, <64 x i32>* %a1, align 128
%v2 = icmp sgt <64 x i32> %v0, zeroinitializer
%v3 = sext <64 x i1> %v2 to <64 x i32>
%v4 = add nsw <64 x i32> %v1, %v3
store <64 x i32> %v4, <64 x i32>* %a1, align 128
ret void
}
attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvx,+hvx-length128b" }