RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
Code Issues Projects Releases Wiki Activity

Use MachineInstr::mop_iterator instead of MIOperands; NFC

Browse Source 
(Const)?MIOperands is equivalent to the C++ style
MachineInstr::mop_iterator. Use the latter for consistency except for a
few callers of MIOperands::analyzePhysReg().

llvm-svn: 285029
This commit is contained in:
Matthias Braun 2016-10-24 21:36:43 +00:00
parent 569d19c0b3
commit 7fbfea2c1c
6 changed files with 36 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/CodeGen/MachinePipeliner.cpp
View File

@ -1726,9 +1726,9 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
const MachineInstr *MI = SU->getInstr();
if (MI->isPHI())
continue;
for (ConstMIOperands MO(*MI); MO.isValid(); ++MO)
if (MO->isReg() && MO->isUse()) {
unsigned Reg = MO->getReg();
for (const MachineOperand &MO : MI->operands())
if (MO.isReg() && MO.isUse()) {
unsigned Reg = MO.getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg))
Uses.insert(Reg);
else if (MRI.isAllocatable(Reg))
@ -1737,9 +1737,9 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
}
}
for (SUnit *SU : NS)
for (ConstMIOperands MO(*SU->getInstr()); MO.isValid(); ++MO)
if (MO->isReg() && MO->isDef() && !MO->isDead()) {
unsigned Reg = MO->getReg();
for (const MachineOperand &MO : SU->getInstr()->operands())
if (MO.isReg() && MO.isDef() && !MO.isDead()) {
unsigned Reg = MO.getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
if (!Uses.count(Reg))
LiveOutRegs.push_back(RegisterMaskPair(Reg, 0));

34
lib/Target/Hexagon/HexagonEarlyIfConv.cpp
View File

@ -357,10 +357,10 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B)
// update the use of it after predication). PHI uses will be updated
// to use a result of a MUX, and a MUX cannot be created for predicate
// registers.
for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
if (!MO->isReg() || !MO->isDef())
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
unsigned R = MO->getReg();
unsigned R = MO.getReg();
if (!TargetRegisterInfo::isVirtualRegister(R))
continue;
if (MRI->getRegClass(R) != &Hexagon::PredRegsRegClass)
@ -375,10 +375,10 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B)
bool HexagonEarlyIfConversion::usesUndefVReg(const MachineInstr *MI) const {
for (ConstMIOperands MO(*MI); MO.isValid(); ++MO) {
if (!MO->isReg() || !MO->isUse())
for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || !MO.isUse())
continue;
unsigned R = MO->getReg();
unsigned R = MO.getReg();
if (!TargetRegisterInfo::isVirtualRegister(R))
continue;
const MachineInstr *DefI = MRI->getVRegDef(R);
@ -454,10 +454,10 @@ unsigned HexagonEarlyIfConversion::countPredicateDefs(
const MachineBasicBlock *B) const {
unsigned PredDefs = 0;
for (auto &MI : *B) {
for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
if (!MO->isReg() || !MO->isDef())
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
unsigned R = MO->getReg();
unsigned R = MO.getReg();
if (!TargetRegisterInfo::isVirtualRegister(R))
continue;
if (MRI->getRegClass(R) == &Hexagon::PredRegsRegClass)
@ -669,14 +669,14 @@ void HexagonEarlyIfConversion::predicateInstr(MachineBasicBlock *ToB,
unsigned COpc = getCondStoreOpcode(Opc, IfTrue);
assert(COpc);
MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, HII->get(COpc));
MIOperands MO(*MI);
MachineInstr::mop_iterator MOI = MI->operands_begin();
if (HII->isPostIncrement(*MI)) {
MIB.addOperand(*MO);
++MO;
MIB.addOperand(*MOI);
++MOI;
}
MIB.addReg(PredR);
for (; MO.isValid(); ++MO)
MIB.addOperand(*MO);
for (const MachineOperand &MO : make_range(MOI, MI->operands_end()))
MIB.addOperand(MO);
// Set memory references.
MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
@ -949,9 +949,9 @@ void HexagonEarlyIfConversion::replacePhiEdges(MachineBasicBlock *OldB,
MachineBasicBlock::iterator P, N = SB->getFirstNonPHI();
for (P = SB->begin(); P != N; ++P) {
MachineInstr &PN = *P;
for (MIOperands MO(PN); MO.isValid(); ++MO)
if (MO->isMBB() && MO->getMBB() == OldB)
MO->setMBB(NewB);
for (MachineOperand &MO : PN.operands())
if (MO.isMBB() && MO.getMBB() == OldB)
MO.setMBB(NewB);
}
}
}

6
lib/Target/Hexagon/HexagonGenInsert.cpp
View File

@ -1444,10 +1444,10 @@ bool HexagonGenInsert::removeDeadCode(MachineDomTreeNode *N) {
bool AllDead = true;
SmallVector<unsigned,2> Regs;
for (ConstMIOperands Op(*MI); Op.isValid(); ++Op) {
if (!Op->isReg() || !Op->isDef())
for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
unsigned R = Op->getReg();
unsigned R = MO.getReg();
if (!TargetRegisterInfo::isVirtualRegister(R) ||
!MRI->use_nodbg_empty(R)) {
AllDead = false;

8
lib/Target/Hexagon/HexagonGenMux.cpp
View File

@ -132,11 +132,11 @@ void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs,
expandReg(*R++, Uses);
// Look over all operands, and collect explicit defs and uses.
for (ConstMIOperands Mo(*MI); Mo.isValid(); ++Mo) {
if (!Mo->isReg() || Mo->isImplicit())
for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || MO.isImplicit())
continue;
unsigned R = Mo->getReg();
BitVector &Set = Mo->isDef() ? Defs : Uses;
unsigned R = MO.getReg();
BitVector &Set = MO.isDef() ? Defs : Uses;
expandReg(R, Set);
}
}

6
lib/Target/Hexagon/HexagonGenPredicate.cpp
View File

@ -330,9 +330,9 @@ bool HexagonGenPredicate::isScalarPred(Register PredReg) {
case Hexagon::C4_or_orn:
case Hexagon::C2_xor:
// Add operands to the queue.
for (ConstMIOperands Mo(*DefI); Mo.isValid(); ++Mo)
if (Mo->isReg() && Mo->isUse())
WorkQ.push(Register(Mo->getReg()));
for (const MachineOperand &MO : DefI->operands())
if (MO.isReg() && MO.isUse())
WorkQ.push(Register(MO.getReg()));
break;
// All non-vector compares are ok, everything else is bad.

6
lib/Target/Hexagon/HexagonHazardRecognizer.cpp
View File

@ -96,9 +96,9 @@ void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) {
// Keep the set of definitions for each packet, which is used to determine
// if a .new can be used.
for (ConstMIOperands MO(*MI); MO.isValid(); ++MO)
if (MO->isReg() && MO->isDef() && !MO->isImplicit())
RegDefs.insert(MO->getReg());
for (const MachineOperand &MO : MI->operands())
if (MO.isReg() && MO.isDef() && !MO.isImplicit())
RegDefs.insert(MO.getReg());
if (TII->isZeroCost(MI->getOpcode()))
return;