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test/CodeGen/X86: FileCheck-ize and add actions for x86_64-linux and x86_64-win32.

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llvm-svn: 127734
This commit is contained in:
NAKAMURA Takumi 2011-03-16 13:53:07 +00:00
parent aa13f3550e
commit 7fd500c31d
10 changed files with 54 additions and 24 deletions
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7
test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll
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@ -1,5 +1,8 @@
; RUN: llc %s -o - -march=x86-64 | grep {(%rdi,%rax,8)}
; RUN: llc %s -o - -march=x86-64 | not grep {addq.*8}
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
; CHECK-NOT: {{addq.*8}}
; CHECK: ({{%rdi|%rcx}},%rax,8)
; CHECK-NOT: {{addq.*8}}
define void @foo(double* %y) nounwind {
entry:

6
test/CodeGen/X86/2007-07-18-Vector-Extract.ll
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@ -1,5 +1,7 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse | grep {movq (%rdi), %rax}
; RUN: llc < %s -march=x86-64 -mattr=+sse | grep {movq 8(%rdi), %rax}
; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse | FileCheck %s
; CHECK: movq ([[A0:%rdi|%rcx]]), %rax
; CHECK: movq 8([[A0]]), %rax
define i64 @foo_0(<2 x i64>* %val) {
entry:
%val12 = getelementptr <2 x i64>* %val, i32 0, i32 0 ; <i64*> [#uses=1]

4
test/CodeGen/X86/avoid-lea-scale2.ll
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@ -1,4 +1,6 @@
; RUN: llc < %s -march=x86-64 | grep {leal.*-2(\[%\]rdi,\[%\]rdi)}
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
; CHECK: leal -2({{%rdi,%rdi|%rcx,%rcx}})
define i32 @foo(i32 %x) nounwind readnone {
%t0 = shl i32 %x, 1

10
test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
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@ -1,6 +1,10 @@
; RUN: llc < %s -march=x86-64 -o %t -stats -info-output-file - | \
; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 9
; RUN: grep {leal 1(\%rsi),} %t
; RUN: llc < %s -mtriple=x86_64-linux -o /dev/null -stats |& FileCheck %s -check-prefix=STATS
; RUN: llc < %s -mtriple=x86_64-win32 -o /dev/null -stats |& FileCheck %s -check-prefix=STATS
; STATS: 9 asm-printer
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
; CHECK: leal 1({{%rsi|%rdx}}),
define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2, i8* %ptr) nounwind optsize {
entry:

8
test/CodeGen/X86/i64-mem-copy.ll
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@ -1,5 +1,9 @@
; RUN: llc < %s -march=x86-64 | grep {movq.*(%rsi), %rax}
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {movsd.*(%eax),}
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=X64
; X64: movq ({{%rsi|%rdx}}), %r
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X32
; X32: movsd (%eax), %xmm
; Uses movsd to load / store i64 values if sse2 is available.

15
test/CodeGen/X86/lea-3.ll
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@ -1,16 +1,19 @@
; RUN: llc < %s -march=x86-64 | grep {leal (%rdi,%rdi,2), %eax}
define i32 @test(i32 %a) {
%tmp2 = mul i32 %a, 3 ; <i32> [#uses=1]
ret i32 %tmp2
}
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
; RUN: llc < %s -march=x86-64 | grep {leaq (,%rdi,4), %rax}
; CHECK: leaq (,[[A0:%rdi|%rcx]],4), %rax
define i64 @test2(i64 %a) {
%tmp2 = shl i64 %a, 2
%tmp3 = or i64 %tmp2, %a
ret i64 %tmp3
}
; CHECK: leal ([[A0]],[[A0]],2), %eax
define i32 @test(i32 %a) {
%tmp2 = mul i32 %a, 3 ; <i32> [#uses=1]
ret i32 %tmp2
}
;; TODO! LEA instead of shift + copy.
define i64 @test3(i64 %a) {
%tmp2 = shl i64 %a, 3

10
test/CodeGen/X86/mmx-copy-gprs.ll
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@ -1,6 +1,10 @@
; RUN: llc < %s -march=x86-64 | grep {movq.*(%rsi), %rax}
; RUN: llc < %s -march=x86 -mattr=-sse2 | grep {movl.*4(%eax),}
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {movsd.(%eax),}
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=X64
; X64: movq ({{%rsi|%rdx}}), %rax
; RUN: llc < %s -march=x86 -mattr=-sse2 | FileCheck %s -check-prefix=X32
; X32: movl 4(%eax),
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=XMM
; XMM: movsd (%eax),
; This test should use GPRs to copy the mmx value, not MMX regs. Using mmx regs,
; increases the places that need to use emms.

7
test/CodeGen/X86/vec_set-8.ll
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@ -1,5 +1,8 @@
; RUN: llc < %s -march=x86-64 | not grep movsd
; RUN: llc < %s -march=x86-64 | grep {movd.*%rdi,.*%xmm0}
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
; CHECK-NOT: movsd
; CHECK: movd {{%rdi|%rcx}}, %xmm0
; CHECK-NOT: movsd
define <2 x i64> @test(i64 %i) nounwind {
entry:

7
test/CodeGen/X86/vec_shuffle-17.ll
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@ -1,5 +1,8 @@
; RUN: llc < %s -march=x86-64 | grep {movd.*%rdi, %xmm0}
; RUN: llc < %s -march=x86-64 | not grep xor
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
; CHECK-NOT: xor
; CHECK: movd {{%rdi|%rcx}}, %xmm0
; CHECK-NOT: xor
; PR2108
define <2 x i64> @doload64(i64 %x) nounwind {

4
test/CodeGen/X86/x86-64-malloc.ll
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@ -1,4 +1,6 @@
; RUN: llc < %s -march=x86-64 | grep {shll.*3, %edi}
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
; CHECK: shll $3, {{%edi|%ecx}}
; PR3829
; The generated code should multiply by 3 (sizeof i8*) as an i32,
; not as an i64!