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[AArch64] Update test checks on merge-store-dependency.ll. NFC

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This commit is contained in:
David Green 2019-11-05 09:01:32 +00:00
parent 974677b856
commit 7fddf6fd7d
1 changed files with 42 additions and 4 deletions
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46
test/CodeGen/AArch64/merge-store-dependency.ll
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@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu cortex-a53 -mtriple=aarch64-eabi | FileCheck %s --check-prefix=A53
; PR26827 - Merge stores causes wrong dependency.
@ -7,11 +8,48 @@
define void @test(%struct1* %fde, i32 %fd, void (i32, i32, i8*)* %func, i8* %arg) {
;CHECK-LABEL: test
; A53-LABEL: test:
; A53: // %bb.0: // %entry
; A53-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
; A53-NEXT: .cfi_def_cfa_offset 16
; A53-NEXT: .cfi_offset w19, -8
; A53-NEXT: .cfi_offset w30, -16
; A53-NEXT: movi v0.2d, #0000000000000000
; A53-NEXT: mov x8, x0
; A53-NEXT: mov x19, x8
; A53-NEXT: mov w9, #256
; A53-NEXT: mov w0, w1
; A53-NEXT: str q0, [x8]
; A53-NEXT: str q0, [x19, #16]!
; A53-NEXT: strh w9, [x8, #24]
; A53-NEXT: str w1, [x19]
; A53-NEXT: mov w1, #4
; A53-NEXT: stp x2, x3, [x8, #32]
; A53-NEXT: mov x2, x8
; A53-NEXT: str wzr, [x8, #20]
; A53-NEXT: bl fcntl
; A53-NEXT: adrp x9, gv0
; A53-NEXT: add x9, x9, :lo12:gv0
; A53-NEXT: cmp x19, x9
; A53-NEXT: b.eq .LBB0_4
; A53-NEXT: // %bb.1:
; A53-NEXT: ldr w8, [x19]
; A53-NEXT: ldr w9, [x9]
; A53-NEXT: .LBB0_2: // %while.body.i.split.ver.us
; A53-NEXT: // =>This Inner Loop Header: Depth=1
; A53-NEXT: lsl w9, w9, #1
; A53-NEXT: cmp w9, w8
; A53-NEXT: b.le .LBB0_2
; A53-NEXT: // %bb.3: // %while.end.i
; A53-NEXT: bl foo
; A53-NEXT: adrp x8, gv1
; A53-NEXT: str x0, [x8, :lo12:gv1]
; A53-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; A53-NEXT: ret
; A53-NEXT: .LBB0_4: // %while.body.i.split
; A53-NEXT: // =>This Inner Loop Header: Depth=1
; A53-NEXT: b .LBB0_4
entry:
; A53: mov [[DATA:w[0-9]+]], w1
; A53: str q{{[0-9]+}}, {{.*}}
; A53: str q{{[0-9]+}}, {{.*}}
; A53: str w1, {{.*}}
%0 = bitcast %struct1* %fde to i8*
tail call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 40, i1 false)