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[AArch64][GlobalISel] Make <8 x s16> and <16 x s8> legal types for G_SHUFFLE_VECTOR and G_IMPLICIT_DEF.

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Trivial change, we're still missing support for rev matching for these types
in the combiner.
This commit is contained in:
Amara Emerson 2020-07-26 00:46:29 -07:00
parent 98c2717f20
commit 8003a99b34
4 changed files with 84 additions and 22 deletions
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4
lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
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@ -62,7 +62,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
}
getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_FREEZE})
.legalFor({p0, s1, s8, s16, s32, s64, v2s32, v4s32, v2s64})
.legalFor({p0, s1, s8, s16, s32, s64, v2s32, v4s32, v2s64, v16s8, v8s16})
.clampScalar(0, s1, s64)
.widenScalarToNextPow2(0, 8)
.fewerElementsIf(
@ -596,7 +596,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// to be the same size as the dest.
if (DstTy != SrcTy)
return false;
for (auto &Ty : {v2s32, v4s32, v2s64}) {
for (auto &Ty : {v2s32, v4s32, v2s64, v16s8, v8s16}) {
if (DstTy == Ty)
return true;
}

44
test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
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@ -43,6 +43,50 @@ body: |
$q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: shuffle_v16i8
alignment: 4
tracksRegLiveness: true
body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: shuffle_v16i8
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[SHUF:%[0-9]+]]:_(<16 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<16 x s8>), [[COPY1]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
; CHECK: $q0 = COPY [[SHUF]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
%2:_(<16 x s8>) = G_SHUFFLE_VECTOR %0(<16 x s8>), %1, shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
$q0 = COPY %2(<16 x s8>)
RET_ReallyLR implicit $q0
...
---
name: shuffle_v8i16
alignment: 4
tracksRegLiveness: true
body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: shuffle_v8i16
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK: [[SHUF:%[0-9]+]]:_(<8 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<8 x s16>), [[COPY1]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
; CHECK: $q0 = COPY [[SHUF]](<8 x s16>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<8 x s16>) = COPY $q0
%1:_(<8 x s16>) = COPY $q1
%2:_(<8 x s16>) = G_SHUFFLE_VECTOR %0(<8 x s16>), %1, shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
$q0 = COPY %2(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: shuffle_1elt_mask

22
test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
View File

@ -77,3 +77,25 @@ body: |
$w0 = COPY %1
$w1 = COPY %2
...
---
name: test_implicit_def_v16s8
body: |
bb.0:
; CHECK-LABEL: name: test_implicit_def_v16s8
; CHECK: [[DEF:%[0-9]+]]:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK: $q0 = COPY [[DEF]](<16 x s8>)
%0:_(<16 x s8>) = G_IMPLICIT_DEF
$q0 = COPY %0
...
---
name: test_implicit_def_v8s16
body: |
bb.0:
; CHECK-LABEL: name: test_implicit_def_v8s16
; CHECK: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK: $q0 = COPY [[DEF]](<8 x s16>)
%0:_(<8 x s16>) = G_IMPLICIT_DEF
$q0 = COPY %0
...

36
test/CodeGen/AArch64/arm64-rev.ll
View File

@ -426,11 +426,10 @@ define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
; CHECK-NEXT: rev32.16b v0, v0
; CHECK-NEXT: ret
;
; FALLBACK-LABEL: test_vrev32Q8:
; FALLBACK: // %bb.0:
; FALLBACK-NEXT: ldr q0, [x0]
; FALLBACK-NEXT: rev32.16b v0, v0
; FALLBACK-NEXT: ret
; GISEL-LABEL: test_vrev32Q8:
; GISEL: // %bb.0:
; GISEL: tbl.16b v0, { v0, v1 }, v2
; GISEL: ret
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
ret <16 x i8> %tmp2
@ -443,11 +442,10 @@ define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
; CHECK-NEXT: rev32.8h v0, v0
; CHECK-NEXT: ret
;
; FALLBACK-LABEL: test_vrev32Q16:
; FALLBACK: // %bb.0:
; FALLBACK-NEXT: ldr q0, [x0]
; FALLBACK-NEXT: rev32.8h v0, v0
; FALLBACK-NEXT: ret
; GISEL-LABEL: test_vrev32Q16:
; GISEL: // %bb.0:
; GISEL: tbl.16b v0, { v0, v1 }, v2
; GISEL: ret
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
ret <8 x i16> %tmp2
@ -477,11 +475,10 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
; CHECK-NEXT: rev16.16b v0, v0
; CHECK-NEXT: ret
;
; FALLBACK-LABEL: test_vrev16Q8:
; FALLBACK: // %bb.0:
; FALLBACK-NEXT: ldr q0, [x0]
; FALLBACK-NEXT: rev16.16b v0, v0
; FALLBACK-NEXT: ret
; GISEL-LABEL: test_vrev16Q8:
; GISEL: // %bb.0:
; GISEL: tbl.16b v0, { v0, v1 }, v2
; GISEL: ret
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
ret <16 x i8> %tmp2
@ -513,11 +510,10 @@ define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
; CHECK-NEXT: rev32.8h v0, v0
; CHECK-NEXT: ret
;
; FALLBACK-LABEL: test_vrev32Q16_undef:
; FALLBACK: // %bb.0:
; FALLBACK-NEXT: ldr q0, [x0]
; FALLBACK-NEXT: rev32.8h v0, v0
; FALLBACK-NEXT: ret
; GISEL-LABEL: test_vrev32Q16_undef:
; GISEL: // %bb.0:
; GISEL: tbl.16b v0, { v0, v1 }, v2
; GISEL: ret
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
ret <8 x i16> %tmp2