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[PowerPC] Add options to control paired vector memops support

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Adds frontend and backend options to enable and disable the
PowerPC paired vector memory operations added in ISA 3.1.
Instructions using these options will be added in subsequent patches.

Differential Revision: https://reviews.llvm.org/D83722
This commit is contained in:
Baptiste Saleil 2020-07-28 16:02:50 -05:00 committed by Lei Huang
parent 05810ce897
commit 8004150937
6 changed files with 19 additions and 9 deletions
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6
lib/Target/PowerPC/PPC.td
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@ -234,6 +234,10 @@ def FeaturePCRelativeMemops :
SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
"Enable PC relative Memory Ops", "Enable PC relative Memory Ops",
[FeatureISA3_0]>; [FeatureISA3_0]>;
def FeaturePairedVectorMemops:
SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
"32Byte load and store instructions",
[FeatureISA3_0]>;
def FeaturePredictableSelectIsExpensive : def FeaturePredictableSelectIsExpensive :
SubtargetFeature<"predictable-select-expensive", SubtargetFeature<"predictable-select-expensive",
@ -339,7 +343,7 @@ def ProcessorFeatures {
// still exist with the exception of those we know are Power9 specific. // still exist with the exception of those we know are Power9 specific.
list<SubtargetFeature> P10AdditionalFeatures = list<SubtargetFeature> P10AdditionalFeatures =
[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
FeaturePCRelativeMemops, FeatureP10Vector]; FeaturePCRelativeMemops, FeatureP10Vector, FeaturePairedVectorMemops];
list<SubtargetFeature> P10SpecificFeatures = []; list<SubtargetFeature> P10SpecificFeatures = [];
list<SubtargetFeature> P10InheritableFeatures = list<SubtargetFeature> P10InheritableFeatures =
!listconcat(P9InheritableFeatures, P10AdditionalFeatures); !listconcat(P9InheritableFeatures, P10AdditionalFeatures);

1
lib/Target/PowerPC/PPCInstrPrefix.td
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@ -454,6 +454,7 @@ multiclass 8LS_DForm_R_SI34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL,
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
let Predicates = [PrefixInstrs] in { let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {

6
lib/Target/PowerPC/PPCScheduleP9.td
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@ -41,8 +41,10 @@ def P9Model : SchedMachineModel {
let CompleteModel = 1; let CompleteModel = 1;
// Do not support SPE (Signal Processing Engine), prefixed instructions on // Do not support SPE (Signal Processing Engine), prefixed instructions on
// Power 9, PC relative mem ops, or instructions introduced in ISA 3.1. // Power 9, paired vector mem ops, PC relative mem ops, or instructions
let UnsupportedFeatures = [HasSPE, PrefixInstrs, PCRelativeMemops, IsISA3_1]; // introduced in ISA 3.1.
let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops,
PCRelativeMemops, IsISA3_1];
} }
let SchedModel = P9Model in { let SchedModel = P9Model in {

1
lib/Target/PowerPC/PPCSubtarget.cpp
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@ -116,6 +116,7 @@ void PPCSubtarget::initializeEnvironment() {
VectorsUseTwoUnits = false; VectorsUseTwoUnits = false;
UsePPCPreRASchedStrategy = false; UsePPCPreRASchedStrategy = false;
UsePPCPostRASchedStrategy = false; UsePPCPostRASchedStrategy = false;
PairedVectorMemops = false;
PredictableSelectIsExpensive = false; PredictableSelectIsExpensive = false;
HasPOPCNTD = POPCNTD_Unavailable; HasPOPCNTD = POPCNTD_Unavailable;

2
lib/Target/PowerPC/PPCSubtarget.h
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@ -145,6 +145,7 @@ protected:
bool VectorsUseTwoUnits; bool VectorsUseTwoUnits;
bool UsePPCPreRASchedStrategy; bool UsePPCPreRASchedStrategy;
bool UsePPCPostRASchedStrategy; bool UsePPCPostRASchedStrategy;
bool PairedVectorMemops;
bool PredictableSelectIsExpensive; bool PredictableSelectIsExpensive;
POPCNTDKind HasPOPCNTD; POPCNTDKind HasPOPCNTD;
@ -259,6 +260,7 @@ public:
bool hasP10Vector() const { return HasP10Vector; } bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; } bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; } bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; } bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; } bool hasISEL() const { return HasISEL; }
bool hasBPERMD() const { return HasBPERMD; } bool hasBPERMD() const { return HasBPERMD; }

12
test/CodeGen/PowerPC/future-check-features.ll
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@ -1,9 +1,9 @@
; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \ ; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \ ; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: %s -o - 2>&1 | FileCheck %s ; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \ ; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
; RUN: -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \ ; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
; RUN: %s -o - 2>&1 | FileCheck %s ; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
define dso_local signext i32 @f() { define dso_local signext i32 @f() {
entry: entry: