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[X86] Handle SETB_C32r/SETB_C64r in flag copy lowering the same way we handle SBB
Previously we took the restored flag in a GPR, extended it 32 or 64 bits. Then used as an input to a sub from 0. This requires creating a zero extend and creating a 0. This patch changes this to just use an ADD with 255 to restore the carry flag and keep the SETB_C32r/SETB_C64r. Exactly like we handle SBB which is what SETB becomes. Differential Revision: https://reviews.llvm.org/D74152
This commit is contained in:
Craig Topper
parent
44c3fb4d1f
commit
80102bc644
@ -124,10 +124,6 @@ private:
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MachineInstr &JmpI, CondRegArray &CondRegs);
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void rewriteCopy(MachineInstr &MI, MachineOperand &FlagUse,
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MachineInstr &CopyDefI);
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void rewriteSetCarryExtended(MachineBasicBlock &TestMBB,
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MachineBasicBlock::iterator TestPos,
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DebugLoc TestLoc, MachineInstr &SetBI,
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MachineOperand &FlagUse, CondRegArray &CondRegs);
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void rewriteSetCC(MachineBasicBlock &TestMBB,
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MachineBasicBlock::iterator TestPos, DebugLoc TestLoc,
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MachineInstr &SetCCI, MachineOperand &FlagUse,
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@ -165,6 +161,7 @@ enum class FlagArithMnemonic {
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RCL,
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RCR,
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SBB,
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SETB,
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};
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} // namespace
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@ -235,6 +232,10 @@ static FlagArithMnemonic getMnemonicFromOpcode(unsigned Opcode) {
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case X86::ADOX32rm:
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case X86::ADOX64rm:
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return FlagArithMnemonic::ADOX;
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case X86::SETB_C32r:
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case X86::SETB_C64r:
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return FlagArithMnemonic::SETB;
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}
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}
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@ -638,22 +639,9 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) {
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// logic.
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FlagsKilled = true;
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switch (MI.getOpcode()) {
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case X86::SETB_C32r:
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case X86::SETB_C64r:
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// Use custom lowering for arithmetic that is merely extending the
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// carry flag. We model this as the SETB_C* pseudo instructions.
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rewriteSetCarryExtended(*TestMBB, TestPos, TestLoc, MI, *FlagUse,
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CondRegs);
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break;
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default:
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// Generically handle remaining uses as arithmetic instructions.
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rewriteArithmetic(*TestMBB, TestPos, TestLoc, MI, *FlagUse,
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CondRegs);
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break;
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}
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break;
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// Generically handle remaining uses as arithmetic instructions.
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rewriteArithmetic(*TestMBB, TestPos, TestLoc, MI, *FlagUse,
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CondRegs);
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}
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// If this was the last use of the flags, we're done.
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@ -819,6 +807,7 @@ void X86FlagsCopyLoweringPass::rewriteArithmetic(
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case FlagArithMnemonic::RCL:
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case FlagArithMnemonic::RCR:
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case FlagArithMnemonic::SBB:
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case FlagArithMnemonic::SETB:
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Cond = X86::COND_B; // CF == 1
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// Set up an addend that when one is added will need a carry due to not
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// having a higher bit available.
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@ -957,115 +946,6 @@ void X86FlagsCopyLoweringPass::rewriteCopy(MachineInstr &MI,
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MI.eraseFromParent();
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}
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void X86FlagsCopyLoweringPass::rewriteSetCarryExtended(
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MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,
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DebugLoc TestLoc, MachineInstr &SetBI, MachineOperand &FlagUse,
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CondRegArray &CondRegs) {
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// This routine is only used to handle pseudos for setting a register to zero
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// or all ones based on CF. This is essentially the sign extended from 1-bit
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// form of SETB and modeled with the SETB_C* pseudos. They require special
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// handling as they aren't normal SETcc instructions and are lowered to an
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// EFLAGS clobbering operation (SBB typically). One simplifying aspect is that
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// they are only provided in reg-defining forms. A complicating factor is that
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// they can define many different register widths.
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assert(SetBI.getOperand(0).isReg() &&
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"Cannot have a non-register defined operand to this variant of SETB!");
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// Little helper to do the common final step of replacing the register def'ed
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// by this SETB instruction with a new register and removing the SETB
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// instruction.
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auto RewriteToReg = [&](unsigned Reg) {
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MRI->replaceRegWith(SetBI.getOperand(0).getReg(), Reg);
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SetBI.eraseFromParent();
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};
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// Grab the register class used for this particular instruction.
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auto &SetBRC = *MRI->getRegClass(SetBI.getOperand(0).getReg());
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MachineBasicBlock &MBB = *SetBI.getParent();
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auto SetPos = SetBI.getIterator();
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auto SetLoc = SetBI.getDebugLoc();
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auto AdjustReg = [&](unsigned Reg) {
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auto &OrigRC = *MRI->getRegClass(Reg);
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if (&OrigRC == &SetBRC)
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return Reg;
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unsigned NewReg;
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int OrigRegSize = TRI->getRegSizeInBits(OrigRC) / 8;
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int TargetRegSize = TRI->getRegSizeInBits(SetBRC) / 8;
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assert(OrigRegSize <= 8 && "No GPRs larger than 64-bits!");
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assert(TargetRegSize <= 8 && "No GPRs larger than 64-bits!");
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int SubRegIdx[] = {X86::NoSubRegister, X86::sub_8bit, X86::sub_16bit,
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X86::NoSubRegister, X86::sub_32bit};
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// If the original size is smaller than the target *and* is smaller than 4
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// bytes, we need to explicitly zero extend it. We always extend to 4-bytes
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// to maximize the chance of being able to CSE that operation and to avoid
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// partial dependency stalls extending to 2-bytes.
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if (OrigRegSize < TargetRegSize && OrigRegSize < 4) {
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NewReg = MRI->createVirtualRegister(&X86::GR32RegClass);
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BuildMI(MBB, SetPos, SetLoc, TII->get(X86::MOVZX32rr8), NewReg)
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.addReg(Reg);
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if (&SetBRC == &X86::GR32RegClass)
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return NewReg;
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Reg = NewReg;
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OrigRegSize = 4;
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}
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NewReg = MRI->createVirtualRegister(&SetBRC);
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if (OrigRegSize < TargetRegSize) {
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BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::SUBREG_TO_REG),
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NewReg)
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.addImm(0)
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.addReg(Reg)
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.addImm(SubRegIdx[OrigRegSize]);
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} else if (OrigRegSize > TargetRegSize) {
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if (TargetRegSize == 1 && !Subtarget->is64Bit()) {
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// Need to constrain the register class.
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MRI->constrainRegClass(Reg, &X86::GR32_ABCDRegClass);
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}
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BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::COPY),
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NewReg)
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.addReg(Reg, 0, SubRegIdx[TargetRegSize]);
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} else {
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BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::COPY), NewReg)
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.addReg(Reg);
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}
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return NewReg;
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};
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unsigned &CondReg = CondRegs[X86::COND_B];
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if (!CondReg)
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CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, X86::COND_B);
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// Adjust the condition to have the desired register width by zero-extending
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// as needed.
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// FIXME: We should use a better API to avoid the local reference and using a
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// different variable here.
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unsigned ExtCondReg = AdjustReg(CondReg);
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// Now we need to turn this into a bitmask. We do this by subtracting it from
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// zero.
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Register ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass);
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BuildMI(MBB, SetPos, SetLoc, TII->get(X86::MOV32r0), ZeroReg);
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ZeroReg = AdjustReg(ZeroReg);
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unsigned Sub;
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switch (SetBI.getOpcode()) {
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default: llvm_unreachable("Invalid SETB_C* opcode!");
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case X86::SETB_C32r: Sub = X86::SUB32rr; break;
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case X86::SETB_C64r: Sub = X86::SUB64rr; break;
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}
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Register ResultReg = MRI->createVirtualRegister(&SetBRC);
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BuildMI(MBB, SetPos, SetLoc, TII->get(Sub), ResultReg)
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.addReg(ZeroReg)
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.addReg(ExtCondReg);
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return RewriteToReg(ResultReg);
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}
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void X86FlagsCopyLoweringPass::rewriteSetCC(MachineBasicBlock &TestMBB,
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MachineBasicBlock::iterator TestPos,
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DebugLoc TestLoc,
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@ -544,21 +544,17 @@ body: |
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%4:gr32 = SETB_C32r implicit-def $eflags, implicit $eflags
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MOV32mr $rsp, 1, $noreg, -16, $noreg, killed %4
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; CHECK-NOT: $eflags =
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; CHECK: %[[CF_EXT:[^:]*]]:gr32 = MOVZX32rr8 %[[CF_REG]]
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; CHECK-NEXT: %[[ZERO:[^:]*]]:gr32 = MOV32r0 implicit-def $eflags
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; CHECK-NEXT: %[[REPLACEMENT:[^:]*]]:gr32 = SUB32rr %[[ZERO]], %[[CF_EXT]]
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; CHECK-NEXT: MOV32mr $rsp, 1, $noreg, -16, $noreg, killed %[[REPLACEMENT]]
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; CHECK: dead %{{[^:]*}}:gr8 = ADD8ri %[[CF_REG]], 255, implicit-def $eflags
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; CHECK-NEXT: %[[SETB:[^:]*]]:gr32 = SETB_C32r implicit-def{{( dead)?}} $eflags, implicit{{( killed)?}} $eflags
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; CHECK-NEXT: MOV32mr $rsp, 1, $noreg, -16, $noreg, killed %[[SETB]]
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$eflags = COPY %3
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%5:gr64 = SETB_C64r implicit-def $eflags, implicit $eflags
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MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %5
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; CHECK-NOT: $eflags =
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; CHECK: %[[CF_EXT1:[^:]*]]:gr32 = MOVZX32rr8 %[[CF_REG]]
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; CHECK-NEXT: %[[CF_EXT2:[^:]*]]:gr64 = SUBREG_TO_REG 0, %[[CF_EXT1]], %subreg.sub_32bit
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; CHECK-NEXT: %[[ZERO:[^:]*]]:gr32 = MOV32r0 implicit-def $eflags
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; CHECK-NEXT: %[[ZERO_EXT:[^:]*]]:gr64 = SUBREG_TO_REG 0, %[[ZERO]], %subreg.sub_32bit
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; CHECK-NEXT: %[[REPLACEMENT:[^:]*]]:gr64 = SUB64rr %[[ZERO_EXT]], %[[CF_EXT2]]
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; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %[[REPLACEMENT]]
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; CHECK: dead %{{[^:]*}}:gr8 = ADD8ri %[[CF_REG]], 255, implicit-def $eflags
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; CHECK-NEXT: %[[SETB:[^:]*]]:gr64 = SETB_C64r implicit-def{{( dead)?}} $eflags, implicit{{( killed)?}} $eflags
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; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %[[SETB]]
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RET 0
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