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Remove caching of the target machine in NVPTXInstrInfo and
update constructor accordingly. llvm-svn: 211840
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parent
035afbc45f
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@ -29,8 +29,8 @@ using namespace llvm;
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void NVPTXInstrInfo::anchor() {}
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void NVPTXInstrInfo::anchor() {}
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// FIXME: Add the subtarget support on this constructor.
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// FIXME: Add the subtarget support on this constructor.
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NVPTXInstrInfo::NVPTXInstrInfo(NVPTXTargetMachine &tm)
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NVPTXInstrInfo::NVPTXInstrInfo(NVPTXSubtarget &STI)
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: NVPTXGenInstrInfo(), TM(tm), RegInfo(*TM.getSubtargetImpl()) {}
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: NVPTXGenInstrInfo(), RegInfo(STI) {}
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void NVPTXInstrInfo::copyPhysReg(
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void NVPTXInstrInfo::copyPhysReg(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
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MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
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@ -24,11 +24,10 @@
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namespace llvm {
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namespace llvm {
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class NVPTXInstrInfo : public NVPTXGenInstrInfo {
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class NVPTXInstrInfo : public NVPTXGenInstrInfo {
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NVPTXTargetMachine &TM;
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const NVPTXRegisterInfo RegInfo;
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const NVPTXRegisterInfo RegInfo;
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virtual void anchor();
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virtual void anchor();
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public:
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public:
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explicit NVPTXInstrInfo(NVPTXTargetMachine &TM);
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explicit NVPTXInstrInfo(NVPTXSubtarget &STI);
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const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
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const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
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@ -84,7 +84,7 @@ NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
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CodeGenOpt::Level OL, bool is64bit)
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CodeGenOpt::Level OL, bool is64bit)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, is64bit), DL(computeDataLayout(Subtarget)),
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Subtarget(TT, CPU, FS, is64bit), DL(computeDataLayout(Subtarget)),
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InstrInfo(*this), TLInfo(*this), TSInfo(&DL),
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InstrInfo(Subtarget), TLInfo(*this), TSInfo(&DL),
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FrameLowering(*this, is64bit) {
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FrameLowering(*this, is64bit) {
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initAsmInfo();
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initAsmInfo();
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}
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}
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