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Revert r185595-185596 which broke buildbots.

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Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

llvm-svn: 185600
This commit is contained in:
Jakob Stoklund Olesen 2013-07-04 00:26:30 +00:00
parent 8bc33424b2
commit 8099b21497
13 changed files with 85 additions and 25 deletions
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5
include/llvm/CodeGen/FunctionLoweringInfo.h
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@ -115,11 +115,6 @@ public:
/// there's no other convenient place for it to live right now.
std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
/// If the current MBB is a landing pad, the exception pointer and exception
/// selector registers are copied into these virtual registers by
/// SelectionDAGISel::PrepareEHLandingPad().
unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
explicit FunctionLoweringInfo(const TargetMachine &TM) : TM(TM) {}
/// set - Initialize this FunctionLoweringInfo with the given Function

12
include/llvm/CodeGen/ISDOpcodes.h
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@ -77,6 +77,18 @@ namespace ISD {
/// adjustment during unwind.
FRAME_TO_ARGS_OFFSET,
/// RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents the
/// address of the exception block on entry to an landing pad block.
EXCEPTIONADDR,
/// RESULT, OUTCHAIN = LSDAADDR(INCHAIN) - This node represents the
/// address of the Language Specific Data Area for the enclosing function.
LSDAADDR,
/// RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node
/// represents the selection index of the exception thrown.
EHSELECTION,
/// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
/// 'eh_return' gcc dwarf builtin, which is used to return from
/// exception. The general meaning is: adjust stack by OFFSET and pass

16
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -3269,6 +3269,22 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Results.push_back(ExpandConstantFP(CFP, true));
break;
}
case ISD::EHSELECTION: {
unsigned Reg = TLI.getExceptionSelectorRegister();
assert(Reg && "Can't expand to unknown register!");
Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
Node->getValueType(0)));
Results.push_back(Results[0].getValue(1));
break;
}
case ISD::EXCEPTIONADDR: {
unsigned Reg = TLI.getExceptionPointerRegister();
assert(Reg && "Can't expand to unknown register!");
Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
Node->getValueType(0)));
Results.push_back(Results[0].getValue(1));
break;
}
case ISD::FSUB: {
EVT VT = Node->getValueType(0);
assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&

34
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -1919,25 +1919,33 @@ void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
SmallVector<EVT, 2> ValueVTs;
ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
// Get the two live-in registers as SDValues. The physregs have already been
// copied into virtual registers.
// Insert the EXCEPTIONADDR instruction.
assert(FuncInfo.MBB->isLandingPad() &&
"Call to eh.exception not in landing pad!");
SDVTList VTs = DAG.getVTList(TLI->getPointerTy(), MVT::Other);
SDValue Ops[2];
Ops[0] = DAG.getZExtOrTrunc(
DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()),
getCurSDLoc(), ValueVTs[0]);
Ops[1] = DAG.getZExtOrTrunc(
DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()),
getCurSDLoc(), ValueVTs[1]);
Ops[0] = DAG.getRoot();
SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurSDLoc(), VTs, Ops, 1);
SDValue Chain = Op1.getValue(1);
// Merge into one.
// Insert the EHSELECTION instruction.
VTs = DAG.getVTList(TLI->getPointerTy(), MVT::Other);
Ops[0] = Op1;
Ops[1] = Chain;
SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurSDLoc(), VTs, Ops, 2);
Chain = Op2.getValue(1);
Op2 = DAG.getSExtOrTrunc(Op2, getCurSDLoc(), MVT::i32);
Ops[0] = Op1;
Ops[1] = Op2;
SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
&Ops[0], 2);
setValue(&LP, Res);
std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
setValue(&LP, RetPair.first);
DAG.setRoot(RetPair.second);
}
/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for

3
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
View File

@ -92,6 +92,9 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::RETURNADDR: return "RETURNADDR";
case ISD::FRAMEADDR: return "FRAMEADDR";
case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET";
case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR";
case ISD::LSDAADDR: return "LSDAADDR";
case ISD::EHSELECTION: return "EHSELECTION";
case ISD::EH_RETURN: return "EH_RETURN";
case ISD::EH_SJLJ_SETJMP: return "EH_SJLJ_SETJMP";
case ISD::EH_SJLJ_LONGJMP: return "EH_SJLJ_LONGJMP";

11
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -829,13 +829,12 @@ void SelectionDAGISel::PrepareEHLandingPad() {
// Mark exception register as live in.
const TargetLowering *TLI = getTargetLowering();
const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
if (unsigned Reg = TLI->getExceptionPointerRegister())
FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
unsigned Reg = TLI->getExceptionPointerRegister();
if (Reg) MBB->addLiveIn(Reg);
// Mark exception selector register as live in.
if (unsigned Reg = TLI->getExceptionSelectorRegister())
FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
Reg = TLI->getExceptionSelectorRegister();
if (Reg) MBB->addLiveIn(Reg);
}
/// isFoldedOrDeadInstruction - Return true if the specified instruction is
@ -973,8 +972,6 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
// Setup an EH landing-pad block.
FuncInfo->ExceptionPointerVirtReg = 0;
FuncInfo->ExceptionSelectorVirtReg = 0;
if (FuncInfo->MBB->isLandingPad())
PrepareEHLandingPad();

3
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -249,6 +249,9 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
setTruncStoreAction(MVT::f64, MVT::f16, Expand);
setTruncStoreAction(MVT::f32, MVT::f16, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
setExceptionPointerRegister(AArch64::X0);
setExceptionSelectorRegister(AArch64::X1);
}

2
lib/Target/ARM/ARMISelLowering.cpp
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@ -717,6 +717,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
if (!Subtarget->isTargetDarwin()) {
// Non-Darwin platforms may return values in these registers via the
// personality function.
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setExceptionPointerRegister(ARM::R0);
setExceptionSelectorRegister(ARM::R1);
}

5
lib/Target/Hexagon/HexagonISelLowering.cpp
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@ -1428,6 +1428,11 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
if (TM.getSubtargetImpl()->isSubtargetV2()) {

5
lib/Target/Mips/MipsISelLowering.cpp
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@ -346,6 +346,11 @@ MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::FNEG, MVT::f64, Expand);
}
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
setOperationAction(ISD::VAARG, MVT::Other, Expand);

5
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -228,6 +228,11 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
// NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
// SjLj exception handling but a light-weight setjmp/longjmp replacement to
// support continuation, user-level threading, and etc.. As a result, no

5
lib/Target/SystemZ/SystemZISelLowering.cpp
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@ -200,6 +200,11 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
// Expand these using getExceptionSelectorRegister() and
// getExceptionPointerRegister().
setOperationAction(ISD::EXCEPTIONADDR, PtrVT, Expand);
setOperationAction(ISD::EHSELECTION, PtrVT, Expand);
// Handle floating-point types.
for (unsigned I = MVT::FIRST_FP_VALUETYPE;
I <= MVT::LAST_FP_VALUETYPE;

4
lib/Target/X86/X86ISelLowering.cpp
View File

@ -563,6 +563,10 @@ void X86TargetLowering::resetOperationActions() {
setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
}
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
if (Subtarget->is64Bit()) {
setExceptionPointerRegister(X86::RAX);
setExceptionSelectorRegister(X86::RDX);