From 809a4483be000de293d9f1661e56ca685a5e9496 Mon Sep 17 00:00:00 2001
From: Evandro Menezes <evandro.menezes@sifive.com>
Date: Thu, 8 Oct 2020 16:20:24 -0500
Subject: [PATCH] [RISCV] Use the commercial name for scheduling model (NFC)

Use the commercial name for the scheduling model for the SiFive 7 Series.
---
 lib/Target/RISCV/RISCV.td             |  26 +--
 lib/Target/RISCV/RISCVSchedBullet.td  | 224 --------------------------
 lib/Target/RISCV/RISCVSchedSiFive7.td | 222 +++++++++++++++++++++++++
 3 files changed, 235 insertions(+), 237 deletions(-)
 delete mode 100644 lib/Target/RISCV/RISCVSchedBullet.td
 create mode 100644 lib/Target/RISCV/RISCVSchedSiFive7.td

diff --git a/lib/Target/RISCV/RISCV.td b/lib/Target/RISCV/RISCV.td
index 1b2c471faac..3d942815f20 100644
--- a/lib/Target/RISCV/RISCV.td
+++ b/lib/Target/RISCV/RISCV.td
@@ -216,7 +216,7 @@ include "RISCVCallingConv.td"
 include "RISCVInstrInfo.td"
 include "RISCVRegisterBanks.td"
 include "RISCVSchedRocket.td"
-include "RISCVSchedBullet.td"
+include "RISCVSchedSiFive7.td"
 
 //===----------------------------------------------------------------------===//
 // RISC-V processors supported.
@@ -228,8 +228,8 @@ def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
 def : ProcessorModel<"rocket-rv32", RocketModel, []>;
 def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
 
-def : ProcessorModel<"sifive-7-rv32", BulletModel, []>;
-def : ProcessorModel<"sifive-7-rv64", BulletModel, [Feature64Bit]>;
+def : ProcessorModel<"sifive-7-rv32", SiFive7Model, []>;
+def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit]>;
 
 def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
                                                  FeatureStdExtA,
@@ -242,17 +242,17 @@ def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
                                                  FeatureStdExtD,
                                                  FeatureStdExtC]>;
 
-def : ProcessorModel<"sifive-e76", BulletModel, [FeatureStdExtM,
-                                                 FeatureStdExtA,
-                                                 FeatureStdExtF,
-                                                 FeatureStdExtC]>;
+def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM,
+                                                  FeatureStdExtA,
+                                                  FeatureStdExtF,
+                                                  FeatureStdExtC]>;
 
-def : ProcessorModel<"sifive-u74", BulletModel, [Feature64Bit,
-                                                 FeatureStdExtM,
-                                                 FeatureStdExtA,
-                                                 FeatureStdExtF,
-                                                 FeatureStdExtD,
-                                                 FeatureStdExtC]>;
+def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
+                                                  FeatureStdExtM,
+                                                  FeatureStdExtA,
+                                                  FeatureStdExtF,
+                                                  FeatureStdExtD,
+                                                  FeatureStdExtC]>;
 
 //===----------------------------------------------------------------------===//
 // Define the RISC-V target.
diff --git a/lib/Target/RISCV/RISCVSchedBullet.td b/lib/Target/RISCV/RISCVSchedBullet.td
deleted file mode 100644
index 32e28c25e0e..00000000000
--- a/lib/Target/RISCV/RISCVSchedBullet.td
+++ /dev/null
@@ -1,224 +0,0 @@
-//==- RISCVSchedBullet.td - Bullet Scheduling Definitions ----*- tablegen -*-=//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// The following definitions describe the simpler per-operand machine model.
-// This works with MachineScheduler. See MCSchedule.h for details.
-
-// Bullet machine model for scheduling and other instruction cost heuristics.
-def BulletModel : SchedMachineModel {
-  let MicroOpBufferSize = 0; // Explicitly set to zero since Bullet is in-order.
-  let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
-  let LoadLatency = 3;
-  let MispredictPenalty = 3;
-  let CompleteModel = 0;
-  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg];
-}
-
-// The Bullet microarchitecure has two pipelines: A and B.
-// Pipe A can handle memory, integer alu and vector operations.
-// Pipe B can handle integer alu, control flow, integer multiply and divide,
-// and floating point computation.
-let SchedModel = BulletModel in {
-let BufferSize = 0 in {
-def BulletPipeA       : ProcResource<1>;
-def BulletPipeB       : ProcResource<1>;
-}
-
-let BufferSize = 1 in {
-def BulletIDiv        : ProcResource<1> { let Super = BulletPipeB; } // Int Division
-def BulletFDiv        : ProcResource<1> { let Super = BulletPipeB; } // FP Division/Sqrt
-}
-
-def BulletPipeAB : ProcResGroup<[BulletPipeA, BulletPipeB]>;
-
-// Branching
-def : WriteRes<WriteJmp, [BulletPipeB]>;
-def : WriteRes<WriteJal, [BulletPipeB]>;
-def : WriteRes<WriteJalr, [BulletPipeB]>;
-def : WriteRes<WriteJmpReg, [BulletPipeB]>;
-
-// Integer arithmetic and logic
-let Latency = 3 in {
-def : WriteRes<WriteIALU, [BulletPipeAB]>;
-def : WriteRes<WriteIALU32, [BulletPipeAB]>;
-def : WriteRes<WriteShift, [BulletPipeAB]>;
-def : WriteRes<WriteShift32, [BulletPipeAB]>;
-}
-
-// Integer multiplication
-let Latency = 3 in {
-def : WriteRes<WriteIMul, [BulletPipeB]>;
-def : WriteRes<WriteIMul32, [BulletPipeB]>;
-}
-
-// Integer division
-def : WriteRes<WriteIDiv, [BulletPipeB, BulletIDiv]> {
-  let Latency = 16;
-  let ResourceCycles = [1, 15];
-}
-def : WriteRes<WriteIDiv32,  [BulletPipeB, BulletIDiv]> {
-  let Latency = 16;
-  let ResourceCycles = [1, 15];
-}
-
-// Memory
-def : WriteRes<WriteSTB, [BulletPipeA]>;
-def : WriteRes<WriteSTH, [BulletPipeA]>;
-def : WriteRes<WriteSTW, [BulletPipeA]>;
-def : WriteRes<WriteSTD, [BulletPipeA]>;
-def : WriteRes<WriteFST32, [BulletPipeA]>;
-def : WriteRes<WriteFST64, [BulletPipeA]>;
-
-let Latency = 3 in {
-def : WriteRes<WriteLDB, [BulletPipeA]>;
-def : WriteRes<WriteLDH, [BulletPipeA]>;
-def : WriteRes<WriteLDW, [BulletPipeA]>;
-def : WriteRes<WriteLDWU, [BulletPipeA]>;
-def : WriteRes<WriteLDD, [BulletPipeA]>;
-}
-
-let Latency = 2 in {
-def : WriteRes<WriteFLD32, [BulletPipeA]>;
-def : WriteRes<WriteFLD64, [BulletPipeA]>;
-}
-
-// Atomic memory
-def : WriteRes<WriteAtomicSTW, [BulletPipeA]>;
-def : WriteRes<WriteAtomicSTD, [BulletPipeA]>;
-
-let Latency = 3 in {
-def : WriteRes<WriteAtomicW, [BulletPipeA]>;
-def : WriteRes<WriteAtomicD, [BulletPipeA]>;
-def : WriteRes<WriteAtomicLDW, [BulletPipeA]>;
-def : WriteRes<WriteAtomicLDD, [BulletPipeA]>;
-}
-
-// Single precision.
-let Latency = 5 in {
-def : WriteRes<WriteFALU32, [BulletPipeB]>;
-def : WriteRes<WriteFMul32, [BulletPipeB]>;
-def : WriteRes<WriteFMulAdd32, [BulletPipeB]>;
-def : WriteRes<WriteFMulSub32, [BulletPipeB]>;
-}
-let Latency = 3 in {
-def : WriteRes<WriteFSGNJ32, [BulletPipeB]>;
-def : WriteRes<WriteFMinMax32, [BulletPipeB]>;
-}
-
-def : WriteRes<WriteFDiv32, [BulletPipeB, BulletFDiv]> { let Latency = 27;
-                                                         let ResourceCycles = [1, 26]; }
-def : WriteRes<WriteFSqrt32, [BulletPipeB, BulletFDiv]> { let Latency = 27;
-                                                          let ResourceCycles = [1, 26]; }
-
-// Double precision
-let Latency = 7 in {
-def : WriteRes<WriteFALU64, [BulletPipeB]>;
-def : WriteRes<WriteFMul64, [BulletPipeB]>;
-def : WriteRes<WriteFMulAdd64, [BulletPipeB]>;
-def : WriteRes<WriteFMulSub64, [BulletPipeB]>;
-}
-let Latency = 3 in {
-def : WriteRes<WriteFSGNJ64, [BulletPipeB]>;
-def : WriteRes<WriteFMinMax64, [BulletPipeB]>;
-}
-
-def : WriteRes<WriteFDiv64, [BulletPipeB, BulletFDiv]> { let Latency = 56;
-                                                         let ResourceCycles = [1, 55]; }
-def : WriteRes<WriteFSqrt64, [BulletPipeB, BulletFDiv]> { let Latency = 56;
-                                                          let ResourceCycles = [1, 55]; }
-
-// Conversions
-let Latency = 3 in {
-def : WriteRes<WriteFCvtI32ToF32, [BulletPipeB]>;
-def : WriteRes<WriteFCvtI32ToF64, [BulletPipeB]>;
-def : WriteRes<WriteFCvtI64ToF32, [BulletPipeB]>;
-def : WriteRes<WriteFCvtI64ToF64, [BulletPipeB]>;
-def : WriteRes<WriteFCvtF32ToI32, [BulletPipeB]>;
-def : WriteRes<WriteFCvtF32ToI64, [BulletPipeB]>;
-def : WriteRes<WriteFCvtF32ToF64, [BulletPipeB]>;
-def : WriteRes<WriteFCvtF64ToI32, [BulletPipeB]>;
-def : WriteRes<WriteFCvtF64ToI64, [BulletPipeB]>;
-def : WriteRes<WriteFCvtF64ToF32, [BulletPipeB]>;
-
-def : WriteRes<WriteFClass32, [BulletPipeB]>;
-def : WriteRes<WriteFClass64, [BulletPipeB]>;
-def : WriteRes<WriteFCmp32, [BulletPipeB]>;
-def : WriteRes<WriteFCmp64, [BulletPipeB]>;
-def : WriteRes<WriteFMovI32ToF32, [BulletPipeB]>;
-def : WriteRes<WriteFMovF32ToI32, [BulletPipeB]>;
-def : WriteRes<WriteFMovI64ToF64, [BulletPipeB]>;
-def : WriteRes<WriteFMovF64ToI64, [BulletPipeB]>;
-}
-
-// Others
-def : WriteRes<WriteCSR, [BulletPipeB]>;
-def : WriteRes<WriteNop, []>;
-
-def : InstRW<[WriteIALU], (instrs COPY)>;
-
-
-//===----------------------------------------------------------------------===//
-// Bypass and advance
-def : ReadAdvance<ReadJmp, 0>;
-def : ReadAdvance<ReadJalr, 0>;
-def : ReadAdvance<ReadCSR, 0>;
-def : ReadAdvance<ReadStoreData, 0>;
-def : ReadAdvance<ReadMemBase, 0>;
-def : ReadAdvance<ReadIALU, 0>;
-def : ReadAdvance<ReadIALU32, 0>;
-def : ReadAdvance<ReadShift, 0>;
-def : ReadAdvance<ReadShift32, 0>;
-def : ReadAdvance<ReadIDiv, 0>;
-def : ReadAdvance<ReadIDiv32, 0>;
-def : ReadAdvance<ReadIMul, 0>;
-def : ReadAdvance<ReadIMul32, 0>;
-def : ReadAdvance<ReadAtomicWA, 0>;
-def : ReadAdvance<ReadAtomicWD, 0>;
-def : ReadAdvance<ReadAtomicDA, 0>;
-def : ReadAdvance<ReadAtomicDD, 0>;
-def : ReadAdvance<ReadAtomicLDW, 0>;
-def : ReadAdvance<ReadAtomicLDD, 0>;
-def : ReadAdvance<ReadAtomicSTW, 0>;
-def : ReadAdvance<ReadAtomicSTD, 0>;
-def : ReadAdvance<ReadFMemBase, 0>;
-def : ReadAdvance<ReadFALU32, 0>;
-def : ReadAdvance<ReadFALU64, 0>;
-def : ReadAdvance<ReadFMul32, 0>;
-def : ReadAdvance<ReadFMulAdd32, 0>;
-def : ReadAdvance<ReadFMulSub32, 0>;
-def : ReadAdvance<ReadFMul64, 0>;
-def : ReadAdvance<ReadFMulAdd64, 0>;
-def : ReadAdvance<ReadFMulSub64, 0>;
-def : ReadAdvance<ReadFDiv32, 0>;
-def : ReadAdvance<ReadFDiv64, 0>;
-def : ReadAdvance<ReadFSqrt32, 0>;
-def : ReadAdvance<ReadFSqrt64, 0>;
-def : ReadAdvance<ReadFCmp32, 0>;
-def : ReadAdvance<ReadFCmp64, 0>;
-def : ReadAdvance<ReadFSGNJ32, 0>;
-def : ReadAdvance<ReadFSGNJ64, 0>;
-def : ReadAdvance<ReadFMinMax32, 0>;
-def : ReadAdvance<ReadFMinMax64, 0>;
-def : ReadAdvance<ReadFCvtF32ToI32, 0>;
-def : ReadAdvance<ReadFCvtF32ToI64, 0>;
-def : ReadAdvance<ReadFCvtF64ToI32, 0>;
-def : ReadAdvance<ReadFCvtF64ToI64, 0>;
-def : ReadAdvance<ReadFCvtI32ToF32, 0>;
-def : ReadAdvance<ReadFCvtI32ToF64, 0>;
-def : ReadAdvance<ReadFCvtI64ToF32, 0>;
-def : ReadAdvance<ReadFCvtI64ToF64, 0>;
-def : ReadAdvance<ReadFCvtF32ToF64, 0>;
-def : ReadAdvance<ReadFCvtF64ToF32, 0>;
-def : ReadAdvance<ReadFMovF32ToI32, 0>;
-def : ReadAdvance<ReadFMovI32ToF32, 0>;
-def : ReadAdvance<ReadFMovF64ToI64, 0>;
-def : ReadAdvance<ReadFMovI64ToF64, 0>;
-def : ReadAdvance<ReadFClass32, 0>;
-def : ReadAdvance<ReadFClass64, 0>;
-}
diff --git a/lib/Target/RISCV/RISCVSchedSiFive7.td b/lib/Target/RISCV/RISCVSchedSiFive7.td
new file mode 100644
index 00000000000..e57ba4f61b9
--- /dev/null
+++ b/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -0,0 +1,222 @@
+//==- RISCVSchedSiFive7.td - SiFive7 Scheduling Definitions --*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+
+// SiFive7 machine model for scheduling and other instruction cost heuristics.
+def SiFive7Model : SchedMachineModel {
+  let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order.
+  let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
+  let LoadLatency = 3;
+  let MispredictPenalty = 3;
+  let CompleteModel = 0;
+  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg];
+}
+
+// The SiFive7 microarchitecure has two pipelines: A and B.
+// Pipe A can handle memory, integer alu and vector operations.
+// Pipe B can handle integer alu, control flow, integer multiply and divide,
+// and floating point computation.
+let SchedModel = SiFive7Model in {
+let BufferSize = 0 in {
+def SiFive7PipeA       : ProcResource<1>;
+def SiFive7PipeB       : ProcResource<1>;
+}
+
+let BufferSize = 1 in {
+def SiFive7IDiv        : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
+def SiFive7FDiv        : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
+}
+
+def SiFive7PipeAB : ProcResGroup<[SiFive7PipeA, SiFive7PipeB]>;
+
+// Branching
+def : WriteRes<WriteJmp, [SiFive7PipeB]>;
+def : WriteRes<WriteJal, [SiFive7PipeB]>;
+def : WriteRes<WriteJalr, [SiFive7PipeB]>;
+def : WriteRes<WriteJmpReg, [SiFive7PipeB]>;
+
+// Integer arithmetic and logic
+let Latency = 3 in {
+def : WriteRes<WriteIALU, [SiFive7PipeAB]>;
+def : WriteRes<WriteIALU32, [SiFive7PipeAB]>;
+def : WriteRes<WriteShift, [SiFive7PipeAB]>;
+def : WriteRes<WriteShift32, [SiFive7PipeAB]>;
+}
+
+// Integer multiplication
+let Latency = 3 in {
+def : WriteRes<WriteIMul, [SiFive7PipeB]>;
+def : WriteRes<WriteIMul32, [SiFive7PipeB]>;
+}
+
+// Integer division
+def : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> {
+  let Latency = 16;
+  let ResourceCycles = [1, 15];
+}
+def : WriteRes<WriteIDiv32,  [SiFive7PipeB, SiFive7IDiv]> {
+  let Latency = 16;
+  let ResourceCycles = [1, 15];
+}
+
+// Memory
+def : WriteRes<WriteSTB, [SiFive7PipeA]>;
+def : WriteRes<WriteSTH, [SiFive7PipeA]>;
+def : WriteRes<WriteSTW, [SiFive7PipeA]>;
+def : WriteRes<WriteSTD, [SiFive7PipeA]>;
+def : WriteRes<WriteFST32, [SiFive7PipeA]>;
+def : WriteRes<WriteFST64, [SiFive7PipeA]>;
+
+let Latency = 3 in {
+def : WriteRes<WriteLDB, [SiFive7PipeA]>;
+def : WriteRes<WriteLDH, [SiFive7PipeA]>;
+def : WriteRes<WriteLDW, [SiFive7PipeA]>;
+def : WriteRes<WriteLDWU, [SiFive7PipeA]>;
+def : WriteRes<WriteLDD, [SiFive7PipeA]>;
+}
+
+let Latency = 2 in {
+def : WriteRes<WriteFLD32, [SiFive7PipeA]>;
+def : WriteRes<WriteFLD64, [SiFive7PipeA]>;
+}
+
+// Atomic memory
+def : WriteRes<WriteAtomicSTW, [SiFive7PipeA]>;
+def : WriteRes<WriteAtomicSTD, [SiFive7PipeA]>;
+
+let Latency = 3 in {
+def : WriteRes<WriteAtomicW, [SiFive7PipeA]>;
+def : WriteRes<WriteAtomicD, [SiFive7PipeA]>;
+def : WriteRes<WriteAtomicLDW, [SiFive7PipeA]>;
+def : WriteRes<WriteAtomicLDD, [SiFive7PipeA]>;
+}
+
+// Single precision.
+let Latency = 5 in {
+def : WriteRes<WriteFALU32, [SiFive7PipeB]>;
+def : WriteRes<WriteFMul32, [SiFive7PipeB]>;
+def : WriteRes<WriteFMulAdd32, [SiFive7PipeB]>;
+def : WriteRes<WriteFMulSub32, [SiFive7PipeB]>;
+}
+let Latency = 3 in {
+def : WriteRes<WriteFSGNJ32, [SiFive7PipeB]>;
+def : WriteRes<WriteFMinMax32, [SiFive7PipeB]>;
+}
+
+def : WriteRes<WriteFDiv32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
+                                                         let ResourceCycles = [1, 26]; }
+def : WriteRes<WriteFSqrt32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
+                                                          let ResourceCycles = [1, 26]; }
+
+// Double precision
+let Latency = 7 in {
+def : WriteRes<WriteFALU64, [SiFive7PipeB]>;
+def : WriteRes<WriteFMul64, [SiFive7PipeB]>;
+def : WriteRes<WriteFMulAdd64, [SiFive7PipeB]>;
+def : WriteRes<WriteFMulSub64, [SiFive7PipeB]>;
+}
+let Latency = 3 in {
+def : WriteRes<WriteFSGNJ64, [SiFive7PipeB]>;
+def : WriteRes<WriteFMinMax64, [SiFive7PipeB]>;
+}
+
+def : WriteRes<WriteFDiv64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
+                                                         let ResourceCycles = [1, 55]; }
+def : WriteRes<WriteFSqrt64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
+                                                          let ResourceCycles = [1, 55]; }
+
+// Conversions
+let Latency = 3 in {
+def : WriteRes<WriteFCvtI32ToF32, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtI32ToF64, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtI64ToF32, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtI64ToF64, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtF32ToI32, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtF32ToI64, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtF32ToF64, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtF64ToI32, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtF64ToI64, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtF64ToF32, [SiFive7PipeB]>;
+
+def : WriteRes<WriteFClass32, [SiFive7PipeB]>;
+def : WriteRes<WriteFClass64, [SiFive7PipeB]>;
+def : WriteRes<WriteFCmp32, [SiFive7PipeB]>;
+def : WriteRes<WriteFCmp64, [SiFive7PipeB]>;
+def : WriteRes<WriteFMovI32ToF32, [SiFive7PipeB]>;
+def : WriteRes<WriteFMovF32ToI32, [SiFive7PipeB]>;
+def : WriteRes<WriteFMovI64ToF64, [SiFive7PipeB]>;
+def : WriteRes<WriteFMovF64ToI64, [SiFive7PipeB]>;
+}
+
+// Others
+def : WriteRes<WriteCSR, [SiFive7PipeB]>;
+def : WriteRes<WriteNop, []>;
+
+def : InstRW<[WriteIALU], (instrs COPY)>;
+
+
+//===----------------------------------------------------------------------===//
+// Bypass and advance
+def : ReadAdvance<ReadJmp, 0>;
+def : ReadAdvance<ReadJalr, 0>;
+def : ReadAdvance<ReadCSR, 0>;
+def : ReadAdvance<ReadStoreData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : ReadAdvance<ReadIALU, 0>;
+def : ReadAdvance<ReadIALU32, 0>;
+def : ReadAdvance<ReadShift, 0>;
+def : ReadAdvance<ReadShift32, 0>;
+def : ReadAdvance<ReadIDiv, 0>;
+def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIMul, 0>;
+def : ReadAdvance<ReadIMul32, 0>;
+def : ReadAdvance<ReadAtomicWA, 0>;
+def : ReadAdvance<ReadAtomicWD, 0>;
+def : ReadAdvance<ReadAtomicDA, 0>;
+def : ReadAdvance<ReadAtomicDD, 0>;
+def : ReadAdvance<ReadAtomicLDW, 0>;
+def : ReadAdvance<ReadAtomicLDD, 0>;
+def : ReadAdvance<ReadAtomicSTW, 0>;
+def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFALU32, 0>;
+def : ReadAdvance<ReadFALU64, 0>;
+def : ReadAdvance<ReadFMul32, 0>;
+def : ReadAdvance<ReadFMulAdd32, 0>;
+def : ReadAdvance<ReadFMulSub32, 0>;
+def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMulAdd64, 0>;
+def : ReadAdvance<ReadFMulSub64, 0>;
+def : ReadAdvance<ReadFDiv32, 0>;
+def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt32, 0>;
+def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp32, 0>;
+def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ32, 0>;
+def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax32, 0>;
+def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFMovF32ToI32, 0>;
+def : ReadAdvance<ReadFMovI32ToF32, 0>;
+def : ReadAdvance<ReadFMovF64ToI64, 0>;
+def : ReadAdvance<ReadFMovI64ToF64, 0>;
+def : ReadAdvance<ReadFClass32, 0>;
+def : ReadAdvance<ReadFClass64, 0>;
+}