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Redo previous patch so optimization only done for i1.
Simpler and safer. llvm-svn: 44663
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@ -2455,10 +2455,6 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
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MVT::ValueType VT = N->getValueType(0);
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MVT::ValueType VT0 = N0.getValueType();
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// Some targets have SETCC types bigger than 1 bit, but do not set all the
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// bits to 1; identified by getSetCCResultContents. Watch out for these.
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// fold select C, X, X -> X
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if (N1 == N2)
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return N1;
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@ -2483,22 +2479,14 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
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return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
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}
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// fold select C, 0, X -> ~C & X
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if (VT == VT0 && N1C && N1C->isNullValue() &&
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(N0.Val->getOpcode()!=ISD::SETCC || VT==MVT::i1 ||
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TLI.getSetCCResultContents()==
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TargetLowering::ZeroOrNegativeOneSetCCResult)) {
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SDOperand XORNode;
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XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(~0UL, VT));
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if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
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SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
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AddToWorkList(XORNode.Val);
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return DAG.getNode(ISD::AND, VT, XORNode, N2);
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}
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// fold select C, X, 1 -> ~C | X
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if (VT == VT0 && N2C && N2C->getValue() == 1 &&
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(N0.Val->getOpcode()!=ISD::SETCC || VT==MVT::i1 ||
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TLI.getSetCCResultContents()==
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TargetLowering::ZeroOrNegativeOneSetCCResult)) {
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SDOperand XORNode;
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XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(~0UL, VT));
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if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getValue() == 1) {
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SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
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AddToWorkList(XORNode.Val);
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return DAG.getNode(ISD::OR, VT, XORNode, N1);
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}
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