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Lower AVX v4i64->v4i32 truncate to one shuffle.

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llvm-svn: 202996
This commit is contained in:
Cameron McInally 2014-03-05 19:41:16 +00:00
parent c4f7318790
commit 80fa2d42e5
2 changed files with 7 additions and 15 deletions
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14
lib/Target/X86/X86ISelLowering.cpp
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@ -9134,24 +9134,14 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
DAG.getIntPtrConstant(0));
}
// On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
DAG.getIntPtrConstant(0));
SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
DAG.getIntPtrConstant(2));
OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
// The PSHUFD mask:
static const int ShufMask1[] = {0, 2, 0, 0};
SDValue Undef = DAG.getUNDEF(VT);
OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
// The MOVLHPS mask:
static const int ShufMask2[] = {0, 1, 4, 5};
return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
static const int ShufMask[] = {0, 2, 4, 6};
return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
}
if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {

8
test/CodeGen/X86/avx-trunc.ll
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@ -1,13 +1,15 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
define <4 x i32> @trunc_64_32(<4 x i64> %A) nounwind uwtable readnone ssp{
; CHECK: trunc_64_32
; CHECK: pshufd
; CHECK-LABEL: trunc_64_32
; CHECK: shufps
; CHECK-NOT: pshufd
; CHECK-NOT: movlhps
%B = trunc <4 x i64> %A to <4 x i32>
ret <4 x i32>%B
}
define <8 x i16> @trunc_32_16(<8 x i32> %A) nounwind uwtable readnone ssp{
; CHECK: trunc_32_16
; CHECK-LABEL: trunc_32_16
; CHECK: pshufb
%B = trunc <8 x i32> %A to <8 x i16>
ret <8 x i16>%B