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[mips][microMIPS] Implement CodeGen support for SW16 and LW16 instructions
Differential Revision: http://reviews.llvm.org/D6581 llvm-svn: 228149
This commit is contained in:
Zoran Jovanovic
parent
a410c1a5f3
commit
8107003a7b
@ -1,4 +1,5 @@
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def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
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def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
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def simm4 : Operand<i32> {
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let DecoderMethod = "DecodeSimm4";
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@ -65,7 +66,7 @@ def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
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class mem_mm_4_generic : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, simm4);
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let MIOperandInfo = (ops GPRMM16, simm4);
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let OperandType = "OPERAND_MEMORY";
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let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
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}
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@ -879,6 +880,16 @@ def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
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def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
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(SRL_MM GPR32:$src, immZExt5:$imm)>;
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def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
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(SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
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def : MipsPat<(store GPR32:$src, addr:$addr),
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(SW_MM GPR32:$src, addr:$addr)>;
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def : MipsPat<(load addrimm4lsl2:$addr),
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(LW16_MM addrimm4lsl2:$addr)>;
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def : MipsPat<(load addr:$addr),
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(LW_MM addr:$addr)>;
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//===----------------------------------------------------------------------===//
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// MicroMips instruction aliases
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//===----------------------------------------------------------------------===//
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@ -95,6 +95,12 @@ bool MipsDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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@ -73,6 +73,9 @@ private:
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virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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/// Match addr+simm10 and addr
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virtual bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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@ -1192,11 +1192,15 @@ def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
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def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
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LW_FM<0x21>;
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def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
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LW_FM<0x23>;
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}
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def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
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def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
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}
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/// load/store left/right
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let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
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@ -1211,6 +1215,7 @@ def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
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ISA_MIPS1_NOT_32R6_64R6;
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}
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let AdditionalPredicates = [NotInMicroMips] in {
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// COP2 Memory Instructions
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def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
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ISA_MIPS1_NOT_32R6_64R6;
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@ -1230,6 +1235,7 @@ let DecoderNamespace = "COP3_" in {
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def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
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ISA_MIPS2;
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}
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}
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def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
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def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
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@ -1858,7 +1864,9 @@ def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
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let AddedComplexity = 40 in {
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def : LoadRegImmPat<LBu, i32, zextloadi8>;
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def : LoadRegImmPat<LH, i32, sextloadi16>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def : LoadRegImmPat<LW, i32, load>;
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}
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}
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//===----------------------------------------------------------------------===//
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@ -407,6 +407,31 @@ bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
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selectAddrDefault(Addr, Base, Offset);
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}
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bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
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if (dyn_cast<FrameIndexSDNode>(Base))
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return false;
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else {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset);
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if (CN) {
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unsigned CnstOff = CN->getZExtValue();
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if (CnstOff == (CnstOff & 0x3c))
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return true;
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}
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return false;
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}
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}
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// For all other cases where "lw" would be selected, don't select "lw16"
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// because it would result in additional instructions to prepare operands.
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if (selectAddrRegImm(Addr, Base, Offset))
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return false;
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return selectAddrDefault(Addr, Base, Offset);
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}
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bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (selectAddrRegImm10(Addr, Base, Offset))
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@ -65,6 +65,9 @@ private:
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bool selectIntAddrMM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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@ -124,7 +124,7 @@ end:
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; MICROMIPS: $[[BB0]]:
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; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
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; MICROMIPS: li16 $[[R2:[0-9]+]], 1
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; MICROMIPS: sw $[[R2]], 0($[[R1]])
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; MICROMIPS: sw16 $[[R2]], 0($[[R1]])
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; MICROMIPS: $[[BB2]]:
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; MICROMIPS: jr $ra
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; MICROMIPS: nop
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27
test/CodeGen/Mips/micromips-sw-lw-16.ll
Normal file
27
test/CodeGen/Mips/micromips-sw-lw-16.ll
Normal file
@ -0,0 +1,27 @@
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; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm \
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; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
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; Function Attrs: noinline nounwind
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define void @bar(i32* %p) #0 {
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entry:
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%p.addr = alloca i32*, align 4
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store i32* %p, i32** %p.addr, align 4
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%0 = load i32** %p.addr, align 4
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%1 = load i32* %0, align 4
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%add = add nsw i32 7, %1
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%2 = load i32** %p.addr, align 4
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store i32 %add, i32* %2, align 4
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%3 = load i32** %p.addr, align 4
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%add.ptr = getelementptr inbounds i32* %3, i32 1
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%4 = load i32* %add.ptr, align 4
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%add1 = add nsw i32 7, %4
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%5 = load i32** %p.addr, align 4
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%add.ptr2 = getelementptr inbounds i32* %5, i32 1
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store i32 %add1, i32* %add.ptr2, align 4
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ret void
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}
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; CHECK: lw16 ${{[0-9]+}}, 0($4)
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; CHECK: sw16 ${{[0-9]+}}, 0($4)
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; CHECK: lw16 ${{[0-9]+}}, 4(${{[0-9]+}})
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; CHECK: sw16 ${{[0-9]+}}, 4(${{[0-9]+}})
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