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InstCombine: Modernize a bunch of cast combines.
Also make them vector-aware. llvm-svn: 199608
This commit is contained in:
Benjamin Kramer
parent
319cbf6707
commit
813eb189fa
@ -858,37 +858,27 @@ Instruction *InstCombiner::visitZExt(ZExtInst &CI) {
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}
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}
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// zext(trunc(t) & C) -> (t & zext(C)).
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if (SrcI && SrcI->getOpcode() == Instruction::And && SrcI->hasOneUse())
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if (ConstantInt *C = dyn_cast<ConstantInt>(SrcI->getOperand(1)))
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if (TruncInst *TI = dyn_cast<TruncInst>(SrcI->getOperand(0))) {
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Value *TI0 = TI->getOperand(0);
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if (TI0->getType() == CI.getType())
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return
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BinaryOperator::CreateAnd(TI0,
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ConstantExpr::getZExt(C, CI.getType()));
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}
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// zext(trunc(X) & C) -> (X & zext(C)).
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Constant *C;
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Value *X;
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if (SrcI &&
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match(SrcI, m_OneUse(m_And(m_Trunc(m_Value(X)), m_Constant(C)))) &&
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X->getType() == CI.getType())
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return BinaryOperator::CreateAnd(X, ConstantExpr::getZExt(C, CI.getType()));
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// zext((trunc(t) & C) ^ C) -> ((t & zext(C)) ^ zext(C)).
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if (SrcI && SrcI->getOpcode() == Instruction::Xor && SrcI->hasOneUse())
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if (ConstantInt *C = dyn_cast<ConstantInt>(SrcI->getOperand(1)))
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if (BinaryOperator *And = dyn_cast<BinaryOperator>(SrcI->getOperand(0)))
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if (And->getOpcode() == Instruction::And && And->hasOneUse() &&
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And->getOperand(1) == C)
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if (TruncInst *TI = dyn_cast<TruncInst>(And->getOperand(0))) {
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Value *TI0 = TI->getOperand(0);
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if (TI0->getType() == CI.getType()) {
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Constant *ZC = ConstantExpr::getZExt(C, CI.getType());
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Value *NewAnd = Builder->CreateAnd(TI0, ZC);
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return BinaryOperator::CreateXor(NewAnd, ZC);
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}
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}
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// zext((trunc(X) & C) ^ C) -> ((X & zext(C)) ^ zext(C)).
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Value *And;
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if (SrcI && match(SrcI, m_OneUse(m_Xor(m_Value(And), m_Constant(C)))) &&
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match(And, m_OneUse(m_And(m_Trunc(m_Value(X)), m_Specific(C)))) &&
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X->getType() == CI.getType()) {
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Constant *ZC = ConstantExpr::getZExt(C, CI.getType());
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return BinaryOperator::CreateXor(Builder->CreateAnd(X, ZC), ZC);
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}
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// zext (xor i1 X, true) to i32 --> xor (zext i1 X to i32), 1
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Value *X;
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if (SrcI && SrcI->hasOneUse() && SrcI->getType()->isIntegerTy(1) &&
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match(SrcI, m_Not(m_Value(X))) &&
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(!X->hasOneUse() || !isa<CmpInst>(X))) {
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if (SrcI && SrcI->hasOneUse() &&
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SrcI->getType()->getScalarType()->isIntegerTy(1) &&
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match(SrcI, m_Not(m_Value(X))) && (!X->hasOneUse() || !isa<CmpInst>(X))) {
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Value *New = Builder->CreateZExt(X, CI.getType());
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return BinaryOperator::CreateXor(New, ConstantInt::get(CI.getType(), 1));
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}
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@ -902,10 +892,10 @@ Instruction *InstCombiner::transformSExtICmp(ICmpInst *ICI, Instruction &CI) {
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Value *Op0 = ICI->getOperand(0), *Op1 = ICI->getOperand(1);
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ICmpInst::Predicate Pred = ICI->getPredicate();
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if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
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if (Constant *Op1C = dyn_cast<Constant>(Op1)) {
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// (x <s 0) ? -1 : 0 -> ashr x, 31 -> all ones if negative
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// (x >s -1) ? -1 : 0 -> not (ashr x, 31) -> all ones if positive
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if ((Pred == ICmpInst::ICMP_SLT && Op1C->isZero()) ||
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if ((Pred == ICmpInst::ICMP_SLT && Op1C->isNullValue()) ||
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(Pred == ICmpInst::ICMP_SGT && Op1C->isAllOnesValue())) {
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Value *Sh = ConstantInt::get(Op0->getType(),
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@ -918,7 +908,9 @@ Instruction *InstCombiner::transformSExtICmp(ICmpInst *ICI, Instruction &CI) {
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In = Builder->CreateNot(In, In->getName()+".not");
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return ReplaceInstUsesWith(CI, In);
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}
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}
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if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
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// If we know that only one bit of the LHS of the icmp can be set and we
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// have an equality comparison with zero or a power of 2, we can transform
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// the icmp and sext into bitwise/integer operations.
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@ -975,19 +967,6 @@ Instruction *InstCombiner::transformSExtICmp(ICmpInst *ICI, Instruction &CI) {
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}
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}
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// vector (x <s 0) ? -1 : 0 -> ashr x, 31 -> all ones if signed.
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if (VectorType *VTy = dyn_cast<VectorType>(CI.getType())) {
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if (Pred == ICmpInst::ICMP_SLT && match(Op1, m_Zero()) &&
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Op0->getType() == CI.getType()) {
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Type *EltTy = VTy->getElementType();
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// splat the shift constant to a constant vector.
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Constant *VSh = ConstantInt::get(VTy, EltTy->getScalarSizeInBits()-1);
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Value *In = Builder->CreateAShr(Op0, VSh, Op0->getName()+".lobit");
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return ReplaceInstUsesWith(CI, In);
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}
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}
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return 0;
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}
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@ -13,6 +13,7 @@ entry:
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%cond = or <4 x i32> %2, %3
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ret <4 x i32> %cond
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; CHECK-LABEL: @psignd_3
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; CHECK: ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
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; CHECK: sub nsw <4 x i32> zeroinitializer, %a
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; CHECK: xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
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@ -20,3 +21,25 @@ entry:
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; CHECK: and <4 x i32> %b.lobit, %sub
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; CHECK: or <4 x i32> %1, %2
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}
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define <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b) nounwind ssp {
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entry:
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%cmp = icmp sgt <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%sub = sub nsw <4 x i32> zeroinitializer, %a
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%0 = icmp slt <4 x i32> %sext, zeroinitializer
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%sext3 = sext <4 x i1> %0 to <4 x i32>
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%1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
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%2 = and <4 x i32> %a, %1
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%3 = and <4 x i32> %sext3, %sub
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%cond = or <4 x i32> %2, %3
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ret <4 x i32> %cond
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; CHECK-LABEL: @test1
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; CHECK: ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
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; CHECK: xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
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; CHECK: sub nsw <4 x i32> zeroinitializer, %a
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; CHECK: and <4 x i32> %b.lobit, %a
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; CHECK: and <4 x i32> %b.lobit.not, %sub
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; CHECK: or <4 x i32> %0, %1
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}
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@ -5,7 +5,41 @@ define i64 @test_sext_zext(i16 %A) {
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%c1 = zext i16 %A to i32 ; <i32> [#uses=1]
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%c2 = sext i32 %c1 to i64 ; <i64> [#uses=1]
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ret i64 %c2
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; CHECK-LABEL: @test_sext_zext
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; CHECK-NOT: %c1
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; CHECK: %c2 = zext i16 %A to i64
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; CHECK: ret i64 %c2
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}
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define <2 x i64> @test2(<2 x i1> %A) {
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%xor = xor <2 x i1> %A, <i1 true, i1 true>
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%zext = zext <2 x i1> %xor to <2 x i64>
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ret <2 x i64> %zext
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; CHECK-LABEL: @test2
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; CHECK-NEXT: zext <2 x i1> %A to <2 x i64>
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; CHECK-NEXT: xor <2 x i64> %1, <i64 1, i64 1>
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}
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define <2 x i64> @test3(<2 x i64> %A) {
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%trunc = trunc <2 x i64> %A to <2 x i32>
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%and = and <2 x i32> %trunc, <i32 23, i32 42>
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%zext = zext <2 x i32> %and to <2 x i64>
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ret <2 x i64> %zext
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; CHECK-LABEL: @test3
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; CHECK-NEXT: and <2 x i64> %A, <i64 23, i64 42>
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}
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define <2 x i64> @test4(<2 x i64> %A) {
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%trunc = trunc <2 x i64> %A to <2 x i32>
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%and = and <2 x i32> %trunc, <i32 23, i32 42>
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%xor = xor <2 x i32> %and, <i32 23, i32 42>
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%zext = zext <2 x i32> %xor to <2 x i64>
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ret <2 x i64> %zext
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; CHECK-LABEL: @test4
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; CHECK-NEXT: xor <2 x i64> %A, <i64 4294967295, i64 4294967295>
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; CHECK-NEXT: and <2 x i64> %1, <i64 23, i64 42>
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}
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