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[InstCombine] add tests for PR35792; NFC
llvm-svn: 323436
This commit is contained in:
Sanjay Patel
parent
112b81231e
commit
813ee2220b
192
test/Transforms/InstCombine/and-narrow.ll
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192
test/Transforms/InstCombine/and-narrow.ll
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -data-layout="n8:16:32" -S | FileCheck %s --check-prefix=ALL --check-prefix=LEGAL8
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; RUN: opt < %s -instcombine -data-layout="n16" -S | FileCheck %s --check-prefix=ALL --check-prefix=LEGAL16
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; PR35792 - https://bugs.llvm.org/show_bug.cgi?id=35792
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define i16 @zext_add(i8 %x) {
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; ALL-LABEL: @zext_add(
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; ALL-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i16
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; ALL-NEXT: [[B:%.*]] = add nuw nsw i16 [[Z]], 44
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; ALL-NEXT: [[R:%.*]] = and i16 [[B]], [[Z]]
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; ALL-NEXT: ret i16 [[R]]
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;
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%z = zext i8 %x to i16
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%b = add i16 %z, 44
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%r = and i16 %b, %z
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ret i16 %r
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}
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define i16 @zext_sub(i8 %x) {
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; ALL-LABEL: @zext_sub(
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; ALL-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i16
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; ALL-NEXT: [[B:%.*]] = sub nsw i16 251, [[Z]]
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; ALL-NEXT: [[R:%.*]] = and i16 [[B]], [[Z]]
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; ALL-NEXT: ret i16 [[R]]
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;
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%z = zext i8 %x to i16
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%b = sub i16 -5, %z
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%r = and i16 %b, %z
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ret i16 %r
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}
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define i16 @zext_mul(i8 %x) {
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; ALL-LABEL: @zext_mul(
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; ALL-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i16
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; ALL-NEXT: [[B:%.*]] = mul nuw nsw i16 [[Z]], 3
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; ALL-NEXT: [[R:%.*]] = and i16 [[B]], [[Z]]
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; ALL-NEXT: ret i16 [[R]]
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;
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%z = zext i8 %x to i16
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%b = mul i16 %z, 3
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%r = and i16 %b, %z
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ret i16 %r
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}
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define i16 @zext_lshr(i8 %x) {
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; ALL-LABEL: @zext_lshr(
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; ALL-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i16
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; ALL-NEXT: [[B:%.*]] = lshr i16 [[Z]], 4
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; ALL-NEXT: [[R:%.*]] = and i16 [[B]], [[Z]]
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; ALL-NEXT: ret i16 [[R]]
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;
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%z = zext i8 %x to i16
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%b = lshr i16 %z, 4
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%r = and i16 %b, %z
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ret i16 %r
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}
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define i16 @zext_ashr(i8 %x) {
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; ALL-LABEL: @zext_ashr(
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; ALL-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i16
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; ALL-NEXT: [[TMP1:%.*]] = lshr i16 [[Z]], 2
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; ALL-NEXT: [[R:%.*]] = and i16 [[TMP1]], [[Z]]
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; ALL-NEXT: ret i16 [[R]]
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;
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%z = zext i8 %x to i16
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%b = ashr i16 %z, 2
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%r = and i16 %b, %z
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ret i16 %r
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}
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define i16 @zext_shl(i8 %x) {
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; ALL-LABEL: @zext_shl(
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; ALL-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i16
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; ALL-NEXT: [[B:%.*]] = shl nuw nsw i16 [[Z]], 3
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; ALL-NEXT: [[R:%.*]] = and i16 [[B]], [[Z]]
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; ALL-NEXT: ret i16 [[R]]
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;
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%z = zext i8 %x to i16
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%b = shl i16 %z, 3
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%r = and i16 %b, %z
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ret i16 %r
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}
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define <2 x i16> @zext_add_vec(<2 x i8> %x) {
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; ALL-LABEL: @zext_add_vec(
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; ALL-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
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; ALL-NEXT: [[B:%.*]] = add nuw nsw <2 x i16> [[Z]], <i16 44, i16 42>
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; ALL-NEXT: [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
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; ALL-NEXT: ret <2 x i16> [[R]]
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;
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%z = zext <2 x i8> %x to <2 x i16>
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%b = add <2 x i16> %z, <i16 44, i16 42>
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%r = and <2 x i16> %b, %z
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ret <2 x i16> %r
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}
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define <2 x i16> @zext_sub_vec(<2 x i8> %x) {
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; ALL-LABEL: @zext_sub_vec(
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; ALL-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
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; ALL-NEXT: [[B:%.*]] = sub nuw nsw <2 x i16> <i16 -5, i16 -4>, [[Z]]
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; ALL-NEXT: [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
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; ALL-NEXT: ret <2 x i16> [[R]]
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;
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%z = zext <2 x i8> %x to <2 x i16>
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%b = sub <2 x i16> <i16 -5, i16 -4>, %z
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%r = and <2 x i16> %b, %z
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ret <2 x i16> %r
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}
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define <2 x i16> @zext_mul_vec(<2 x i8> %x) {
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; ALL-LABEL: @zext_mul_vec(
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; ALL-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
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; ALL-NEXT: [[B:%.*]] = mul nsw <2 x i16> [[Z]], <i16 3, i16 -2>
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; ALL-NEXT: [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
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; ALL-NEXT: ret <2 x i16> [[R]]
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;
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%z = zext <2 x i8> %x to <2 x i16>
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%b = mul <2 x i16> %z, <i16 3, i16 -2>
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%r = and <2 x i16> %b, %z
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ret <2 x i16> %r
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}
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define <2 x i16> @zext_lshr_vec(<2 x i8> %x) {
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; ALL-LABEL: @zext_lshr_vec(
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; ALL-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
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; ALL-NEXT: [[B:%.*]] = lshr <2 x i16> [[Z]], <i16 4, i16 2>
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; ALL-NEXT: [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
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; ALL-NEXT: ret <2 x i16> [[R]]
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;
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%z = zext <2 x i8> %x to <2 x i16>
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%b = lshr <2 x i16> %z, <i16 4, i16 2>
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%r = and <2 x i16> %b, %z
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ret <2 x i16> %r
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}
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define <2 x i16> @zext_ashr_vec(<2 x i8> %x) {
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; ALL-LABEL: @zext_ashr_vec(
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; ALL-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
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; ALL-NEXT: [[B:%.*]] = lshr <2 x i16> [[Z]], <i16 2, i16 3>
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; ALL-NEXT: [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
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; ALL-NEXT: ret <2 x i16> [[R]]
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;
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%z = zext <2 x i8> %x to <2 x i16>
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%b = ashr <2 x i16> %z, <i16 2, i16 3>
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%r = and <2 x i16> %b, %z
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ret <2 x i16> %r
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}
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define <2 x i16> @zext_shl_vec(<2 x i8> %x) {
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; ALL-LABEL: @zext_shl_vec(
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; ALL-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
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; ALL-NEXT: [[B:%.*]] = shl <2 x i16> [[Z]], <i16 3, i16 2>
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; ALL-NEXT: [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
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; ALL-NEXT: ret <2 x i16> [[R]]
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;
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%z = zext <2 x i8> %x to <2 x i16>
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%b = shl <2 x i16> %z, <i16 3, i16 2>
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%r = and <2 x i16> %b, %z
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ret <2 x i16> %r
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}
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; Don't create poison by narrowing a shift below the shift amount.
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define <2 x i16> @zext_lshr_vec_overshift(<2 x i8> %x) {
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; ALL-LABEL: @zext_lshr_vec_overshift(
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; ALL-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
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; ALL-NEXT: [[B:%.*]] = lshr <2 x i16> [[Z]], <i16 4, i16 8>
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; ALL-NEXT: [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
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; ALL-NEXT: ret <2 x i16> [[R]]
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;
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%z = zext <2 x i8> %x to <2 x i16>
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%b = lshr <2 x i16> %z, <i16 4, i16 8>
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%r = and <2 x i16> %b, %z
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ret <2 x i16> %r
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}
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; Don't create poison by narrowing a shift below the shift amount.
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define <2 x i16> @zext_shl_vec_overshift(<2 x i8> %x) {
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; ALL-LABEL: @zext_shl_vec_overshift(
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; ALL-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
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; ALL-NEXT: [[B:%.*]] = shl <2 x i16> [[Z]], <i16 8, i16 2>
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; ALL-NEXT: [[R:%.*]] = and <2 x i16> [[B]], [[Z]]
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; ALL-NEXT: ret <2 x i16> [[R]]
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;
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%z = zext <2 x i8> %x to <2 x i16>
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%b = shl <2 x i16> %z, <i16 8, i16 2>
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%r = and <2 x i16> %b, %z
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ret <2 x i16> %r
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}
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