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ARM assembly parsing and encoding for VLD2 single-element, double spaced.
llvm-svn: 146983
This commit is contained in:
Jim Grosbach
parent
46b085721a
commit
8156a5dcee
@ -174,7 +174,7 @@ def VecListOneDWordIndexed : Operand<i32> {
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let ParserMatchClass = VecListOneDWordIndexAsmOperand;
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let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
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}
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// Register list of two D registers, with byte lane subscripting.
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// Register list of two D registers with byte lane subscripting.
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def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
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let Name = "VecListTwoDByteIndexed";
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let ParserMethod = "parseVectorList";
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@ -204,6 +204,26 @@ def VecListTwoDWordIndexed : Operand<i32> {
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let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
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let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
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}
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// Register list of two Q registers with half-word lane subscripting.
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def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
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let Name = "VecListTwoQHWordIndexed";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListIndexedOperands";
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}
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def VecListTwoQHWordIndexed : Operand<i32> {
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let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
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let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
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}
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// ...with word lane subscripting.
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def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
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let Name = "VecListTwoQWordIndexed";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListIndexedOperands";
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}
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def VecListTwoQWordIndexed : Operand<i32> {
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let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
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let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
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}
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//===----------------------------------------------------------------------===//
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// NEON-specific DAG Nodes.
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@ -5735,6 +5755,10 @@ defm VLD2LNdAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr",
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(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNdAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr",
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(ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNqAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr",
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(ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNqAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr",
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(ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr!",
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(ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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@ -5742,6 +5766,10 @@ defm VLD2LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!",
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(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!",
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(ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!",
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(ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!",
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(ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNdWB_register_Asm :
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NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
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(ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
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@ -5754,6 +5782,14 @@ defm VLD2LNdWB_register_Asm :
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NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
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(ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VLD2LNqWB_register_Asm :
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NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
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(ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VLD2LNqWB_register_Asm :
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NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
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(ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VST2 single-lane pseudo-instructions. These need special handling for
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@ -1128,33 +1128,49 @@ public:
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return VectorList.Count == 2;
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}
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bool isSingleSpacedVectorIndexed() const {
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return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
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}
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bool isDoubleSpacedVectorIndexed() const {
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return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
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}
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bool isVecListOneDByteIndexed() const {
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if (Kind != k_VectorListIndexed) return false;
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if (!isSingleSpacedVectorIndexed()) return false;
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return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
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}
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bool isVecListOneDHWordIndexed() const {
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if (Kind != k_VectorListIndexed) return false;
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if (!isSingleSpacedVectorIndexed()) return false;
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return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
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}
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bool isVecListOneDWordIndexed() const {
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if (Kind != k_VectorListIndexed) return false;
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if (!isSingleSpacedVectorIndexed()) return false;
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return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
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}
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bool isVecListTwoDByteIndexed() const {
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if (Kind != k_VectorListIndexed) return false;
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if (!isSingleSpacedVectorIndexed()) return false;
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return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
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}
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bool isVecListTwoDHWordIndexed() const {
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if (Kind != k_VectorListIndexed) return false;
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if (!isSingleSpacedVectorIndexed()) return false;
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return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
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}
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bool isVecListTwoQWordIndexed() const {
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if (!isDoubleSpacedVectorIndexed()) return false;
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return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
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}
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bool isVecListTwoQHWordIndexed() const {
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if (!isDoubleSpacedVectorIndexed()) return false;
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return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
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}
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bool isVecListTwoDWordIndexed() const {
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if (Kind != k_VectorListIndexed) return false;
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if (!isSingleSpacedVectorIndexed()) return false;
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return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
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}
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@ -2035,11 +2051,14 @@ public:
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}
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static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
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unsigned Index, SMLoc S, SMLoc E) {
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unsigned Index,
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bool isDoubleSpaced,
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SMLoc S, SMLoc E) {
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ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
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Op->VectorList.RegNum = RegNum;
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Op->VectorList.Count = Count;
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Op->VectorList.LaneIndex = Index;
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Op->VectorList.isDoubleSpaced = isDoubleSpaced;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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@ -2849,7 +2868,8 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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break;
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case IndexedLane:
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Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
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LaneIndex, S,E));
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LaneIndex,
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false, S, E));
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break;
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}
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return MatchOperand_Success;
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@ -2872,7 +2892,8 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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break;
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case IndexedLane:
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Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
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LaneIndex, S,E));
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LaneIndex,
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false, S, E));
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break;
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}
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return MatchOperand_Success;
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@ -3020,11 +3041,6 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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Error(EndLoc, "mismatched lane index in register list");
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return MatchOperand_ParseFail;
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}
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if (Spacing == 2 && LaneKind != NoLanes) {
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Error(EndLoc,
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"lane index specfier invalid in double spaced register list");
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return MatchOperand_ParseFail;
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}
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}
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SMLoc E = Parser.getTok().getLoc();
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@ -3047,7 +3063,9 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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break;
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case IndexedLane:
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Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
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LaneIndex, S, E));
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LaneIndex,
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(Spacing == 2),
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S, E));
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break;
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}
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return MatchOperand_Success;
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@ -5181,84 +5199,132 @@ static unsigned getRealVSTLNOpcode(unsigned Opc) {
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}
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}
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static unsigned getRealVLDLNOpcode(unsigned Opc) {
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static unsigned getRealVLDLNOpcode(unsigned Opc, unsigned &Spacing) {
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switch(Opc) {
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default: assert(0 && "unexpected opcode!");
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// VLD1LN
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case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8:
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case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8:
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case ARM::VLD1LNdWB_fixed_Asm_U8:
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Spacing = 1;
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return ARM::VLD1LNd8_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_16: case ARM::VLD1LNdWB_fixed_Asm_P16:
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case ARM::VLD1LNdWB_fixed_Asm_I16: case ARM::VLD1LNdWB_fixed_Asm_S16:
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case ARM::VLD1LNdWB_fixed_Asm_U16:
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Spacing = 1;
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return ARM::VLD1LNd16_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F:
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case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32:
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case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32:
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Spacing = 1;
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return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8:
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case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8:
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case ARM::VLD1LNdWB_register_Asm_U8:
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Spacing = 1;
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return ARM::VLD1LNd8_UPD;
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case ARM::VLD1LNdWB_register_Asm_16: case ARM::VLD1LNdWB_register_Asm_P16:
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case ARM::VLD1LNdWB_register_Asm_I16: case ARM::VLD1LNdWB_register_Asm_S16:
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case ARM::VLD1LNdWB_register_Asm_U16:
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Spacing = 1;
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return ARM::VLD1LNd16_UPD;
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case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F:
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case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32:
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case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32:
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Spacing = 1;
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return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8:
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case ARM::VLD1LNdAsm_I8: case ARM::VLD1LNdAsm_S8:
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case ARM::VLD1LNdAsm_U8:
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Spacing = 1;
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return ARM::VLD1LNd8;
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case ARM::VLD1LNdAsm_16: case ARM::VLD1LNdAsm_P16:
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case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16:
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case ARM::VLD1LNdAsm_U16:
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Spacing = 1;
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return ARM::VLD1LNd16;
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case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F:
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case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32:
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case ARM::VLD1LNdAsm_S32: case ARM::VLD1LNdAsm_U32:
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Spacing = 1;
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return ARM::VLD1LNd32;
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// VLD2LN
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case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8:
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case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8:
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case ARM::VLD2LNdWB_fixed_Asm_U8:
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Spacing = 1;
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return ARM::VLD2LNd8_UPD;
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case ARM::VLD2LNdWB_fixed_Asm_16: case ARM::VLD2LNdWB_fixed_Asm_P16:
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case ARM::VLD2LNdWB_fixed_Asm_I16: case ARM::VLD2LNdWB_fixed_Asm_S16:
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case ARM::VLD2LNdWB_fixed_Asm_U16:
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Spacing = 1;
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return ARM::VLD2LNd16_UPD;
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case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
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case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32:
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case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32:
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Spacing = 1;
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return ARM::VLD2LNd32_UPD;
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case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16:
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case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16:
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case ARM::VLD2LNqWB_fixed_Asm_U16:
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Spacing = 1;
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return ARM::VLD2LNq16_UPD;
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case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F:
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case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32:
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case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32:
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Spacing = 2;
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return ARM::VLD2LNq32_UPD;
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case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8:
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case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8:
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case ARM::VLD2LNdWB_register_Asm_U8:
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Spacing = 1;
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return ARM::VLD2LNd8_UPD;
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case ARM::VLD2LNdWB_register_Asm_16: case ARM::VLD2LNdWB_register_Asm_P16:
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case ARM::VLD2LNdWB_register_Asm_I16: case ARM::VLD2LNdWB_register_Asm_S16:
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case ARM::VLD2LNdWB_register_Asm_U16:
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Spacing = 1;
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return ARM::VLD2LNd16_UPD;
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case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
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case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32:
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case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32:
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Spacing = 1;
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return ARM::VLD2LNd32_UPD;
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case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16:
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case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16:
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case ARM::VLD2LNqWB_register_Asm_U16:
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Spacing = 2;
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return ARM::VLD2LNq16_UPD;
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case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F:
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case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32:
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case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32:
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Spacing = 2;
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return ARM::VLD2LNq32_UPD;
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case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8:
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case ARM::VLD2LNdAsm_I8: case ARM::VLD2LNdAsm_S8:
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case ARM::VLD2LNdAsm_U8:
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Spacing = 1;
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return ARM::VLD2LNd8;
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case ARM::VLD2LNdAsm_16: case ARM::VLD2LNdAsm_P16:
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case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16:
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case ARM::VLD2LNdAsm_U16:
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Spacing = 1;
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return ARM::VLD2LNd16;
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case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F:
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case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32:
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case ARM::VLD2LNdAsm_S32: case ARM::VLD2LNdAsm_U32:
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Spacing = 1;
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return ARM::VLD2LNd32;
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case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16:
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case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16:
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case ARM::VLD2LNqAsm_U16:
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Spacing = 2;
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return ARM::VLD2LNq16;
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case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F:
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case ARM::VLD2LNqAsm_F32: case ARM::VLD2LNqAsm_I32:
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case ARM::VLD2LNqAsm_S32: case ARM::VLD2LNqAsm_U32:
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Spacing = 2;
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return ARM::VLD2LNq32;
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}
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}
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@ -5415,7 +5481,8 @@ processInstruction(MCInst &Inst,
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
|
||||
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
|
||||
TmpInst.addOperand(Inst.getOperand(2)); // Rn
|
||||
@ -5429,26 +5496,34 @@ processInstruction(MCInst &Inst,
|
||||
return true;
|
||||
}
|
||||
|
||||
case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8:
|
||||
case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8:
|
||||
case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16:
|
||||
case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8:
|
||||
case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8:
|
||||
case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16:
|
||||
case ARM::VLD2LNdWB_register_Asm_P16: case ARM::VLD2LNdWB_register_Asm_I16:
|
||||
case ARM::VLD2LNdWB_register_Asm_S16: case ARM::VLD2LNdWB_register_Asm_U16:
|
||||
case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
|
||||
case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
|
||||
case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32:
|
||||
case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: {
|
||||
case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32:
|
||||
case ARM::VLD2LNqWB_register_Asm_P16: case ARM::VLD2LNqWB_register_Asm_I16:
|
||||
case ARM::VLD2LNqWB_register_Asm_S16: case ARM::VLD2LNqWB_register_Asm_U16:
|
||||
case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F:
|
||||
case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32:
|
||||
case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
|
||||
unsigned Spacing;
|
||||
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(0)); // Vd
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
|
||||
Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
|
||||
TmpInst.addOperand(Inst.getOperand(2)); // Rn
|
||||
TmpInst.addOperand(Inst.getOperand(3)); // alignment
|
||||
TmpInst.addOperand(Inst.getOperand(4)); // Rm
|
||||
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
|
||||
Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(1)); // lane
|
||||
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
|
||||
TmpInst.addOperand(Inst.getOperand(6));
|
||||
@ -5467,7 +5542,8 @@ processInstruction(MCInst &Inst,
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
|
||||
unsigned Spacing;
|
||||
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(0)); // Vd
|
||||
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
|
||||
TmpInst.addOperand(Inst.getOperand(2)); // Rn
|
||||
@ -5481,26 +5557,34 @@ processInstruction(MCInst &Inst,
|
||||
return true;
|
||||
}
|
||||
|
||||
case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_P16: case ARM::VLD2LNdWB_fixed_Asm_I16:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_S16: case ARM::VLD2LNdWB_fixed_Asm_U16:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: {
|
||||
case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_P16: case ARM::VLD2LNqWB_fixed_Asm_I16:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_S16: case ARM::VLD2LNqWB_fixed_Asm_U16:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
|
||||
unsigned Spacing;
|
||||
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(0)); // Vd
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
|
||||
Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
|
||||
TmpInst.addOperand(Inst.getOperand(2)); // Rn
|
||||
TmpInst.addOperand(Inst.getOperand(3)); // alignment
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
|
||||
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
|
||||
Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(1)); // lane
|
||||
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
|
||||
TmpInst.addOperand(Inst.getOperand(5));
|
||||
@ -5517,7 +5601,8 @@ processInstruction(MCInst &Inst,
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
|
||||
unsigned Spacing;
|
||||
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(0)); // Vd
|
||||
TmpInst.addOperand(Inst.getOperand(2)); // Rn
|
||||
TmpInst.addOperand(Inst.getOperand(3)); // alignment
|
||||
@ -5529,22 +5614,29 @@ processInstruction(MCInst &Inst,
|
||||
return true;
|
||||
}
|
||||
|
||||
case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8:
|
||||
case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16:
|
||||
case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8:
|
||||
case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16:
|
||||
case ARM::VLD2LNdAsm_P16: case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16:
|
||||
case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F:
|
||||
case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F:
|
||||
case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: case ARM::VLD2LNdAsm_S32:
|
||||
case ARM::VLD2LNdAsm_U32: {
|
||||
case ARM::VLD2LNdAsm_U32: case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16:
|
||||
case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: case ARM::VLD2LNqAsm_U16:
|
||||
case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: case ARM::VLD2LNqAsm_F32:
|
||||
case ARM::VLD2LNqAsm_I32: case ARM::VLD2LNqAsm_S32:
|
||||
case ARM::VLD2LNqAsm_U32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
|
||||
unsigned Spacing;
|
||||
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(0)); // Vd
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
|
||||
Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(2)); // Rn
|
||||
TmpInst.addOperand(Inst.getOperand(3)); // alignment
|
||||
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
|
||||
Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(1)); // lane
|
||||
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
|
||||
TmpInst.addOperand(Inst.getOperand(5));
|
||||
|
||||
@ -230,8 +230,9 @@
|
||||
vld2.8 {d16[1], d17[1]}, [r0, :16]
|
||||
vld2.16 {d16[1], d17[1]}, [r0, :32]
|
||||
vld2.32 {d16[1], d17[1]}, [r0]
|
||||
@ vld2.16 {d17[1], d19[1]}, [r0]
|
||||
@ vld2.32 {d17[0], d19[0]}, [r0, :64]
|
||||
vld2.16 {d17[1], d19[1]}, [r0]
|
||||
vld2.32 {d17[0], d19[0]}, [r0, :64]
|
||||
vld2.32 {d17[0], d19[0]}, [r0, :64]!
|
||||
vld2.8 {d2[4], d3[4]}, [r2], r3
|
||||
vld2.8 {d2[4], d3[4]}, [r2]!
|
||||
vld2.8 {d2[4], d3[4]}, [r2]
|
||||
@ -239,8 +240,9 @@
|
||||
@ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4]
|
||||
@ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4]
|
||||
@ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf4]
|
||||
@ FIXME: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4]
|
||||
@ FIXME: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4]
|
||||
@ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4]
|
||||
@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4]
|
||||
@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64]! @ encoding: [0x5d,0x19,0xe0,0xf4]
|
||||
@ CHECK: vld2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0xa2,0xf4]
|
||||
@ CHECK: vld2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0xa2,0xf4]
|
||||
@ CHECK: vld2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0xa2,0xf4]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user