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Fix SPARC backend call instruction so that arguments passed through registers
are correctly marked as used instead of passing all possible argument registers as used. llvm-svn: 123301
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@ -1,3 +1,4 @@
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//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
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//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
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//
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//
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// The LLVM Compiler Infrastructure
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// The LLVM Compiler Infrastructure
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@ -514,11 +515,22 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
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else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
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std::vector<EVT> NodeTys;
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// Returns a chain & a flag for retval copy to use
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NodeTys.push_back(MVT::Other); // Returns a chain
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
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SmallVector<SDValue, 8> Ops;
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SDValue Ops[] = { Chain, Callee, InFlag };
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Ops.push_back(Chain);
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Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
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Ops.push_back(Callee);
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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unsigned Reg = RegsToPass[i].first;
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if (Reg >= SP::I0 && Reg <= SP::I7)
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Reg = Reg-SP::I0+SP::O0;
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Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType()));
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}
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if (InFlag.getNode())
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Ops.push_back(InFlag);
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Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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InFlag = Chain.getValue(1);
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Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
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Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
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@ -119,9 +119,10 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
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def call : SDNode<"SPISD::CALL", SDT_SPCall,
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def call : SDNode<"SPISD::CALL", SDT_SPCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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def retflag : SDNode<"SPISD::RET_FLAG", SDTNone,
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def retflag : SDNode<"SPISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue]>;
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[SDNPHasChain, SDNPOptInGlue]>;
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@ -517,11 +518,11 @@ let Uses = [FCC] in
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// Section B.24 - Call and Link Instruction, p. 125
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// Section B.24 - Call and Link Instruction, p. 125
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// This is the only Format 1 instruction
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// This is the only Format 1 instruction
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let Uses = [O0, O1, O2, O3, O4, O5],
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let Uses = [O6],
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hasDelaySlot = 1, isCall = 1,
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hasDelaySlot = 1, isCall = 1,
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Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
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Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
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D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
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D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
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def CALL : InstSP<(outs), (ins calltarget:$dst),
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def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
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"call $dst", []> {
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"call $dst", []> {
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bits<30> disp;
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bits<30> disp;
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let op = 1;
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let op = 1;
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@ -530,11 +531,11 @@ let Uses = [O0, O1, O2, O3, O4, O5],
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// indirect calls
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// indirect calls
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def JMPLrr : F3_1<2, 0b111000,
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def JMPLrr : F3_1<2, 0b111000,
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(outs), (ins MEMrr:$ptr),
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(outs), (ins MEMrr:$ptr, variable_ops),
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"call $ptr",
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"call $ptr",
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[(call ADDRrr:$ptr)]>;
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[(call ADDRrr:$ptr)]>;
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def JMPLri : F3_2<2, 0b111000,
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def JMPLri : F3_2<2, 0b111000,
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(outs), (ins MEMri:$ptr),
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(outs), (ins MEMri:$ptr, variable_ops),
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"call $ptr",
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"call $ptr",
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[(call ADDRri:$ptr)]>;
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[(call ADDRri:$ptr)]>;
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}
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}
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13
test/CodeGen/SPARC/2011-01-11-Call.ll
Normal file
13
test/CodeGen/SPARC/2011-01-11-Call.ll
Normal file
@ -0,0 +1,13 @@
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; RUN: llc -march=sparc -O0 <%s
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define void @test() nounwind {
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entry:
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%0 = tail call i32 (...)* @foo() nounwind
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tail call void (...)* @bar() nounwind
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ret void
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}
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declare i32 @foo(...)
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declare void @bar(...)
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