mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 04:02:41 +01:00
[MIPS GlobalISel] Lower float and double arguments in registers
Lower float and double arguments in registers for MIPS32. When float/double argument is passed through gpr registers select appropriate move instruction. Differential Revision: https://reviews.llvm.org/D59642 llvm-svn: 356882
This commit is contained in:
Petar Avramovic
parent
dfaaae5904
commit
818c1c89bd
@ -23,10 +23,10 @@ using namespace llvm;
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MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI)
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: CallLowering(&TLI) {}
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bool MipsCallLowering::MipsHandler::assign(unsigned VReg,
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const CCValAssign &VA) {
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bool MipsCallLowering::MipsHandler::assign(unsigned VReg, const CCValAssign &VA,
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const EVT &VT) {
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if (VA.isRegLoc()) {
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assignValueToReg(VReg, VA);
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assignValueToReg(VReg, VA, VT);
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} else if (VA.isMemLoc()) {
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assignValueToAddress(VReg, VA);
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} else {
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@ -37,9 +37,10 @@ bool MipsCallLowering::MipsHandler::assign(unsigned VReg,
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bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<unsigned> VRegs,
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ArrayRef<CCValAssign> ArgLocs,
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unsigned ArgLocsStartIndex) {
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unsigned ArgLocsStartIndex,
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const EVT &VT) {
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for (unsigned i = 0; i < VRegs.size(); ++i)
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if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i]))
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if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT))
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return false;
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return true;
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}
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@ -71,10 +72,10 @@ bool MipsCallLowering::MipsHandler::handle(
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for (unsigned i = 0; i < SplitLength; ++i)
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VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT}));
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if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Reg))
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if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Reg, VT))
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return false;
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} else {
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if (!assign(Args[ArgsIndex].Reg, ArgLocs[ArgLocsIndex]))
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if (!assign(Args[ArgsIndex].Reg, ArgLocs[ArgLocsIndex], VT))
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return false;
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}
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}
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@ -88,7 +89,8 @@ public:
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: MipsHandler(MIRBuilder, MRI) {}
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private:
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void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) override;
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void assignValueToReg(unsigned ValVReg, const CCValAssign &VA,
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const EVT &VT) override;
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unsigned getStackAddress(const CCValAssign &VA,
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MachineMemOperand *&MMO) override;
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@ -97,7 +99,7 @@ private:
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bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
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ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
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unsigned ArgsReg) override;
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unsigned ArgsReg, const EVT &VT) override;
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virtual void markPhysRegUsed(unsigned PhysReg) {
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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@ -127,21 +129,47 @@ private:
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} // end anonymous namespace
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void IncomingValueHandler::assignValueToReg(unsigned ValVReg,
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const CCValAssign &VA) {
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const CCValAssign &VA,
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const EVT &VT) {
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const MipsSubtarget &STI =
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static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
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unsigned PhysReg = VA.getLocReg();
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switch (VA.getLocInfo()) {
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case CCValAssign::LocInfo::SExt:
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case CCValAssign::LocInfo::ZExt:
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case CCValAssign::LocInfo::AExt: {
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auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
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MIRBuilder.buildTrunc(ValVReg, Copy);
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break;
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if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
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const MipsSubtarget &STI =
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static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
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MIRBuilder
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.buildInstr(STI.isFP64bit() ? Mips::BuildPairF64_64
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: Mips::BuildPairF64)
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.addDef(ValVReg)
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.addUse(PhysReg + (STI.isLittle() ? 0 : 1))
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.addUse(PhysReg + (STI.isLittle() ? 1 : 0))
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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markPhysRegUsed(PhysReg);
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markPhysRegUsed(PhysReg + 1);
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} else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
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MIRBuilder.buildInstr(Mips::MTC1)
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.addDef(ValVReg)
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.addUse(PhysReg)
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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markPhysRegUsed(PhysReg);
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} else {
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switch (VA.getLocInfo()) {
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case CCValAssign::LocInfo::SExt:
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case CCValAssign::LocInfo::ZExt:
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case CCValAssign::LocInfo::AExt: {
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auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
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MIRBuilder.buildTrunc(ValVReg, Copy);
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break;
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}
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default:
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MIRBuilder.buildCopy(ValVReg, PhysReg);
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break;
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}
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markPhysRegUsed(PhysReg);
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}
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default:
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MIRBuilder.buildCopy(ValVReg, PhysReg);
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break;
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}
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markPhysRegUsed(PhysReg);
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}
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unsigned IncomingValueHandler::getStackAddress(const CCValAssign &VA,
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@ -180,8 +208,8 @@ void IncomingValueHandler::assignValueToAddress(unsigned ValVReg,
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bool IncomingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs,
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ArrayRef<CCValAssign> ArgLocs,
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unsigned ArgLocsStartIndex,
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unsigned ArgsReg) {
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if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex))
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unsigned ArgsReg, const EVT &VT) {
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if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
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return false;
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setLeastSignificantFirst(VRegs);
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MIRBuilder.buildMerge(ArgsReg, VRegs);
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@ -196,7 +224,8 @@ public:
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: MipsHandler(MIRBuilder, MRI), MIB(MIB) {}
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private:
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void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) override;
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void assignValueToReg(unsigned ValVReg, const CCValAssign &VA,
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const EVT &VT) override;
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unsigned getStackAddress(const CCValAssign &VA,
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MachineMemOperand *&MMO) override;
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@ -205,7 +234,7 @@ private:
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bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
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ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
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unsigned ArgsReg) override;
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unsigned ArgsReg, const EVT &VT) override;
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unsigned extendRegister(unsigned ValReg, const CCValAssign &VA);
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@ -214,11 +243,40 @@ private:
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} // end anonymous namespace
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void OutgoingValueHandler::assignValueToReg(unsigned ValVReg,
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const CCValAssign &VA) {
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const CCValAssign &VA,
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const EVT &VT) {
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unsigned PhysReg = VA.getLocReg();
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unsigned ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildCopy(PhysReg, ExtReg);
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MIB.addUse(PhysReg, RegState::Implicit);
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const MipsSubtarget &STI =
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static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
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if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
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MIRBuilder
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.buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64
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: Mips::ExtractElementF64)
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.addDef(PhysReg + (STI.isLittle() ? 1 : 0))
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.addUse(ValVReg)
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.addImm(1)
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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MIRBuilder
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.buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64
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: Mips::ExtractElementF64)
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.addDef(PhysReg + (STI.isLittle() ? 0 : 1))
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.addUse(ValVReg)
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.addImm(0)
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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} else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
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MIRBuilder.buildInstr(Mips::MFC1)
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.addDef(PhysReg)
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.addUse(ValVReg)
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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} else {
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unsigned ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildCopy(PhysReg, ExtReg);
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MIB.addUse(PhysReg, RegState::Implicit);
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}
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}
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unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
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@ -286,10 +344,10 @@ unsigned OutgoingValueHandler::extendRegister(unsigned ValReg,
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bool OutgoingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs,
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ArrayRef<CCValAssign> ArgLocs,
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unsigned ArgLocsStartIndex,
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unsigned ArgsReg) {
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unsigned ArgsReg, const EVT &VT) {
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MIRBuilder.buildUnmerge(VRegs, ArgsReg);
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setLeastSignificantFirst(VRegs);
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if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex))
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if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
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return false;
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return true;
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@ -300,6 +358,8 @@ static bool isSupportedType(Type *T) {
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return true;
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if (T->isPointerTy())
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return true;
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if (T->isFloatingPointTy())
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return true;
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return false;
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}
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@ -35,7 +35,7 @@ public:
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protected:
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bool assignVRegs(ArrayRef<unsigned> VRegs, ArrayRef<CCValAssign> ArgLocs,
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unsigned Index);
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unsigned ArgLocsStartIndex, const EVT &VT);
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void setLeastSignificantFirst(SmallVectorImpl<unsigned> &VRegs);
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@ -43,19 +43,21 @@ public:
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MachineRegisterInfo &MRI;
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private:
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bool assign(unsigned VReg, const CCValAssign &VA);
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bool assign(unsigned VReg, const CCValAssign &VA, const EVT &VT);
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virtual unsigned getStackAddress(const CCValAssign &VA,
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MachineMemOperand *&MMO) = 0;
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virtual void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) = 0;
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virtual void assignValueToReg(unsigned ValVReg, const CCValAssign &VA,
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const EVT &VT) = 0;
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virtual void assignValueToAddress(unsigned ValVReg,
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const CCValAssign &VA) = 0;
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virtual bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
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ArrayRef<CCValAssign> ArgLocs,
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unsigned ArgLocsStartIndex, unsigned ArgsReg) = 0;
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unsigned ArgLocsStartIndex, unsigned ArgsReg,
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const EVT &VT) = 0;
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};
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MipsCallLowering(const MipsTargetLowering &TLI);
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211
test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
Normal file
211
test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
Normal file
@ -0,0 +1,211 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
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define float @float_in_fpr(float %a, float %b) {
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; FP32-LABEL: name: float_in_fpr
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; FP32: bb.1.entry:
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; FP32: liveins: $f12, $f14
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
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; FP32: $f0 = COPY [[COPY1]](s32)
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: float_in_fpr
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; FP64: bb.1.entry:
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; FP64: liveins: $f12, $f14
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
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; FP64: $f0 = COPY [[COPY1]](s32)
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; FP64: RetRA implicit $f0
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entry:
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ret float %b
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}
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define double @double_in_fpr(double %a, double %b) {
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; FP32-LABEL: name: double_in_fpr
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; FP32: bb.1.entry:
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; FP32: liveins: $d6, $d7
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; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
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; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
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; FP32: $d0 = COPY [[COPY1]](s64)
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: double_in_fpr
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; FP64: bb.1.entry:
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; FP64: liveins: $d12_64, $d14_64
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; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d12_64
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; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d14_64
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; FP64: $d0_64 = COPY [[COPY1]](s64)
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; FP64: RetRA implicit $d0_64
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entry:
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ret double %b
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}
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define float @float_in_gpr(i32 %a, float %b) {
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; FP32-LABEL: name: float_in_gpr
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; FP32: bb.1.entry:
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; FP32: liveins: $a0, $a1
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP32: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
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; FP32: $f0 = COPY [[MTC1_]](s32)
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: float_in_gpr
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; FP64: bb.1.entry:
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; FP64: liveins: $a0, $a1
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP64: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
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; FP64: $f0 = COPY [[MTC1_]](s32)
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; FP64: RetRA implicit $f0
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entry:
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ret float %b
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}
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define double @double_in_gpr(i32 %a, double %b) {
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; FP32-LABEL: name: double_in_gpr
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; FP32: bb.1.entry:
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; FP32: liveins: $a0, $a2, $a3
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 $a2, $a3
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; FP32: $d0 = COPY [[BuildPairF64_]](s64)
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: double_in_gpr
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; FP64: bb.1.entry:
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; FP64: liveins: $a0, $a2, $a3
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 $a2, $a3
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; FP64: $d0_64 = COPY [[BuildPairF64_64_]](s64)
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; FP64: RetRA implicit $d0_64
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entry:
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ret double %b
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}
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define float @call_float_in_fpr(float %a, float %b) {
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; FP32-LABEL: name: call_float_in_fpr
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; FP32: bb.1.entry:
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; FP32: liveins: $f12, $f14
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
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; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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; FP32: $f12 = COPY [[COPY]](s32)
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; FP32: $f14 = COPY [[COPY1]](s32)
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; FP32: JAL @float_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
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; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
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; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
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; FP32: $f0 = COPY [[COPY2]](s32)
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: call_float_in_fpr
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; FP64: bb.1.entry:
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; FP64: liveins: $f12, $f14
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
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; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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; FP64: $f12 = COPY [[COPY]](s32)
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; FP64: $f14 = COPY [[COPY1]](s32)
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; FP64: JAL @float_in_fpr, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
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; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
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; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
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; FP64: $f0 = COPY [[COPY2]](s32)
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; FP64: RetRA implicit $f0
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entry:
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%call = call float @float_in_fpr(float %a, float %b)
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ret float %call
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}
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define double @call_double_in_fpr(double %a, double %b) {
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; FP32-LABEL: name: call_double_in_fpr
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; FP32: bb.1.entry:
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; FP32: liveins: $d6, $d7
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; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
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; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
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; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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; FP32: $d6 = COPY [[COPY]](s64)
|
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; FP32: $d7 = COPY [[COPY1]](s64)
|
||||
; FP32: JAL @double_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
|
||||
; FP32: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
|
||||
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP32: $d0 = COPY [[COPY2]](s64)
|
||||
; FP32: RetRA implicit $d0
|
||||
; FP64-LABEL: name: call_double_in_fpr
|
||||
; FP64: bb.1.entry:
|
||||
; FP64: liveins: $d12_64, $d14_64
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d12_64
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d14_64
|
||||
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP64: $d12_64 = COPY [[COPY]](s64)
|
||||
; FP64: $d14_64 = COPY [[COPY1]](s64)
|
||||
; FP64: JAL @double_in_fpr, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit $d14_64, implicit-def $d0_64
|
||||
; FP64: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0_64
|
||||
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP64: $d0_64 = COPY [[COPY2]](s64)
|
||||
; FP64: RetRA implicit $d0_64
|
||||
entry:
|
||||
%call = call double @double_in_fpr(double %a, double %b)
|
||||
ret double %call
|
||||
}
|
||||
|
||||
define float @call_float_in_gpr(i32 %a, float %b) {
|
||||
; FP32-LABEL: name: call_float_in_gpr
|
||||
; FP32: bb.1.entry:
|
||||
; FP32: liveins: $a0, $a1
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; FP32: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
|
||||
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP32: $a0 = COPY [[COPY]](s32)
|
||||
; FP32: $a1 = MFC1 [[MTC1_]](s32)
|
||||
; FP32: JAL @float_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $f0
|
||||
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
|
||||
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP32: $f0 = COPY [[COPY1]](s32)
|
||||
; FP32: RetRA implicit $f0
|
||||
; FP64-LABEL: name: call_float_in_gpr
|
||||
; FP64: bb.1.entry:
|
||||
; FP64: liveins: $a0, $a1
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; FP64: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
|
||||
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP64: $a0 = COPY [[COPY]](s32)
|
||||
; FP64: $a1 = MFC1 [[MTC1_]](s32)
|
||||
; FP64: JAL @float_in_gpr, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $f0
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
|
||||
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP64: $f0 = COPY [[COPY1]](s32)
|
||||
; FP64: RetRA implicit $f0
|
||||
entry:
|
||||
%call = call float @float_in_gpr(i32 %a, float %b)
|
||||
ret float %call
|
||||
}
|
||||
|
||||
|
||||
define double @call_double_in_gpr(i32 %a, double %b) {
|
||||
; FP32-LABEL: name: call_double_in_gpr
|
||||
; FP32: bb.1.entry:
|
||||
; FP32: liveins: $a0, $a2, $a3
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 $a2, $a3
|
||||
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP32: $a0 = COPY [[COPY]](s32)
|
||||
; FP32: $a3 = ExtractElementF64 [[BuildPairF64_]](s64), 1
|
||||
; FP32: $a2 = ExtractElementF64 [[BuildPairF64_]](s64), 0
|
||||
; FP32: JAL @double_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $d0
|
||||
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
|
||||
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP32: $d0 = COPY [[COPY1]](s64)
|
||||
; FP32: RetRA implicit $d0
|
||||
; FP64-LABEL: name: call_double_in_gpr
|
||||
; FP64: bb.1.entry:
|
||||
; FP64: liveins: $a0, $a2, $a3
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 $a2, $a3
|
||||
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP64: $a0 = COPY [[COPY]](s32)
|
||||
; FP64: $a3 = ExtractElementF64_64 [[BuildPairF64_64_]](s64), 1
|
||||
; FP64: $a2 = ExtractElementF64_64 [[BuildPairF64_64_]](s64), 0
|
||||
; FP64: JAL @double_in_gpr, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $d0_64
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0_64
|
||||
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP64: $d0_64 = COPY [[COPY1]](s64)
|
||||
; FP64: RetRA implicit $d0_64
|
||||
entry:
|
||||
%call = call double @double_in_gpr(i32 %a, double %b)
|
||||
ret double %call
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user