RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
Code Issues Projects Releases Wiki Activity

TargetMachine: Move lib/CodeGen specific callbacks to LLVMTargetMachine; NFC

Browse Source 
llvm-svn: 346184
This commit is contained in:
Matthias Braun 2018-11-05 23:49:15 +00:00
parent bd8238f4c6
commit 81989e4ac5
1 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
include/llvm/Target/TargetMachine.h
View File

@ -284,18 +284,6 @@ public:
void getNameWithPrefix(SmallVectorImpl<char> &Name, const GlobalValue *GV, void getNameWithPrefix(SmallVectorImpl<char> &Name, const GlobalValue *GV,
Mangler &Mang, bool MayAlwaysUsePrivate = false) const; Mangler &Mang, bool MayAlwaysUsePrivate = false) const;
MCSymbol *getSymbol(const GlobalValue *GV) const; MCSymbol *getSymbol(const GlobalValue *GV) const;
/// True if the target uses physical regs at Prolog/Epilog insertion
/// time. If true (most machines), all vregs must be allocated before
/// PEI. If false (virtual-register machines), then callee-save register
/// spilling and scavenging are not needed or used.
virtual bool usesPhysRegsForPEI() const { return true; }
/// True if the target wants to use interprocedural register allocation by
/// default. The -enable-ipra flag can be used to override this.
virtual bool useIPRA() const {
return false;
}
}; };
/// This class describes a target machine that is implemented with the LLVM /// This class describes a target machine that is implemented with the LLVM
@ -349,6 +337,18 @@ public:
bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out, bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
raw_pwrite_stream *DwoOut, CodeGenFileType FileTYpe, raw_pwrite_stream *DwoOut, CodeGenFileType FileTYpe,
MCContext &Context); MCContext &Context);
/// True if the target uses physical regs at Prolog/Epilog insertion
/// time. If true (most machines), all vregs must be allocated before
/// PEI. If false (virtual-register machines), then callee-save register
/// spilling and scavenging are not needed or used.
virtual bool usesPhysRegsForPEI() const { return true; }
/// True if the target wants to use interprocedural register allocation by
/// default. The -enable-ipra flag can be used to override this.
virtual bool useIPRA() const {
return false;
}
}; };
} // end namespace llvm } // end namespace llvm