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[AMDGPU] gfx1010 exp modifications

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Differential Revision: https://reviews.llvm.org/D61701

llvm-svn: 360287
This commit is contained in:
Stanislav Mekhanoshin 2019-05-08 21:23:37 +00:00
parent cf649c2e81
commit 81a8a4beb0
6 changed files with 99 additions and 2 deletions
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7
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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@ -4764,13 +4764,18 @@ OperandMatchResultTy AMDGPUAsmParser::parseExpTgtImpl(StringRef Str,
if (Str.getAsInteger(10, Val))
return MatchOperand_ParseFail;
if (Val > 3)
if (Val > 4 || (Val == 4 && !isGFX10()))
errorExpTgt();
Val += 12;
return MatchOperand_Success;
}
if (isGFX10() && Str == "prim") {
Val = 20;
return MatchOperand_Success;
}
if (Str.startswith("param")) {
Str = Str.drop_front(5);
if (Str.getAsInteger(10, Val))

4
lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
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@ -923,8 +923,10 @@ void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
O << " mrtz";
else if (Tgt == 9)
O << " null";
else if (Tgt >= 12 && Tgt <= 15)
else if ((Tgt >= 12 && Tgt <= 15) || (Tgt == 16 && AMDGPU::isGFX10(STI)))
O << " pos" << Tgt - 12;
else if (AMDGPU::isGFX10(STI) && Tgt == 20)
O << " prim";
else if (Tgt >= 32 && Tgt <= 63)
O << " param" << Tgt - 32;
else {

8
lib/Target/AMDGPU/SIInstrInfo.td
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@ -1159,6 +1159,14 @@ multiclass EXP_m<bit done, SDPatternOperator node> {
let DecoderNamespace = "GFX8";
let DisableDecoder = DisableVIDecoder;
}
def _gfx10 : EXP_Helper<done>,
SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.GFX10>,
EXPe {
let AssemblerPredicates = [isGFX10Plus];
let DecoderNamespace = "GFX10";
let DisableDecoder = DisableSIDecoder;
}
}
}
}

15
test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll Normal file
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@ -0,0 +1,15 @@
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=NOPRIM %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=PRIM %s
declare void @llvm.amdgcn.exp.i32(i32, i32, i32, i32, i32, i32, i1, i1) #1
; GCN-LABEL: {{^}}test_export_prim_i32:
; NOPRIM: exp invalid_target_20 v0, off, off, off done{{$}}
; PRIM: exp prim v0, off, off, off done{{$}}
define amdgpu_gs void @test_export_prim_i32(i32 inreg %a) #0 {
call void @llvm.amdgcn.exp.i32(i32 20, i32 1, i32 %a, i32 undef, i32 undef, i32 undef, i1 true, i1 false)
ret void
}
attributes #0 = { nounwind }
attributes #1 = { nounwind inaccessiblememonly }

18
test/MC/AMDGPU/exp-gfx10.s Normal file
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@ -0,0 +1,18 @@
// RUN: not llvm-mc -arch=amdgcn -mcpu=verde -show-encoding %s 2>&1 | FileCheck -check-prefix=SI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=VI %s
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
exp prim v1, off, off, off
// SI: :5: error: invalid operand for instruction
// VI: :5: error: invalid operand for instruction
// GFX10: exp prim v1, off, off, off ; encoding: [0x41,0x01,0x00,0xf8,0x01,0x00,0x00,0x00]
exp prim v2, v3, off, off
// SI: :5: error: invalid operand for instruction
// VI: :5: error: invalid operand for instruction
// GFX10: exp prim v2, v3, off, off ; encoding: [0x43,0x01,0x00,0xf8,0x02,0x03,0x00,0x00]
exp pos4 v4, v3, v2, v1
// SI: error: invalid exp target
// VI: error: invalid exp target
// GFX10: exp pos4 v4, v3, v2, v1 ; encoding: [0x0f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01]

49
test/MC/Disassembler/AMDGPU/exp_gfx10.txt Normal file
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@ -0,0 +1,49 @@
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GXF10
# GXF10: exp mrt0 v1, v2, v3, v4 ; encoding: [0x0f,0x00,0x00,0xf8,0x01,0x02,0x03,0x04]
0x0f,0x00,0x00,0xf8,0x01,0x02,0x03,0x04
# GXF10: exp mrt0 v1, v2, v3, v4 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x01,0x02,0x03,0x04]
0x0f,0x10,0x00,0xf8,0x01,0x02,0x03,0x04
# GXF10: exp mrt0 v1, v1, v3, v3 compr ; encoding: [0x0f,0x04,0x00,0xf8,0x01,0x03,0x00,0x00]
0x0f,0x04,0x00,0xf8,0x01,0x03,0x00,0x00
# GXF10: exp mrt0 v1, v2, v3, v4 done ; encoding: [0x0f,0x08,0x00,0xf8,0x01,0x02,0x03,0x04]
0x0f,0x08,0x00,0xf8,0x01,0x02,0x03,0x04
# GXF10: exp mrt0 v2, v2, v4, v4 done compr vm ; encoding: [0x0f,0x1c,0x00,0xf8,0x02,0x04,0x00,0x00]
0x0f,0x1c,0x00,0xf8,0x02,0x04,0x00,0x00
# GXF10: exp mrt0 v7, off, off, off vm ; encoding: [0x01,0x10,0x00,0xf8,0x07,0x00,0x00,0x00]
0x01,0x10,0x00,0xf8,0x07,0x00,0x00,0x00
# GXF10: exp mrt0 off, off, v1, v2 ; encoding: [0x0c,0x00,0x00,0xf8,0x00,0x00,0x01,0x02]
0x0c,0x00,0x00,0xf8,0x00,0x00,0x01,0x02
# GXF10: exp mrt0 off, off, v8, v8 done compr ; encoding: [0x0c,0x0c,0x00,0xf8,0x00,0x08,0x00,0x00]
0x0c,0x0c,0x00,0xf8,0x00,0x08,0x00,0x00
# GXF10: exp mrt0 v1, v1, off, off compr ; encoding: [0x03,0x04,0x00,0xf8,0x01,0x00,0x00,0x00]
0x03,0x04,0x00,0xf8,0x01,0x00,0x00,0x00
# GXF10: exp param0 off, off, off, off compr ; encoding: [0x00,0x06,0x00,0xf8,0x00,0x00,0x00,0x00]
0x00,0x06,0x00,0xf8,0x00,0x00,0x00,0x00
# GXF10: exp mrtz v0, off, off, off done vm ; encoding: [0x81,0x18,0x00,0xf8,0x00,0x00,0x00,0x00]
0x81,0x18,0x00,0xf8,0x00,0x00,0x00,0x00
# GXF10: exp null v255, v0, v255, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0xff,0x00,0xff,0x00]
0x9f,0x00,0x00,0xf8,0xff,0x00,0xff,0x00
# GXF10: exp pos0 v1, off, off, off ; encoding: [0xc1,0x00,0x00,0xf8,0x01,0x00,0x00,0x00]
0xc1,0x00,0x00,0xf8,0x01,0x00,0x00,0x00
# GXF10: exp pos3 v1, off, off, off ; encoding: [0xf1,0x00,0x00,0xf8,0x01,0x00,0x00,0x00]
0xf1,0x00,0x00,0xf8,0x01,0x00,0x00,0x00
# GXF10: exp pos4 v1, off, off, off ; encoding: [0x01,0x01,0x00,0xf8,0x01,0x00,0x00,0x00]
0x01,0x01,0x00,0xf8,0x01,0x00,0x00,0x00
# GXF10: exp prim v2, v3, off, off ; encoding: [0x43,0x01,0x00,0xf8,0x02,0x03,0x00,0x00]
0x43,0x01,0x00,0xf8,0x02,0x03,0x00,0x00