diff --git a/include/llvm/IR/IntrinsicsSystemZ.td b/include/llvm/IR/IntrinsicsSystemZ.td
index b0c5cf0148f..81435e98bea 100644
--- a/include/llvm/IR/IntrinsicsSystemZ.td
+++ b/include/llvm/IR/IntrinsicsSystemZ.td
@@ -436,6 +436,28 @@ let TargetPrefix = "s390" in {
   def int_s390_vstrszb : SystemZTernaryConvCC<llvm_v16i8_ty, llvm_v16i8_ty>;
   def int_s390_vstrszh : SystemZTernaryConvCC<llvm_v16i8_ty, llvm_v8i16_ty>;
   def int_s390_vstrszf : SystemZTernaryConvCC<llvm_v16i8_ty, llvm_v4i32_ty>;
+
+  // Instructions from the NNP-assist Facility
+  def int_s390_vclfnhs : GCCBuiltin<"__builtin_s390_vclfnhs">,
+                         Intrinsic<[llvm_v4f32_ty],
+                                   [llvm_v8i16_ty, llvm_i32_ty],
+                                   [IntrNoMem, ImmArg<ArgIndex<1>>]>;
+  def int_s390_vclfnls : GCCBuiltin<"__builtin_s390_vclfnls">,
+                         Intrinsic<[llvm_v4f32_ty],
+                                   [llvm_v8i16_ty, llvm_i32_ty],
+                                   [IntrNoMem, ImmArg<ArgIndex<1>>]>;
+  def int_s390_vcrnfs : GCCBuiltin<"__builtin_s390_vcrnfs">,
+                        Intrinsic<[llvm_v8i16_ty],
+                                  [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty],
+                                  [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+  def int_s390_vcfn : GCCBuiltin<"__builtin_s390_vcfn">,
+                      Intrinsic<[llvm_v8i16_ty],
+                                [llvm_v8i16_ty, llvm_i32_ty],
+                                [IntrNoMem, ImmArg<ArgIndex<1>>]>;
+  def int_s390_vcnf : GCCBuiltin<"__builtin_s390_vcnf">,
+                      Intrinsic<[llvm_v8i16_ty],
+                                [llvm_v8i16_ty, llvm_i32_ty],
+                                [IntrNoMem, ImmArg<ArgIndex<1>>]>;
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp
index 3336587aa85..f873ff06f1f 100644
--- a/lib/Support/Host.cpp
+++ b/lib/Support/Host.cpp
@@ -324,8 +324,11 @@ StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) {
       return HaveVectorSupport? "z14" : "zEC12";
     case 8561:
     case 8562:
-    default:
       return HaveVectorSupport? "z15" : "zEC12";
+    case 3931:
+    case 3932:
+    default:
+      return HaveVectorSupport? "arch14" : "zEC12";
   }
 }
 } // end anonymous namespace
diff --git a/lib/Target/SystemZ/SystemZFeatures.td b/lib/Target/SystemZ/SystemZFeatures.td
index b1706a4a899..78b8394d648 100644
--- a/lib/Target/SystemZ/SystemZFeatures.td
+++ b/lib/Target/SystemZ/SystemZFeatures.td
@@ -291,6 +291,45 @@ def Arch13NewFeatures : SystemZFeatureList<[
     FeatureDeflateConversion
 ]>;
 
+//===----------------------------------------------------------------------===//
+//
+// New features added in the Fourteenth Edition of the z/Architecture
+//
+//===----------------------------------------------------------------------===//
+
+def FeatureVectorPackedDecimalEnhancement2 : SystemZFeature<
+  "vector-packed-decimal-enhancement-2", "VectorPackedDecimalEnhancement2", (all_of FeatureVectorPackedDecimalEnhancement2),
+  "Assume that the vector packed decimal enhancement facility 2 is installed"
+>;
+
+def FeatureNNPAssist : SystemZFeature<
+  "nnp-assist", "NNPAssist", (all_of FeatureNNPAssist),
+  "Assume that the NNP-assist facility is installed"
+>;
+
+def FeatureBEAREnhancement : SystemZFeature<
+  "bear-enhancement", "BEAREnhancement", (all_of FeatureBEAREnhancement),
+  "Assume that the BEAR-enhancement facility is installed"
+>;
+
+def FeatureResetDATProtection : SystemZFeature<
+  "reset-dat-protection", "ResetDATProtection", (all_of FeatureResetDATProtection),
+  "Assume that the reset-DAT-protection facility is installed"
+>;
+
+def FeatureProcessorActivityInstrumentation : SystemZFeature<
+  "processor-activity-instrumentation", "ProcessorActivityInstrumentation", (all_of FeatureProcessorActivityInstrumentation),
+  "Assume that the processor-activity-instrumentation facility is installed"
+>;
+
+def Arch14NewFeatures : SystemZFeatureList<[
+    FeatureVectorPackedDecimalEnhancement2,
+    FeatureNNPAssist,
+    FeatureBEAREnhancement,
+    FeatureResetDATProtection,
+    FeatureProcessorActivityInstrumentation
+]>;
+
 //===----------------------------------------------------------------------===//
 //
 // Cumulative supported and unsupported feature sets
@@ -309,9 +348,13 @@ def Arch12SupportedFeatures
   : SystemZFeatureAdd<Arch11SupportedFeatures.List, Arch12NewFeatures.List>;
 def Arch13SupportedFeatures
   : SystemZFeatureAdd<Arch12SupportedFeatures.List, Arch13NewFeatures.List>;
+def Arch14SupportedFeatures
+  : SystemZFeatureAdd<Arch13SupportedFeatures.List, Arch14NewFeatures.List>;
 
-def Arch13UnsupportedFeatures
+def Arch14UnsupportedFeatures
   : SystemZFeatureList<[]>;
+def Arch13UnsupportedFeatures
+  : SystemZFeatureAdd<Arch14UnsupportedFeatures.List, Arch14NewFeatures.List>;
 def Arch12UnsupportedFeatures
   : SystemZFeatureAdd<Arch13UnsupportedFeatures.List, Arch13NewFeatures.List>;
 def Arch11UnsupportedFeatures
diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td
index bc2fe8e4c4c..5cb46cdb36a 100644
--- a/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -1438,6 +1438,55 @@ class InstVRRi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   let Inst{7-0}   = op{7-0};
 }
 
+class InstVRRj<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<6, outs, ins, asmstr, pattern> {
+  field bits<48> Inst;
+  field bits<48> SoftFail = 0;
+
+  bits<5> V1;
+  bits<5> V2;
+  bits<5> V3;
+  bits<4> M4;
+
+  let Inst{47-40} = op{15-8};
+  let Inst{39-36} = V1{3-0};
+  let Inst{35-32} = V2{3-0};
+  let Inst{31-28} = V3{3-0};
+  let Inst{27-24} = 0;
+  let Inst{23-20} = M4;
+  let Inst{19-16} = 0;
+  let Inst{15-12} = 0;
+  let Inst{11}    = V1{4};
+  let Inst{10}    = V2{4};
+  let Inst{9}     = V3{4};
+  let Inst{8}     = 0;
+  let Inst{7-0}   = op{7-0};
+}
+
+class InstVRRk<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<6, outs, ins, asmstr, pattern> {
+  field bits<48> Inst;
+  field bits<48> SoftFail = 0;
+
+  bits<5> V1;
+  bits<5> V2;
+  bits<4> M3;
+
+  let Inst{47-40} = op{15-8};
+  let Inst{39-36} = V1{3-0};
+  let Inst{35-32} = V2{3-0};
+  let Inst{31-28} = 0;
+  let Inst{27-24} = 0;
+  let Inst{23-20} = M3;
+  let Inst{19-16} = 0;
+  let Inst{15-12} = 0;
+  let Inst{11}    = V1{4};
+  let Inst{10}    = V2{4};
+  let Inst{9}     = 0;
+  let Inst{8}     = 0;
+  let Inst{7-0}   = op{7-0};
+}
+
 class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
@@ -2780,6 +2829,16 @@ class SideEffectUnaryS<string mnemonic, bits<16> opcode,
   let AccessBytes = bytes;
 }
 
+class SideEffectUnarySIY<string mnemonic, bits<16> opcode,
+                         bits<5> bytes,
+                         AddressingMode mode = bdaddr20only>
+  : InstSIY<opcode, (outs), (ins mode:$BD1),
+            mnemonic#"\t$BD1", []> {
+  let mayLoad = 1;
+  let AccessBytes = bytes;
+  let I2 = 0;
+}
+
 class SideEffectAddressS<string mnemonic, bits<16> opcode,
                         SDPatternOperator operator,
                         AddressingMode mode = bdaddr12only>
@@ -3660,6 +3719,17 @@ class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
   let M5 = modifier;
 }
 
+class BinaryExtraVRRb<string mnemonic, bits<16> opcode, bits<4> type = 0>
+  : InstVRRb<opcode, (outs VR128:$V1), (ins VR128:$V2, VR128:$V3, imm32zx4:$M5),
+             mnemonic#"\t$V1, $V2, $V3, $M5", []> {
+  let M4 = type;
+}
+
+class BinaryExtraVRRbGeneric<string mnemonic, bits<16> opcode>
+  : InstVRRb<opcode, (outs VR128:$V1),
+             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
+             mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
+
 // Declare a pair of instructions, one which sets CC and one which doesn't.
 // The CC-setting form ends with "S" and sets the low bit of M5.
 multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
@@ -3773,6 +3843,10 @@ class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
   let M4 = 0;
 }
 
+class BinaryVRRk<string mnemonic, bits<16> opcode>
+  : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
+             mnemonic#"\t$V1, $V2, $M3", []>;
+
 class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  TypedReg tr1, TypedReg tr2, bits<4> type>
   : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
@@ -4534,6 +4608,11 @@ class TernaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
                                       imm32zx4:$M3, imm32zx4:$M4),
              mnemonic#"\t$R1, $V2, $M3, $M4", []>;
 
+class TernaryVRRj<string mnemonic, bits<16> opcode>
+  : InstVRRj<opcode, (outs VR128:$V1), (ins VR128:$V2,
+                                        VR128:$V3, imm32zx4:$M4),
+             mnemonic#"\t$V1, $V2, $V3, $M4", []>;
+
 class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
   : InstVRSb<opcode, (outs VR128:$V1),
              (ins VR128:$V1src, GR64:$R3, shift12only:$BD2, imm32zx4:$M4),
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index ca095074001..7df7cc93d6e 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2163,6 +2163,11 @@ let Predicates = [FeatureDeflateConversion],
   def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939,
                                            GR128, GR128, GR64>;
 
+// NNPA.
+let Predicates = [FeatureNNPAssist],
+    mayLoad = 1, mayStore = 1, Defs = [R0D, CC], Uses = [R0D, R1D] in
+  def NNPA : SideEffectInherentRRE<"nnpa", 0xB93B>;
+
 // Execute.
 let hasSideEffects = 1 in {
   def EX   : SideEffectBinaryRX<"ex", 0x44, ADDR64>;
diff --git a/lib/Target/SystemZ/SystemZInstrSystem.td b/lib/Target/SystemZ/SystemZInstrSystem.td
index ecce16c9cd7..e26417ddb72 100644
--- a/lib/Target/SystemZ/SystemZInstrSystem.td
+++ b/lib/Target/SystemZ/SystemZInstrSystem.td
@@ -26,6 +26,8 @@ let hasSideEffects = 1, Defs = [CC] in {
   def LPSW : SideEffectUnaryS<"lpsw", 0x8200, null_frag, 8>;
   def LPSWE : SideEffectUnaryS<"lpswe", 0xB2B2, null_frag, 16>;
 }
+let Predicates = [FeatureBEAREnhancement], hasSideEffects = 1, Defs = [CC] in
+  def LPSWEY : SideEffectUnarySIY<"lpswey", 0xEB71, 16>;
 
 // Insert PSW key.
 let Uses = [R2L], Defs = [R2L] in
@@ -103,6 +105,20 @@ let hasSideEffects = 1 in
 let hasSideEffects = 1 in
   def STPX : StoreInherentS<"stpx", 0xB211, null_frag, 4>;
 
+//===----------------------------------------------------------------------===//
+// Breaking-Event-Address-Register Instructions.
+//===----------------------------------------------------------------------===//
+
+let Predicates = [FeatureBEAREnhancement] in {
+  // Load BEAR.
+  let hasSideEffects = 1 in
+    def LBEAR : SideEffectUnaryS<"lbear", 0xB200, null_frag, 8>;
+
+  // Store BEAR.
+  let hasSideEffects = 1 in
+    def STBEAR : StoreInherentS<"stbear", 0xB201, null_frag, 8>;
+}
+
 //===----------------------------------------------------------------------===//
 // Storage-Key and Real Memory Instructions.
 //===----------------------------------------------------------------------===//
@@ -157,6 +173,10 @@ let hasSideEffects = 1 in
 let hasSideEffects = 1 in
   defm IDTE : SideEffectQuaternaryRRFbOpt<"idte", 0xB98E, GR64, GR64, GR64>;
 
+// Reset DAT protection.
+let Predicates = [FeatureResetDATProtection], hasSideEffects = 1 in
+  defm RDP : SideEffectQuaternaryRRFbOpt<"rdp", 0xB98B, GR64, GR64, GR64>;
+
 // Compare and replace DAT table entry.
 let Predicates = [FeatureEnhancedDAT2], hasSideEffects = 1, Defs = [CC] in
   defm CRDTE : SideEffectQuaternaryRRFbOpt<"crdte", 0xB98F, GR128, GR128, GR64>;
@@ -372,6 +392,11 @@ let Predicates = [FeatureMessageSecurityAssist3],
     hasSideEffects = 1, Uses = [R0L, R1D] in
   def PCKMO : SideEffectInherentRRE<"pckmo", 0xB928>;
 
+// Query processor activity counter information.
+let Predicates = [FeatureProcessorActivityInstrumentation],
+    hasSideEffects = 1, Uses = [R0D], Defs = [R0D, CC] in
+  def QPACI : StoreInherentS<"qpaci", 0xB28F, null_frag, 0>;
+
 //===----------------------------------------------------------------------===//
 // Miscellaneous Instructions.
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/SystemZ/SystemZInstrVector.td b/lib/Target/SystemZ/SystemZInstrVector.td
index a85eb1623e1..2e9524a44f9 100644
--- a/lib/Target/SystemZ/SystemZInstrVector.td
+++ b/lib/Target/SystemZ/SystemZInstrVector.td
@@ -1749,6 +1749,37 @@ let Predicates = [FeatureVectorEnhancements2] in {
   }
 }
 
+//===----------------------------------------------------------------------===//
+// NNP assist instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [FeatureVector, FeatureNNPAssist] in {
+  let Uses = [FPC], mayRaiseFPException = 1 in
+    def VCFN : UnaryVRRaFloatGeneric<"vcfn", 0xE65D>;
+  def : Pat<(int_s390_vcfn VR128:$x, imm32zx4_timm:$m),
+            (VCFN VR128:$x, 1, imm32zx4:$m)>;
+
+  let Uses = [FPC], mayRaiseFPException = 1 in
+    def VCLFNL : UnaryVRRaFloatGeneric<"vclfnl", 0xE65E>;
+  def : Pat<(int_s390_vclfnls VR128:$x, imm32zx4_timm:$m),
+            (VCLFNL VR128:$x, 2, imm32zx4:$m)>;
+
+  let Uses = [FPC], mayRaiseFPException = 1 in
+    def VCLFNH : UnaryVRRaFloatGeneric<"vclfnh", 0xE656>;
+  def : Pat<(int_s390_vclfnhs VR128:$x, imm32zx4_timm:$m),
+            (VCLFNH VR128:$x, 2, imm32zx4:$m)>;
+
+  let Uses = [FPC], mayRaiseFPException = 1 in
+    def VCNF : UnaryVRRaFloatGeneric<"vcnf", 0xE655>;
+  def : Pat<(int_s390_vcnf VR128:$x, imm32zx4_timm:$m),
+            (VCNF VR128:$x, imm32zx4:$m, 1)>;
+
+  let Uses = [FPC], mayRaiseFPException = 1 in
+    def VCRNF : BinaryVRRcFloatGeneric<"vcrnf", 0xE675>;
+  def : Pat<(int_s390_vcrnfs VR128:$x, VR128:$y, imm32zx4_timm:$m),
+            (VCRNF VR128:$x, VR128:$y, imm32zx4:$m, 2)>;
+}
+
 //===----------------------------------------------------------------------===//
 // Packed-decimal instructions
 //===----------------------------------------------------------------------===//
@@ -1786,3 +1817,26 @@ let Predicates = [FeatureVectorPackedDecimal] in {
     def VCP : CompareVRRh<"vcp", 0xE677>;
   }
 }
+
+let Predicates = [FeatureVectorPackedDecimalEnhancement2] in {
+  def VSCHP : BinaryExtraVRRbGeneric<"vschp", 0xE674>;
+  def VSCHSP : BinaryExtraVRRb<"vschsp", 0xE674, 2>;
+  def VSCHDP : BinaryExtraVRRb<"vschdp", 0xE674, 3>;
+  def VSCHXP : BinaryExtraVRRb<"vschxp", 0xE674, 4>;
+
+  def VSCSHP : BinaryVRRb<"vscshp", 0xE67C, null_frag, v128b, v128b>;
+
+  def VCSPH : TernaryVRRj<"vcsph", 0xE67D>;
+
+  let Defs = [CC] in
+    def VCLZDP : BinaryVRRk<"vclzdp", 0xE651>;
+
+  let Defs = [CC] in
+    def VSRPR : QuaternaryVRIf<"vsrpr", 0xE672>;
+
+  let Defs = [CC] in {
+    def VPKZR : QuaternaryVRIf<"vpkzr", 0xE670>;
+    def VUPKZH : BinaryVRRk<"vupkzh", 0xE654>;
+    def VUPKZL : BinaryVRRk<"vupkzl", 0xE65C>;
+  }
+}
diff --git a/lib/Target/SystemZ/SystemZProcessors.td b/lib/Target/SystemZ/SystemZProcessors.td
index 57c2411b8dc..4fceaa14c59 100644
--- a/lib/Target/SystemZ/SystemZProcessors.td
+++ b/lib/Target/SystemZ/SystemZProcessors.td
@@ -38,3 +38,5 @@ def : ProcessorModel<"z14", Z14Model, Arch12SupportedFeatures.List>;
 def : ProcessorModel<"arch13", Z15Model, Arch13SupportedFeatures.List>;
 def : ProcessorModel<"z15", Z15Model, Arch13SupportedFeatures.List>;
 
+def : ProcessorModel<"arch14", Z15Model, Arch14SupportedFeatures.List>;
+
diff --git a/lib/Target/SystemZ/SystemZSubtarget.cpp b/lib/Target/SystemZ/SystemZSubtarget.cpp
index 0b344c1fe9c..bfcdee270f2 100644
--- a/lib/Target/SystemZ/SystemZSubtarget.cpp
+++ b/lib/Target/SystemZ/SystemZSubtarget.cpp
@@ -45,6 +45,7 @@ SystemZSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
     HasVectorEnhancements2 = false;
     HasVectorPackedDecimal = false;
     HasVectorPackedDecimalEnhancement = false;
+    HasVectorPackedDecimalEnhancement2 = false;
   }
 
   return *this;
@@ -82,7 +83,10 @@ SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
       HasInsertReferenceBitsMultiple(false), HasMiscellaneousExtensions3(false),
       HasMessageSecurityAssist9(false), HasVectorEnhancements2(false),
       HasVectorPackedDecimalEnhancement(false), HasEnhancedSort(false),
-      HasDeflateConversion(false), HasSoftFloat(false), TargetTriple(TT),
+      HasDeflateConversion(false), HasVectorPackedDecimalEnhancement2(false),
+      HasNNPAssist(false), HasBEAREnhancement(false),
+      HasResetDATProtection(false), HasProcessorActivityInstrumentation(false),
+      HasSoftFloat(false), TargetTriple(TT),
       SpecialRegisters(initializeSpecialRegisters()),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       TSInfo(), FrameLowering() {}
diff --git a/lib/Target/SystemZ/SystemZSubtarget.h b/lib/Target/SystemZ/SystemZSubtarget.h
index 2fc7d30ec0c..f6c155de44a 100644
--- a/lib/Target/SystemZ/SystemZSubtarget.h
+++ b/lib/Target/SystemZ/SystemZSubtarget.h
@@ -68,6 +68,11 @@ protected:
   bool HasVectorPackedDecimalEnhancement;
   bool HasEnhancedSort;
   bool HasDeflateConversion;
+  bool HasVectorPackedDecimalEnhancement2;
+  bool HasNNPAssist;
+  bool HasBEAREnhancement;
+  bool HasResetDATProtection;
+  bool HasProcessorActivityInstrumentation;
   bool HasSoftFloat;
 
 private:
@@ -250,6 +255,27 @@ public:
   // Return true if the target has the deflate-conversion facility.
   bool hasDeflateConversion() const { return HasDeflateConversion; }
 
+  // Return true if the target has the vector-packed-decimal
+  // enhancement facility 2.
+  bool hasVectorPackedDecimalEnhancement2() const {
+    return HasVectorPackedDecimalEnhancement2;
+  }
+
+  // Return true if the target has the NNP-assist facility.
+  bool hasNNPAssist() const { return HasNNPAssist; }
+
+  // Return true if the target has the BEAR-enhancement facility.
+  bool hasBEAREnhancement() const { return HasBEAREnhancement; }
+
+  // Return true if the target has the reset-DAT-protection facility.
+  bool hasResetDATProtection() const { return HasResetDATProtection; }
+
+  // Return true if the target has the processor-activity-instrumentation
+  // facility.
+  bool hasProcessorActivityInstrumentation() const {
+    return HasProcessorActivityInstrumentation;
+  }
+
   // Return true if soft float should be used.
   bool hasSoftFloat() const { return HasSoftFloat; }
 
diff --git a/test/CodeGen/SystemZ/vec-intrinsics-04.ll b/test/CodeGen/SystemZ/vec-intrinsics-04.ll
new file mode 100644
index 00000000000..4b61d5a43f1
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-intrinsics-04.ll
@@ -0,0 +1,54 @@
+; Test vector intrinsics added with arch14.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch14 | FileCheck %s
+
+declare <4 x float> @llvm.s390.vclfnhs(<8 x i16>, i32)
+declare <4 x float> @llvm.s390.vclfnls(<8 x i16>, i32)
+declare <8 x i16> @llvm.s390.vcrnfs(<4 x float>, <4 x float>, i32)
+declare <8 x i16> @llvm.s390.vcfn(<8 x i16>, i32)
+declare <8 x i16> @llvm.s390.vcnf(<8 x i16>, i32)
+
+; VCLFNH.
+define <4 x float> @test_vclfnhs(<8 x i16> %a) {
+; CHECK-LABEL: test_vclfnhs:
+; CHECK: vclfnh %v24, %v24, 2, 0
+; CHECK: br %r14
+  %res = call <4 x float> @llvm.s390.vclfnhs(<8 x i16> %a, i32 0)
+  ret <4 x float> %res
+}
+
+; VCLFNL.
+define <4 x float> @test_vclfnls(<8 x i16> %a) {
+; CHECK-LABEL: test_vclfnls:
+; CHECK: vclfnl %v24, %v24, 2, 0
+; CHECK: br %r14
+  %res = call <4 x float> @llvm.s390.vclfnls(<8 x i16> %a, i32 0)
+  ret <4 x float> %res
+}
+
+; VCRNF.
+define <8 x i16> @test_vcrnfs(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: test_vcrnfs:
+; CHECK: vcrnf %v24, %v24, %v26, 0, 2
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vcrnfs(<4 x float> %a, <4 x float> %b, i32 0)
+  ret <8 x i16> %res
+}
+
+; VCFN.
+define <8 x i16> @test_vcfn(<8 x i16> %a) {
+; CHECK-LABEL: test_vcfn:
+; CHECK: vcfn %v24, %v24, 1, 0
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vcfn(<8 x i16> %a, i32 0)
+  ret <8 x i16> %res
+}
+
+; VCNF.
+define <8 x i16> @test_vcnf(<8 x i16> %a) {
+; CHECK-LABEL: test_vcnf:
+; CHECK: vcnf %v24, %v24, 0, 1
+; CHECK: br %r14
+  %res = call <8 x i16> @llvm.s390.vcnf(<8 x i16> %a, i32 0)
+  ret <8 x i16> %res
+}
diff --git a/test/MC/Disassembler/SystemZ/insns-arch14.txt b/test/MC/Disassembler/SystemZ/insns-arch14.txt
new file mode 100644
index 00000000000..5f8dacc2d2f
--- /dev/null
+++ b/test/MC/Disassembler/SystemZ/insns-arch14.txt
@@ -0,0 +1,499 @@
+# Test arch14 instructions that don't have PC-relative operands.
+# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=arch14 \
+# RUN:   | FileCheck %s
+
+# CHECK: lbear 0
+0xb2 0x00 0x00 0x00
+
+# CHECK: lbear 0(%r1)
+0xb2 0x00 0x10 0x00
+
+# CHECK: lbear 0(%r15)
+0xb2 0x00 0xf0 0x00
+
+# CHECK: lbear 4095
+0xb2 0x00 0x0f 0xff
+
+# CHECK: lbear 4095(%r1)
+0xb2 0x00 0x1f 0xff
+
+# CHECK: lbear 4095(%r15)
+0xb2 0x00 0xff 0xff
+
+# CHECK: lpswey -524288
+0xeb 0x00 0x00 0x00 0x80 0x71
+
+# CHECK: lpswey -1
+0xeb 0x00 0x0f 0xff 0xff 0x71
+
+# CHECK: lpswey 0
+0xeb 0x00 0x00 0x00 0x00 0x71
+
+# CHECK: lpswey 1
+0xeb 0x00 0x00 0x01 0x00 0x71
+
+# CHECK: lpswey 524287
+0xeb 0x00 0x0f 0xff 0x7f 0x71
+
+# CHECK: lpswey 0(%r1)
+0xeb 0x00 0x10 0x00 0x00 0x71
+
+# CHECK: lpswey 0(%r15)
+0xeb 0x00 0xf0 0x00 0x00 0x71
+
+# CHECK: lpswey 524287(%r1)
+0xeb 0x00 0x1f 0xff 0x7f 0x71
+
+# CHECK: lpswey 524287(%r15)
+0xeb 0x00 0xff 0xff 0x7f 0x71
+
+# CHECK: nnpa
+0xb9 0x3b 0x00 0x00
+
+# CHECK: qpaci 0
+0xb2 0x8f 0x00 0x00
+
+# CHECK: qpaci 0(%r1)
+0xb2 0x8f 0x10 0x00
+
+# CHECK: qpaci 0(%r15)
+0xb2 0x8f 0xf0 0x00
+
+# CHECK: qpaci 4095
+0xb2 0x8f 0x0f 0xff
+
+# CHECK: qpaci 4095(%r1)
+0xb2 0x8f 0x1f 0xff
+
+# CHECK: qpaci 4095(%r15)
+0xb2 0x8f 0xff 0xff
+
+# CHECK: rdp %r0, %r0, %r0
+0xb9 0x8b 0x00 0x00
+
+# CHECK: rdp %r0, %r0, %r15
+0xb9 0x8b 0x00 0x0f
+
+# CHECK: rdp %r0, %r15, %r0
+0xb9 0x8b 0xf0 0x00
+
+# CHECK: rdp %r15, %r0, %r0
+0xb9 0x8b 0x00 0xf0
+
+# CHECK: rdp %r0, %r0, %r0, 15
+0xb9 0x8b 0x0f 0x00
+
+# CHECK: rdp %r4, %r5, %r6, 7
+0xb9 0x8b 0x57 0x46
+
+# CHECK: stbear 0
+0xb2 0x01 0x00 0x00
+
+# CHECK: stbear 0(%r1)
+0xb2 0x01 0x10 0x00
+
+# CHECK: stbear 0(%r15)
+0xb2 0x01 0xf0 0x00
+
+# CHECK: stbear 4095
+0xb2 0x01 0x0f 0xff
+
+# CHECK: stbear 4095(%r1)
+0xb2 0x01 0x1f 0xff
+
+# CHECK: stbear 4095(%r15)
+0xb2 0x01 0xff 0xff
+
+# CHECK: vcfn %v0, %v0, 0, 0
+0xe6 0x00 0x00 0x00 0x00 0x5d
+
+# CHECK: vcfn %v0, %v0, 15, 0
+0xe6 0x00 0x00 0x00 0xf0 0x5d
+
+# CHECK: vcfn %v0, %v0, 0, 15
+0xe6 0x00 0x00 0x0f 0x00 0x5d
+
+# CHECK: vcfn %v0, %v15, 0, 0
+0xe6 0x0f 0x00 0x00 0x00 0x5d
+
+# CHECK: vcfn %v0, %v31, 0, 0
+0xe6 0x0f 0x00 0x00 0x04 0x5d
+
+# CHECK: vcfn %v15, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x00 0x5d
+
+# CHECK: vcfn %v31, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x08 0x5d
+
+# CHECK: vcfn %v14, %v17, 11, 9
+0xe6 0xe1 0x00 0x09 0xb4 0x5d
+
+# CHECK: vclfnl %v0, %v0, 0, 0
+0xe6 0x00 0x00 0x00 0x00 0x5e
+
+# CHECK: vclfnl %v0, %v0, 15, 0
+0xe6 0x00 0x00 0x00 0xf0 0x5e
+
+# CHECK: vclfnl %v0, %v0, 0, 15
+0xe6 0x00 0x00 0x0f 0x00 0x5e
+
+# CHECK: vclfnl %v0, %v15, 0, 0
+0xe6 0x0f 0x00 0x00 0x00 0x5e
+
+# CHECK: vclfnl %v0, %v31, 0, 0
+0xe6 0x0f 0x00 0x00 0x04 0x5e
+
+# CHECK: vclfnl %v15, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x00 0x5e
+
+# CHECK: vclfnl %v31, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x08 0x5e
+
+# CHECK: vclfnl %v14, %v17, 11, 9
+0xe6 0xe1 0x00 0x09 0xb4 0x5e
+
+# CHECK: vclfnh %v0, %v0, 0, 0
+0xe6 0x00 0x00 0x00 0x00 0x56
+
+# CHECK: vclfnh %v0, %v0, 15, 0
+0xe6 0x00 0x00 0x00 0xf0 0x56
+
+# CHECK: vclfnh %v0, %v0, 0, 15
+0xe6 0x00 0x00 0x0f 0x00 0x56
+
+# CHECK: vclfnh %v0, %v15, 0, 0
+0xe6 0x0f 0x00 0x00 0x00 0x56
+
+# CHECK: vclfnh %v0, %v31, 0, 0
+0xe6 0x0f 0x00 0x00 0x04 0x56
+
+# CHECK: vclfnh %v15, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x00 0x56
+
+# CHECK: vclfnh %v31, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x08 0x56
+
+# CHECK: vclfnh %v14, %v17, 11, 9
+0xe6 0xe1 0x00 0x09 0xb4 0x56
+
+# CHECK: vcnf %v0, %v0, 0, 0
+0xe6 0x00 0x00 0x00 0x00 0x55
+
+# CHECK: vcnf %v0, %v0, 15, 0
+0xe6 0x00 0x00 0x00 0xf0 0x55
+
+# CHECK: vcnf %v0, %v0, 0, 15
+0xe6 0x00 0x00 0x0f 0x00 0x55
+
+# CHECK: vcnf %v0, %v15, 0, 0
+0xe6 0x0f 0x00 0x00 0x00 0x55
+
+# CHECK: vcnf %v0, %v31, 0, 0
+0xe6 0x0f 0x00 0x00 0x04 0x55
+
+# CHECK: vcnf %v15, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x00 0x55
+
+# CHECK: vcnf %v31, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x08 0x55
+
+# CHECK: vcnf %v14, %v17, 11, 9
+0xe6 0xe1 0x00 0x09 0xb4 0x55
+
+# CHECK: vcrnf %v0, %v0, %v0, 0, 0
+0xe6 0x00 0x00 0x00 0x00 0x75
+
+# CHECK: vcrnf %v0, %v0, %v0, 15, 0
+0xe6 0x00 0x00 0x00 0xf0 0x75
+
+# CHECK: vcrnf %v0, %v0, %v0, 0, 15
+0xe6 0x00 0x00 0x0f 0x00 0x75
+
+# CHECK: vcrnf %v0, %v0, %v31, 0, 0
+0xe6 0x00 0xf0 0x00 0x02 0x75
+
+# CHECK: vcrnf %v0, %v31, %v0, 0, 0
+0xe6 0x0f 0x00 0x00 0x04 0x75
+
+# CHECK: vcrnf %v31, %v0, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x08 0x75
+
+# CHECK: vcrnf %v18, %v3, %v20, 11, 9
+0xe6 0x23 0x40 0x09 0xba 0x75
+
+# CHECK: vclzdp %v0, %v0, 0
+0xe6 0x00 0x00 0x00 0x00 0x51
+
+# CHECK: vclzdp %v0, %v0, 15
+0xe6 0x00 0x00 0xf0 0x00 0x51
+
+# CHECK: vclzdp %v0, %v15, 0
+0xe6 0x0f 0x00 0x00 0x00 0x51
+
+# CHECK: vclzdp %v0, %v31, 0
+0xe6 0x0f 0x00 0x00 0x04 0x51
+
+# CHECK: vclzdp %v15, %v0, 0
+0xe6 0xf0 0x00 0x00 0x00 0x51
+
+# CHECK: vclzdp %v31, %v0, 0
+0xe6 0xf0 0x00 0x00 0x08 0x51
+
+# CHECK: vclzdp %v18, %v3, 12
+0xe6 0x23 0x00 0xc0 0x08 0x51
+
+# CHECK: vcsph %v0, %v0, %v0, 0
+0xe6 0x00 0x00 0x00 0x00 0x7d
+
+# CHECK: vcsph %v0, %v0, %v0, 15
+0xe6 0x00 0x00 0xf0 0x00 0x7d
+
+# CHECK: vcsph %v0, %v0, %v15, 0
+0xe6 0x00 0xf0 0x00 0x00 0x7d
+
+# CHECK: vcsph %v0, %v0, %v31, 0
+0xe6 0x00 0xf0 0x00 0x02 0x7d
+
+# CHECK: vcsph %v0, %v15, %v0, 0
+0xe6 0x0f 0x00 0x00 0x00 0x7d
+
+# CHECK: vcsph %v0, %v31, %v0, 0
+0xe6 0x0f 0x00 0x00 0x04 0x7d
+
+# CHECK: vcsph %v15, %v0, %v0, 0
+0xe6 0xf0 0x00 0x00 0x00 0x7d
+
+# CHECK: vcsph %v31, %v0, %v0, 0
+0xe6 0xf0 0x00 0x00 0x08 0x7d
+
+# CHECK: vcsph %v18, %v3, %v20, 12
+0xe6 0x23 0x40 0xc0 0x0a 0x7d
+
+# CHECK: vpkzr %v0, %v0, %v0, 0, 0
+0xe6 0x00 0x00 0x00 0x00 0x70
+
+# CHECK: vpkzr %v0, %v0, %v0, 0, 15
+0xe6 0x00 0x00 0xf0 0x00 0x70
+
+# CHECK: vpkzr %v0, %v0, %v0, 255, 0
+0xe6 0x00 0x00 0x0f 0xf0 0x70
+
+# CHECK: vpkzr %v0, %v0, %v31, 0, 0
+0xe6 0x00 0xf0 0x00 0x02 0x70
+
+# CHECK: vpkzr %v0, %v31, %v0, 0, 0
+0xe6 0x0f 0x00 0x00 0x04 0x70
+
+# CHECK: vpkzr %v31, %v0, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x08 0x70
+
+# CHECK: vpkzr %v13, %v17, %v21, 121, 11
+0xe6 0xd1 0x50 0xb7 0x96 0x70
+
+# CHECK: vschp %v0, %v0, %v0, 0, 0
+0xe6 0x00 0x00 0x00 0x00 0x74
+
+# CHECK: vschp %v0, %v0, %v0, 15, 0
+0xe6 0x00 0x00 0x00 0xf0 0x74
+
+# CHECK: vschp %v0, %v0, %v0, 0, 0
+0xe6 0x00 0x00 0x00 0x00 0x74
+
+# CHECK: vschp %v0, %v0, %v0, 15, 0
+0xe6 0x00 0x00 0x00 0xf0 0x74
+
+# CHECK: vschp %v0, %v0, %v0, 0, 12
+0xe6 0x00 0x00 0xc0 0x00 0x74
+
+# CHECK: vschp %v0, %v0, %v15, 0, 0
+0xe6 0x00 0xf0 0x00 0x00 0x74
+
+# CHECK: vschp %v0, %v0, %v31, 0, 0
+0xe6 0x00 0xf0 0x00 0x02 0x74
+
+# CHECK: vschp %v0, %v15, %v0, 0, 0
+0xe6 0x0f 0x00 0x00 0x00 0x74
+
+# CHECK: vschp %v0, %v31, %v0, 0, 0
+0xe6 0x0f 0x00 0x00 0x04 0x74
+
+# CHECK: vschp %v15, %v0, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x00 0x74
+
+# CHECK: vschp %v31, %v0, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x08 0x74
+
+# CHECK: vschp %v18, %v3, %v20, 11, 4
+0xe6 0x23 0x40 0x40 0xba 0x74
+
+# CHECK: vschp %v18, %v3, %v20, 0, 15
+0xe6 0x23 0x40 0xf0 0x0a 0x74
+
+# CHECK: vschsp %v0, %v0, %v0, 0
+0xe6 0x00 0x00 0x00 0x20 0x74
+
+# CHECK: vschsp %v0, %v0, %v0, 0
+0xe6 0x00 0x00 0x00 0x20 0x74
+
+# CHECK: vschsp %v0, %v0, %v0, 12
+0xe6 0x00 0x00 0xc0 0x20 0x74
+
+# CHECK: vschsp %v0, %v0, %v15, 0
+0xe6 0x00 0xf0 0x00 0x20 0x74
+
+# CHECK: vschsp %v0, %v0, %v31, 0
+0xe6 0x00 0xf0 0x00 0x22 0x74
+
+# CHECK: vschsp %v0, %v15, %v0, 0
+0xe6 0x0f 0x00 0x00 0x20 0x74
+
+# CHECK: vschsp %v0, %v31, %v0, 0
+0xe6 0x0f 0x00 0x00 0x24 0x74
+
+# CHECK: vschsp %v15, %v0, %v0, 0
+0xe6 0xf0 0x00 0x00 0x20 0x74
+
+# CHECK: vschsp %v31, %v0, %v0, 0
+0xe6 0xf0 0x00 0x00 0x28 0x74
+
+# CHECK: vschsp %v18, %v3, %v20, 0
+0xe6 0x23 0x40 0x00 0x2a 0x74
+
+# CHECK: vschdp %v0, %v0, %v0, 0
+0xe6 0x00 0x00 0x00 0x30 0x74
+
+# CHECK: vschdp %v0, %v0, %v0, 0
+0xe6 0x00 0x00 0x00 0x30 0x74
+
+# CHECK: vschdp %v0, %v0, %v0, 12
+0xe6 0x00 0x00 0xc0 0x30 0x74
+
+# CHECK: vschdp %v0, %v0, %v15, 0
+0xe6 0x00 0xf0 0x00 0x30 0x74
+
+# CHECK: vschdp %v0, %v0, %v31, 0
+0xe6 0x00 0xf0 0x00 0x32 0x74
+
+# CHECK: vschdp %v0, %v15, %v0, 0
+0xe6 0x0f 0x00 0x00 0x30 0x74
+
+# CHECK: vschdp %v0, %v31, %v0, 0
+0xe6 0x0f 0x00 0x00 0x34 0x74
+
+# CHECK: vschdp %v15, %v0, %v0, 0
+0xe6 0xf0 0x00 0x00 0x30 0x74
+
+# CHECK: vschdp %v31, %v0, %v0, 0
+0xe6 0xf0 0x00 0x00 0x38 0x74
+
+# CHECK: vschdp %v18, %v3, %v20, 0
+0xe6 0x23 0x40 0x00 0x3a 0x74
+
+# CHECK: vschxp %v0, %v0, %v0, 0
+0xe6 0x00 0x00 0x00 0x40 0x74
+
+# CHECK: vschxp %v0, %v0, %v0, 0
+0xe6 0x00 0x00 0x00 0x40 0x74
+
+# CHECK: vschxp %v0, %v0, %v0, 12
+0xe6 0x00 0x00 0xc0 0x40 0x74
+
+# CHECK: vschxp %v0, %v0, %v15, 0
+0xe6 0x00 0xf0 0x00 0x40 0x74
+
+# CHECK: vschxp %v0, %v0, %v31, 0
+0xe6 0x00 0xf0 0x00 0x42 0x74
+
+# CHECK: vschxp %v0, %v15, %v0, 0
+0xe6 0x0f 0x00 0x00 0x40 0x74
+
+# CHECK: vschxp %v0, %v31, %v0, 0
+0xe6 0x0f 0x00 0x00 0x44 0x74
+
+# CHECK: vschxp %v15, %v0, %v0, 0
+0xe6 0xf0 0x00 0x00 0x40 0x74
+
+# CHECK: vschxp %v31, %v0, %v0, 0
+0xe6 0xf0 0x00 0x00 0x48 0x74
+
+# CHECK: vschxp %v18, %v3, %v20, 0
+0xe6 0x23 0x40 0x00 0x4a 0x74
+
+# CHECK: vscshp %v0, %v0, %v0
+0xe6 0x00 0x00 0x00 0x00 0x7c
+
+# CHECK: vscshp %v0, %v0, %v31
+0xe6 0x00 0xf0 0x00 0x02 0x7c
+
+# CHECK: vscshp %v0, %v31, %v0
+0xe6 0x0f 0x00 0x00 0x04 0x7c
+
+# CHECK: vscshp %v31, %v0, %v0
+0xe6 0xf0 0x00 0x00 0x08 0x7c
+
+# CHECK: vscshp %v18, %v3, %v20
+0xe6 0x23 0x40 0x00 0x0a 0x7c
+
+# CHECK: vsrpr %v0, %v0, %v0, 0, 0
+0xe6 0x00 0x00 0x00 0x00 0x72
+
+# CHECK: vsrpr %v0, %v0, %v0, 0, 15
+0xe6 0x00 0x00 0xf0 0x00 0x72
+
+# CHECK: vsrpr %v0, %v0, %v0, 255, 0
+0xe6 0x00 0x00 0x0f 0xf0 0x72
+
+# CHECK: vsrpr %v0, %v0, %v31, 0, 0
+0xe6 0x00 0xf0 0x00 0x02 0x72
+
+# CHECK: vsrpr %v0, %v31, %v0, 0, 0
+0xe6 0x0f 0x00 0x00 0x04 0x72
+
+# CHECK: vsrpr %v31, %v0, %v0, 0, 0
+0xe6 0xf0 0x00 0x00 0x08 0x72
+
+# CHECK: vsrpr %v13, %v17, %v21, 121, 11
+0xe6 0xd1 0x50 0xb7 0x96 0x72
+
+# CHECK: vupkzh %v0, %v0, 0
+0xe6 0x00 0x00 0x00 0x00 0x54
+
+# CHECK: vupkzh %v0, %v0, 15
+0xe6 0x00 0x00 0xf0 0x00 0x54
+
+# CHECK: vupkzh %v0, %v15, 0
+0xe6 0x0f 0x00 0x00 0x00 0x54
+
+# CHECK: vupkzh %v0, %v31, 0
+0xe6 0x0f 0x00 0x00 0x04 0x54
+
+# CHECK: vupkzh %v15, %v0, 0
+0xe6 0xf0 0x00 0x00 0x00 0x54
+
+# CHECK: vupkzh %v31, %v0, 0
+0xe6 0xf0 0x00 0x00 0x08 0x54
+
+# CHECK: vupkzh %v18, %v3, 12
+0xe6 0x23 0x00 0xc0 0x08 0x54
+
+# CHECK: vupkzl %v0, %v0, 0
+0xe6 0x00 0x00 0x00 0x00 0x5c
+
+# CHECK: vupkzl %v0, %v0, 15
+0xe6 0x00 0x00 0xf0 0x00 0x5c
+
+# CHECK: vupkzl %v0, %v15, 0
+0xe6 0x0f 0x00 0x00 0x00 0x5c
+
+# CHECK: vupkzl %v0, %v31, 0
+0xe6 0x0f 0x00 0x00 0x04 0x5c
+
+# CHECK: vupkzl %v15, %v0, 0
+0xe6 0xf0 0x00 0x00 0x00 0x5c
+
+# CHECK: vupkzl %v31, %v0, 0
+0xe6 0xf0 0x00 0x00 0x08 0x5c
+
+# CHECK: vupkzl %v18, %v3, 12
+0xe6 0x23 0x00 0xc0 0x08 0x5c
+
diff --git a/test/MC/SystemZ/insn-bad-arch14.s b/test/MC/SystemZ/insn-bad-arch14.s
new file mode 100644
index 00000000000..712f16faec7
--- /dev/null
+++ b/test/MC/SystemZ/insn-bad-arch14.s
@@ -0,0 +1,223 @@
+# For arch14 only.
+# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=arch14 < %s 2> %t
+# RUN: FileCheck < %t %s
+
+#CHECK: error: invalid operand
+#CHECK: lbear	-1
+#CHECK: error: invalid operand
+#CHECK: lbear	4096
+#CHECK: error: invalid use of indexed addressing
+#CHECK: lbear	0(%r1,%r2)
+
+	lbear	-1
+	lbear	4096
+	lbear	0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: lpswey	-524289
+#CHECK: error: invalid operand
+#CHECK: lpswey	524288
+#CHECK: error: invalid use of indexed addressing
+#CHECK: lpswey	0(%r1,%r2)
+
+	lpswey	-524289
+	lpswey	524288
+	lpswey	0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: qpaci	-1
+#CHECK: error: invalid operand
+#CHECK: qpaci	4096
+#CHECK: error: invalid use of indexed addressing
+#CHECK: qpaci	0(%r1,%r2)
+
+	qpaci	-1
+	qpaci	4096
+	qpaci	0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: rdp	%r0, %r0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: rdp	%r0, %r0, %r0, 16
+
+	rdp	%r0, %r0, %r0, -1
+	rdp	%r0, %r0, %r0, 16
+
+#CHECK: error: invalid operand
+#CHECK: stbear	-1
+#CHECK: error: invalid operand
+#CHECK: stbear	4096
+#CHECK: error: invalid use of indexed addressing
+#CHECK: stbear	0(%r1,%r2)
+
+	stbear	-1
+	stbear	4096
+	stbear	0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: vcfn	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vcfn	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vcfn	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vcfn	%v0, %v0, 16, 0
+
+	vcfn	%v0, %v0, 0, -1
+	vcfn	%v0, %v0, 0, 16
+	vcfn	%v0, %v0, -1, 0
+	vcfn	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: vclfnl	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vclfnl	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vclfnl	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vclfnl	%v0, %v0, 16, 0
+
+	vclfnl	%v0, %v0, 0, -1
+	vclfnl	%v0, %v0, 0, 16
+	vclfnl	%v0, %v0, -1, 0
+	vclfnl	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: vclfnh	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vclfnh	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vclfnh	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vclfnh	%v0, %v0, 16, 0
+
+	vclfnh	%v0, %v0, 0, -1
+	vclfnh	%v0, %v0, 0, 16
+	vclfnh	%v0, %v0, -1, 0
+	vclfnh	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: vcnf	%v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vcnf	%v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vcnf	%v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vcnf	%v0, %v0, 16, 0
+
+	vcnf	%v0, %v0, 0, -1
+	vcnf	%v0, %v0, 0, 16
+	vcnf	%v0, %v0, -1, 0
+	vcnf	%v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: vcrnf	%v0, %v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vcrnf	%v0, %v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vcrnf	%v0, %v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vcrnf	%v0, %v0, %v0, 16, 0
+
+	vcrnf	%v0, %v0, %v0, 0, -1
+	vcrnf	%v0, %v0, %v0, 0, 16
+	vcrnf	%v0, %v0, %v0, -1, 0
+	vcrnf	%v0, %v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: vclzdp	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vclzdp	%v0, %v0, 16
+
+	vclzdp	%v0, %v0, -1
+	vclzdp	%v0, %v0, 16
+
+#CHECK: error: invalid operand
+#CHECK: vcsph	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vcsph	%v0, %v0, %v0, 16
+
+	vcsph	%v0, %v0, %v0, -1
+	vcsph	%v0, %v0, %v0, 16
+
+#CHECK: error: invalid operand
+#CHECK: vpkzr	%v0, %v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vpkzr	%v0, %v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vpkzr	%v0, %v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vpkzr	%v0, %v0, %v0, 256, 0
+
+	vpkzr	%v0, %v0, %v0, 0, -1
+	vpkzr	%v0, %v0, %v0, 0, 16
+	vpkzr	%v0, %v0, %v0, -1, 0
+	vpkzr	%v0, %v0, %v0, 256, 0
+
+#CHECK: error: invalid operand
+#CHECK: vschp	%v0, %v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vschp	%v0, %v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vschp	%v0, %v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vschp	%v0, %v0, %v0, 16, 0
+
+	vschp	%v0, %v0, %v0, 0, -1
+	vschp	%v0, %v0, %v0, 0, 16
+	vschp	%v0, %v0, %v0, -1, 0
+	vschp	%v0, %v0, %v0, 16, 0
+
+#CHECK: error: invalid operand
+#CHECK: vschsp	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vschsp	%v0, %v0, %v0, 16
+
+	vschsp	%v0, %v0, %v0, -1
+	vschsp	%v0, %v0, %v0, 16
+
+#CHECK: error: invalid operand
+#CHECK: vschdp	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vschdp	%v0, %v0, %v0, 16
+
+	vschdp	%v0, %v0, %v0, -1
+	vschdp	%v0, %v0, %v0, 16
+
+#CHECK: error: invalid operand
+#CHECK: vschxp	%v0, %v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vschxp	%v0, %v0, %v0, 16
+
+	vschxp	%v0, %v0, %v0, -1
+	vschxp	%v0, %v0, %v0, 16
+
+#CHECK: error: invalid operand
+#CHECK: vsrpr	%v0, %v0, %v0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: vsrpr	%v0, %v0, %v0, 0, 16
+#CHECK: error: invalid operand
+#CHECK: vsrpr	%v0, %v0, %v0, -1, 0
+#CHECK: error: invalid operand
+#CHECK: vsrpr	%v0, %v0, %v0, 256, 0
+
+	vsrpr	%v0, %v0, %v0, 0, -1
+	vsrpr	%v0, %v0, %v0, 0, 16
+	vsrpr	%v0, %v0, %v0, -1, 0
+	vsrpr	%v0, %v0, %v0, 256, 0
+
+#CHECK: error: invalid operand
+#CHECK: vupkzh	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vupkzh	%v0, %v0, 16
+
+	vupkzh	%v0, %v0, -1
+	vupkzh	%v0, %v0, 16
+
+#CHECK: error: invalid operand
+#CHECK: vupkzl	%v0, %v0, -1
+#CHECK: error: invalid operand
+#CHECK: vupkzl	%v0, %v0, 16
+
+	vupkzl	%v0, %v0, -1
+	vupkzl	%v0, %v0, 16
diff --git a/test/MC/SystemZ/insn-bad-z15.s b/test/MC/SystemZ/insn-bad-z15.s
index 484dfd342da..b6b2d3787f5 100644
--- a/test/MC/SystemZ/insn-bad-z15.s
+++ b/test/MC/SystemZ/insn-bad-z15.s
@@ -17,6 +17,11 @@
 
 	kdsa	%r0, %r1
 
+#CHECK: error: instruction requires: bear-enhancement
+#CHECK: lbear	0
+
+	lbear	0
+
 #CHECK: error: invalid operand
 #CHECK: ldrv	%f0, -1
 #CHECK: error: invalid operand
@@ -39,6 +44,11 @@
 	lerv	%f0, 4096
 	lerv	%f0, 0(%v1,%r2)
 
+#CHECK: error: instruction requires: bear-enhancement
+#CHECK: lpswey	0
+
+	lpswey	0
+
 #CHECK: error: invalid use of indexed addressing
 #CHECK: mvcrl	160(%r1,%r15),160(%r15)
 #CHECK: error: invalid operand
@@ -56,6 +66,11 @@
         mvcrl	0(%r1),-1(%r15)
         mvcrl	0(%r1),4096(%r15)
 
+#CHECK: error: instruction requires: nnp-assist
+#CHECK: nnpa
+
+	nnpa
+
 #CHECK: error: invalid operand
 #CHECK: popcnt	%r2, %r4, -1
 #CHECK: error: invalid operand
@@ -64,6 +79,16 @@
 	popcnt	%r2, %r4, -1
 	popcnt	%r2, %r4, 16
 
+#CHECK: error: instruction requires: processor-activity-instrumentation
+#CHECK: qpaci	0
+
+	qpaci	0
+
+#CHECK: error: instruction requires: reset-dat-protection
+#CHECK: rdp	%r0, %r0, %r0
+
+	rdp	%r0, %r0, %r0
+
 #CHECK: error: invalid operand
 #CHECK: selgr	%r0, %r0, %r0, -1
 #CHECK: error: invalid operand
@@ -96,6 +121,11 @@
 	sortl	%r1, %r2
 	sortl	%r2, %r1
 
+#CHECK: error: instruction requires: bear-enhancement
+#CHECK: stbear	0
+
+	stbear	0
+
 #CHECK: error: invalid operand
 #CHECK: stdrv	%f0, -1
 #CHECK: error: invalid operand
@@ -200,6 +230,11 @@
 	vcfps	%v0, %v0, -1, 0, 0
 	vcfps	%v0, %v0, 16, 0, 0
 
+#CHECK: error: instruction requires: nnp-assist
+#CHECK: vcfn	%v0, %v0, 0, 0
+
+	vcfn	%v0, %v0, 0, 0
+
 #CHECK: error: invalid operand
 #CHECK: vclfeb	%v0, %v0, 0, -1
 #CHECK: error: invalid operand
@@ -234,6 +269,31 @@
 	vclfp	%v0, %v0, -1, 0, 0
 	vclfp	%v0, %v0, 16, 0, 0
 
+#CHECK: error: instruction requires: nnp-assist
+#CHECK: vclfnl	%v0, %v0, 0, 0
+
+	vclfnl	%v0, %v0, 0, 0
+
+#CHECK: error: instruction requires: nnp-assist
+#CHECK: vclfnh	%v0, %v0, 0, 0
+
+	vclfnh	%v0, %v0, 0, 0
+
+#CHECK: error: instruction requires: vector-packed-decimal-enhancement-2
+#CHECK: vclzdp	%v0, %v0, 0
+
+	vclzdp	%v0, %v0, 0
+
+#CHECK: error: instruction requires: nnp-assist
+#CHECK: vcnf	%v0, %v0, 0, 0
+
+	vcnf	%v0, %v0, 0, 0
+
+#CHECK: error: instruction requires: nnp-assist
+#CHECK: vcrnf	%v0, %v0, %v0, 0, 0
+
+	vcrnf	%v0, %v0, %v0, 0, 0
+
 #CHECK: error: invalid operand
 #CHECK: vcsfp	%v0, %v0, 0, 0, -1
 #CHECK: error: invalid operand
@@ -254,6 +314,36 @@
 	vcsfp	%v0, %v0, -1, 0, 0
 	vcsfp	%v0, %v0, 16, 0, 0
 
+#CHECK: error: instruction requires: vector-packed-decimal-enhancement-2
+#CHECK: vschp	%v0, %v0, %v0, 0, 0
+
+	vschp	%v0, %v0, %v0, 0, 0
+
+#CHECK: error: instruction requires: vector-packed-decimal-enhancement-2
+#CHECK: vschsp	%v0, %v0, %v0, 0
+
+	vschsp	%v0, %v0, %v0, 0
+
+#CHECK: error: instruction requires: vector-packed-decimal-enhancement-2
+#CHECK: vschdp	%v0, %v0, %v0, 0
+
+	vschdp	%v0, %v0, %v0, 0
+
+#CHECK: error: instruction requires: vector-packed-decimal-enhancement-2
+#CHECK: vschxp	%v0, %v0, %v0, 0
+
+	vschxp	%v0, %v0, %v0, 0
+
+#CHECK: error: instruction requires: vector-packed-decimal-enhancement-2
+#CHECK: vcsph	%v0, %v0, %v0, 0
+
+	vcsph	%v0, %v0, %v0, 0
+
+#CHECK: error: instruction requires: vector-packed-decimal-enhancement-2
+#CHECK: vscshp	%v0, %v0, %v0
+
+	vscshp	%v0, %v0, %v0
+
 #CHECK: error: invalid operand
 #CHECK: vcvb	%r0, %v0, 0, -1
 #CHECK: error: invalid operand
@@ -543,6 +633,11 @@
 	vllebrzh	%v0, 4096
 	vllebrzh	%v0, 0(%v1,%r2)
 
+#CHECK: error: instruction requires: vector-packed-decimal-enhancement-2
+#CHECK: vpkzr	%v0, %v0, %v0, 0, 0
+
+	vpkzr	%v0, %v0, %v0, 0, 0
+
 #CHECK: error: invalid operand
 #CHECK: vsld	%v0, %v0, %v0, -1
 #CHECK: error: invalid operand
@@ -559,6 +654,11 @@
 	vsrd	%v0, %v0, %v0, -1
 	vsrd	%v0, %v0, %v0, 256
 
+#CHECK: error: instruction requires: vector-packed-decimal-enhancement-2
+#CHECK: vsrpr	%v0, %v0, %v0, 0, 0
+
+	vsrpr	%v0, %v0, %v0, 0, 0
+
 #CHECK: error: invalid operand
 #CHECK: vstbr	%v0, 0, -1
 #CHECK: error: invalid operand
@@ -825,6 +925,16 @@
 	vstrszh  %v0, %v0, %v0
 	vstrszh  %v0, %v0, %v0, %v0, 0, 0
 
+#CHECK: error: instruction requires: vector-packed-decimal-enhancement-2
+#CHECK: vupkzh	%v0, %v0, 0
+
+	vupkzh	%v0, %v0, 0
+
+#CHECK: error: instruction requires: vector-packed-decimal-enhancement-2
+#CHECK: vupkzl	%v0, %v0, 0
+
+	vupkzl	%v0, %v0, 0
+
 #CHECK: error: invalid operand
 #CHECK: wcefb	%v0, %v0, 0, -1
 #CHECK: error: invalid operand
diff --git a/test/MC/SystemZ/insn-good-arch14.s b/test/MC/SystemZ/insn-good-arch14.s
new file mode 100644
index 00000000000..2cc666950ec
--- /dev/null
+++ b/test/MC/SystemZ/insn-good-arch14.s
@@ -0,0 +1,377 @@
+# For arch14 and above.
+# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch14 -show-encoding %s \
+# RUN:   | FileCheck %s
+
+#CHECK: lbear	0                       # encoding: [0xb2,0x00,0x00,0x00]
+#CHECK: lbear	0(%r1)                  # encoding: [0xb2,0x00,0x10,0x00]
+#CHECK: lbear	0(%r15)                 # encoding: [0xb2,0x00,0xf0,0x00]
+#CHECK: lbear	4095                    # encoding: [0xb2,0x00,0x0f,0xff]
+#CHECK: lbear	4095(%r1)               # encoding: [0xb2,0x00,0x1f,0xff]
+#CHECK: lbear	4095(%r15)              # encoding: [0xb2,0x00,0xff,0xff]
+
+	lbear	0
+	lbear	0(%r1)
+	lbear	0(%r15)
+	lbear	4095
+	lbear	4095(%r1)
+	lbear	4095(%r15)
+
+#CHECK: lpswey	-524288                 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x71]
+#CHECK: lpswey	-1                      # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x71]
+#CHECK: lpswey	0                       # encoding: [0xeb,0x00,0x00,0x00,0x00,0x71]
+#CHECK: lpswey	1                       # encoding: [0xeb,0x00,0x00,0x01,0x00,0x71]
+#CHECK: lpswey	524287                  # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x71]
+#CHECK: lpswey	0(%r1)                  # encoding: [0xeb,0x00,0x10,0x00,0x00,0x71]
+#CHECK: lpswey	0(%r15)                 # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x71]
+#CHECK: lpswey	524287(%r1)             # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x71]
+#CHECK: lpswey	524287(%r15)            # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x71]
+
+	lpswey	-524288
+	lpswey	-1
+	lpswey	0
+	lpswey	1
+	lpswey	524287
+	lpswey	0(%r1)
+	lpswey	0(%r15)
+	lpswey	524287(%r1)
+	lpswey	524287(%r15)
+
+#CHECK: nnpa                            # encoding: [0xb9,0x3b,0x00,0x00]
+
+	nnpa
+
+#CHECK: qpaci	0                  	# encoding: [0xb2,0x8f,0x00,0x00]
+#CHECK: qpaci	0(%r1)             	# encoding: [0xb2,0x8f,0x10,0x00]
+#CHECK: qpaci	0(%r15)            	# encoding: [0xb2,0x8f,0xf0,0x00]
+#CHECK: qpaci	4095                 	# encoding: [0xb2,0x8f,0x0f,0xff]
+#CHECK: qpaci	4095(%r1)             	# encoding: [0xb2,0x8f,0x1f,0xff]
+#CHECK: qpaci	4095(%r15)             	# encoding: [0xb2,0x8f,0xff,0xff]
+
+	qpaci	0
+	qpaci	0(%r1)
+	qpaci	0(%r15)
+	qpaci	4095
+	qpaci	4095(%r1)
+	qpaci	4095(%r15)
+
+#CHECK: rdp	%r0, %r0, %r0           # encoding: [0xb9,0x8b,0x00,0x00]
+#CHECK: rdp	%r0, %r0, %r15          # encoding: [0xb9,0x8b,0x00,0x0f]
+#CHECK: rdp	%r0, %r15, %r0          # encoding: [0xb9,0x8b,0xf0,0x00]
+#CHECK: rdp	%r15, %r0, %r0          # encoding: [0xb9,0x8b,0x00,0xf0]
+#CHECK: rdp	%r0, %r0, %r0, 15       # encoding: [0xb9,0x8b,0x0f,0x00]
+#CHECK: rdp	%r4, %r5, %r6, 7        # encoding: [0xb9,0x8b,0x57,0x46]
+
+	rdp	%r0, %r0, %r0
+	rdp	%r0, %r0, %r15
+	rdp	%r0, %r15, %r0
+	rdp	%r15, %r0, %r0
+	rdp	%r0, %r0, %r0, 15
+	rdp	%r4, %r5, %r6, 7
+
+#CHECK: stbear	0                       # encoding: [0xb2,0x01,0x00,0x00]
+#CHECK: stbear	0(%r1)                  # encoding: [0xb2,0x01,0x10,0x00]
+#CHECK: stbear	0(%r15)                 # encoding: [0xb2,0x01,0xf0,0x00]
+#CHECK: stbear	4095                    # encoding: [0xb2,0x01,0x0f,0xff]
+#CHECK: stbear	4095(%r1)               # encoding: [0xb2,0x01,0x1f,0xff]
+#CHECK: stbear	4095(%r15)              # encoding: [0xb2,0x01,0xff,0xff]
+
+	stbear	0
+	stbear	0(%r1)
+	stbear	0(%r15)
+	stbear	4095
+	stbear	4095(%r1)
+	stbear	4095(%r15)
+
+#CHECK: vcfn	%v0, %v0, 0, 0          # encoding: [0xe6,0x00,0x00,0x00,0x00,0x5d]
+#CHECK: vcfn	%v0, %v0, 15, 0         # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x5d]
+#CHECK: vcfn	%v0, %v0, 0, 15         # encoding: [0xe6,0x00,0x00,0x0f,0x00,0x5d]
+#CHECK: vcfn	%v0, %v15, 0, 0         # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x5d]
+#CHECK: vcfn	%v0, %v31, 0, 0         # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x5d]
+#CHECK: vcfn	%v15, %v0, 0, 0         # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x5d]
+#CHECK: vcfn	%v31, %v0, 0, 0         # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x5d]
+#CHECK: vcfn	%v14, %v17, 11, 9       # encoding: [0xe6,0xe1,0x00,0x09,0xb4,0x5d]
+
+	vcfn	%v0, %v0, 0, 0
+	vcfn	%v0, %v0, 15, 0
+	vcfn	%v0, %v0, 0, 15
+	vcfn	%v0, %v15, 0, 0
+	vcfn	%v0, %v31, 0, 0
+	vcfn	%v15, %v0, 0, 0
+	vcfn	%v31, %v0, 0, 0
+	vcfn	%v14, %v17, 11, 9
+
+#CHECK: vclfnl	%v0, %v0, 0, 0          # encoding: [0xe6,0x00,0x00,0x00,0x00,0x5e]
+#CHECK: vclfnl	%v0, %v0, 15, 0         # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x5e]
+#CHECK: vclfnl	%v0, %v0, 0, 15         # encoding: [0xe6,0x00,0x00,0x0f,0x00,0x5e]
+#CHECK: vclfnl	%v0, %v15, 0, 0         # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x5e]
+#CHECK: vclfnl	%v0, %v31, 0, 0         # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x5e]
+#CHECK: vclfnl	%v15, %v0, 0, 0         # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x5e]
+#CHECK: vclfnl	%v31, %v0, 0, 0         # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x5e]
+#CHECK: vclfnl	%v14, %v17, 11, 9       # encoding: [0xe6,0xe1,0x00,0x09,0xb4,0x5e]
+
+	vclfnl	%v0, %v0, 0, 0
+	vclfnl	%v0, %v0, 15, 0
+	vclfnl	%v0, %v0, 0, 15
+	vclfnl	%v0, %v15, 0, 0
+	vclfnl	%v0, %v31, 0, 0
+	vclfnl	%v15, %v0, 0, 0
+	vclfnl	%v31, %v0, 0, 0
+	vclfnl	%v14, %v17, 11, 9
+
+#CHECK: vclfnh	%v0, %v0, 0, 0          # encoding: [0xe6,0x00,0x00,0x00,0x00,0x56]
+#CHECK: vclfnh	%v0, %v0, 15, 0         # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x56]
+#CHECK: vclfnh	%v0, %v0, 0, 15         # encoding: [0xe6,0x00,0x00,0x0f,0x00,0x56]
+#CHECK: vclfnh	%v0, %v15, 0, 0         # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x56]
+#CHECK: vclfnh	%v0, %v31, 0, 0         # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x56]
+#CHECK: vclfnh	%v15, %v0, 0, 0         # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x56]
+#CHECK: vclfnh	%v31, %v0, 0, 0         # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x56]
+#CHECK: vclfnh	%v14, %v17, 11, 9       # encoding: [0xe6,0xe1,0x00,0x09,0xb4,0x56]
+
+	vclfnh	%v0, %v0, 0, 0
+	vclfnh	%v0, %v0, 15, 0
+	vclfnh	%v0, %v0, 0, 15
+	vclfnh	%v0, %v15, 0, 0
+	vclfnh	%v0, %v31, 0, 0
+	vclfnh	%v15, %v0, 0, 0
+	vclfnh	%v31, %v0, 0, 0
+	vclfnh	%v14, %v17, 11, 9
+
+#CHECK: vcnf	%v0, %v0, 0, 0          # encoding: [0xe6,0x00,0x00,0x00,0x00,0x55]
+#CHECK: vcnf	%v0, %v0, 15, 0         # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x55]
+#CHECK: vcnf	%v0, %v0, 0, 15         # encoding: [0xe6,0x00,0x00,0x0f,0x00,0x55]
+#CHECK: vcnf	%v0, %v15, 0, 0         # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x55]
+#CHECK: vcnf	%v0, %v31, 0, 0         # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x55]
+#CHECK: vcnf	%v15, %v0, 0, 0         # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x55]
+#CHECK: vcnf	%v31, %v0, 0, 0         # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x55]
+#CHECK: vcnf	%v14, %v17, 11, 9       # encoding: [0xe6,0xe1,0x00,0x09,0xb4,0x55]
+
+	vcnf	%v0, %v0, 0, 0
+	vcnf	%v0, %v0, 15, 0
+	vcnf	%v0, %v0, 0, 15
+	vcnf	%v0, %v15, 0, 0
+	vcnf	%v0, %v31, 0, 0
+	vcnf	%v15, %v0, 0, 0
+	vcnf	%v31, %v0, 0, 0
+	vcnf	%v14, %v17, 11, 9
+
+#CHECK: vcrnf	%v0, %v0, %v0, 0, 0     # encoding: [0xe6,0x00,0x00,0x00,0x00,0x75]
+#CHECK: vcrnf	%v0, %v0, %v0, 15, 0    # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x75]
+#CHECK: vcrnf	%v0, %v0, %v0, 0, 15    # encoding: [0xe6,0x00,0x00,0x0f,0x00,0x75]
+#CHECK: vcrnf	%v0, %v0, %v31, 0, 0    # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x75]
+#CHECK: vcrnf	%v0, %v31, %v0, 0, 0    # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x75]
+#CHECK: vcrnf	%v31, %v0, %v0, 0, 0    # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x75]
+#CHECK: vcrnf	%v18, %v3, %v20, 11, 9  # encoding: [0xe6,0x23,0x40,0x09,0xba,0x75]
+
+	vcrnf	%v0, %v0, %v0, 0, 0
+	vcrnf	%v0, %v0, %v0, 15, 0
+	vcrnf	%v0, %v0, %v0, 0, 15
+	vcrnf	%v0, %v0, %v31, 0, 0
+	vcrnf	%v0, %v31, %v0, 0, 0
+	vcrnf	%v31, %v0, %v0, 0, 0
+	vcrnf	%v18, %v3, %v20, 11, 9
+
+#CHECK: vclzdp	%v0, %v0, 0             # encoding: [0xe6,0x00,0x00,0x00,0x00,0x51]
+#CHECK: vclzdp	%v0, %v0, 15            # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x51]
+#CHECK: vclzdp	%v0, %v15, 0            # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x51]
+#CHECK: vclzdp	%v0, %v31, 0            # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x51]
+#CHECK: vclzdp	%v15, %v0, 0            # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x51]
+#CHECK: vclzdp	%v31, %v0, 0            # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x51]
+#CHECK: vclzdp	%v18, %v3, 12           # encoding: [0xe6,0x23,0x00,0xc0,0x08,0x51]
+
+	vclzdp	%v0, %v0, 0
+	vclzdp	%v0, %v0, 15
+	vclzdp	%v0, %v15, 0
+	vclzdp	%v0, %v31, 0
+	vclzdp	%v15, %v0, 0
+	vclzdp	%v31, %v0, 0
+	vclzdp	%v18, %v3, 12
+
+#CHECK: vcsph	%v0, %v0, %v0, 0        # encoding: [0xe6,0x00,0x00,0x00,0x00,0x7d]
+#CHECK: vcsph	%v0, %v0, %v0, 15       # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x7d]
+#CHECK: vcsph	%v0, %v0, %v15, 0       # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x7d]
+#CHECK: vcsph	%v0, %v0, %v31, 0       # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x7d]
+#CHECK: vcsph	%v0, %v15, %v0, 0       # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x7d]
+#CHECK: vcsph	%v0, %v31, %v0, 0       # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x7d]
+#CHECK: vcsph	%v15, %v0, %v0, 0       # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x7d]
+#CHECK: vcsph	%v31, %v0, %v0, 0       # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x7d]
+#CHECK: vcsph	%v18, %v3, %v20, 12     # encoding: [0xe6,0x23,0x40,0xc0,0x0a,0x7d]
+
+	vcsph	%v0, %v0, %v0, 0
+	vcsph	%v0, %v0, %v0, 15
+	vcsph	%v0, %v0, %v15, 0
+	vcsph	%v0, %v0, %v31, 0
+	vcsph	%v0, %v15, %v0, 0
+	vcsph	%v0, %v31, %v0, 0
+	vcsph	%v15, %v0, %v0, 0
+	vcsph	%v31, %v0, %v0, 0
+	vcsph	%v18, %v3, %v20, 12
+
+#CHECK: vpkzr	%v0, %v0, %v0, 0, 0     # encoding: [0xe6,0x00,0x00,0x00,0x00,0x70]
+#CHECK: vpkzr	%v0, %v0, %v0, 0, 15    # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x70]
+#CHECK: vpkzr	%v0, %v0, %v0, 255, 0   # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x70]
+#CHECK: vpkzr	%v0, %v0, %v31, 0, 0    # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x70]
+#CHECK: vpkzr	%v0, %v31, %v0, 0, 0    # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x70]
+#CHECK: vpkzr	%v31, %v0, %v0, 0, 0    # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x70]
+#CHECK: vpkzr	%v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x70]
+
+	vpkzr	%v0, %v0, %v0, 0, 0
+	vpkzr	%v0, %v0, %v0, 0, 15
+	vpkzr	%v0, %v0, %v0, 255, 0
+	vpkzr	%v0, %v0, %v31, 0, 0
+	vpkzr	%v0, %v31, %v0, 0, 0
+	vpkzr	%v31, %v0, %v0, 0, 0
+	vpkzr	%v13, %v17, %v21, 0x79, 11
+
+#CHECK: vschp	%v0, %v0, %v0, 0, 0     # encoding: [0xe6,0x00,0x00,0x00,0x00,0x74]
+#CHECK: vschp	%v0, %v0, %v0, 15, 0    # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x74]
+#CHECK: vschp	%v0, %v0, %v0, 0, 0     # encoding: [0xe6,0x00,0x00,0x00,0x00,0x74]
+#CHECK: vschp	%v0, %v0, %v0, 15, 0    # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x74]
+#CHECK: vschp	%v0, %v0, %v0, 0, 12    # encoding: [0xe6,0x00,0x00,0xc0,0x00,0x74]
+#CHECK: vschp	%v0, %v0, %v15, 0, 0    # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x74]
+#CHECK: vschp	%v0, %v0, %v31, 0, 0    # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x74]
+#CHECK: vschp	%v0, %v15, %v0, 0, 0    # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x74]
+#CHECK: vschp	%v0, %v31, %v0, 0, 0    # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x74]
+#CHECK: vschp	%v15, %v0, %v0, 0, 0    # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x74]
+#CHECK: vschp	%v31, %v0, %v0, 0, 0    # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x74]
+#CHECK: vschp	%v18, %v3, %v20, 11, 4  # encoding: [0xe6,0x23,0x40,0x40,0xba,0x74]
+#CHECK: vschp	%v18, %v3, %v20, 0, 15  # encoding: [0xe6,0x23,0x40,0xf0,0x0a,0x74]
+
+	vschp	%v0, %v0, %v0, 0, 0
+	vschp	%v0, %v0, %v0, 15, 0
+	vschp	%v0, %v0, %v0, 0, 0
+	vschp	%v0, %v0, %v0, 15, 0
+	vschp	%v0, %v0, %v0, 0, 12
+	vschp	%v0, %v0, %v15, 0, 0
+	vschp	%v0, %v0, %v31, 0, 0
+	vschp	%v0, %v15, %v0, 0, 0
+	vschp	%v0, %v31, %v0, 0, 0
+	vschp	%v15, %v0, %v0, 0, 0
+	vschp	%v31, %v0, %v0, 0, 0
+	vschp	%v18, %v3, %v20, 11, 4
+	vschp	%v18, %v3, %v20, 0, 15
+
+#CHECK: vschsp	%v0, %v0, %v0, 0        # encoding: [0xe6,0x00,0x00,0x00,0x20,0x74]
+#CHECK: vschsp	%v0, %v0, %v0, 0        # encoding: [0xe6,0x00,0x00,0x00,0x20,0x74]
+#CHECK: vschsp	%v0, %v0, %v0, 12       # encoding: [0xe6,0x00,0x00,0xc0,0x20,0x74]
+#CHECK: vschsp	%v0, %v0, %v15, 0       # encoding: [0xe6,0x00,0xf0,0x00,0x20,0x74]
+#CHECK: vschsp	%v0, %v0, %v31, 0       # encoding: [0xe6,0x00,0xf0,0x00,0x22,0x74]
+#CHECK: vschsp	%v0, %v15, %v0, 0       # encoding: [0xe6,0x0f,0x00,0x00,0x20,0x74]
+#CHECK: vschsp	%v0, %v31, %v0, 0       # encoding: [0xe6,0x0f,0x00,0x00,0x24,0x74]
+#CHECK: vschsp	%v15, %v0, %v0, 0       # encoding: [0xe6,0xf0,0x00,0x00,0x20,0x74]
+#CHECK: vschsp	%v31, %v0, %v0, 0       # encoding: [0xe6,0xf0,0x00,0x00,0x28,0x74]
+#CHECK: vschsp	%v18, %v3, %v20, 0      # encoding: [0xe6,0x23,0x40,0x00,0x2a,0x74]
+
+	vschsp	%v0, %v0, %v0, 0
+	vschsp	%v0, %v0, %v0, 0
+	vschsp	%v0, %v0, %v0, 12
+	vschsp	%v0, %v0, %v15, 0
+	vschsp	%v0, %v0, %v31, 0
+	vschsp	%v0, %v15, %v0, 0
+	vschsp	%v0, %v31, %v0, 0
+	vschsp	%v15, %v0, %v0, 0
+	vschsp	%v31, %v0, %v0, 0
+	vschsp	%v18, %v3, %v20, 0
+
+#CHECK: vschdp	%v0, %v0, %v0, 0        # encoding: [0xe6,0x00,0x00,0x00,0x30,0x74]
+#CHECK: vschdp	%v0, %v0, %v0, 0        # encoding: [0xe6,0x00,0x00,0x00,0x30,0x74]
+#CHECK: vschdp	%v0, %v0, %v0, 12       # encoding: [0xe6,0x00,0x00,0xc0,0x30,0x74]
+#CHECK: vschdp	%v0, %v0, %v15, 0       # encoding: [0xe6,0x00,0xf0,0x00,0x30,0x74]
+#CHECK: vschdp	%v0, %v0, %v31, 0       # encoding: [0xe6,0x00,0xf0,0x00,0x32,0x74]
+#CHECK: vschdp	%v0, %v15, %v0, 0       # encoding: [0xe6,0x0f,0x00,0x00,0x30,0x74]
+#CHECK: vschdp	%v0, %v31, %v0, 0       # encoding: [0xe6,0x0f,0x00,0x00,0x34,0x74]
+#CHECK: vschdp	%v15, %v0, %v0, 0       # encoding: [0xe6,0xf0,0x00,0x00,0x30,0x74]
+#CHECK: vschdp	%v31, %v0, %v0, 0       # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x74]
+#CHECK: vschdp	%v18, %v3, %v20, 0      # encoding: [0xe6,0x23,0x40,0x00,0x3a,0x74]
+
+	vschdp	%v0, %v0, %v0, 0
+	vschdp	%v0, %v0, %v0, 0
+	vschdp	%v0, %v0, %v0, 12
+	vschdp	%v0, %v0, %v15, 0
+	vschdp	%v0, %v0, %v31, 0
+	vschdp	%v0, %v15, %v0, 0
+	vschdp	%v0, %v31, %v0, 0
+	vschdp	%v15, %v0, %v0, 0
+	vschdp	%v31, %v0, %v0, 0
+	vschdp	%v18, %v3, %v20, 0
+
+#CHECK: vschxp	%v0, %v0, %v0, 0        # encoding: [0xe6,0x00,0x00,0x00,0x40,0x74]
+#CHECK: vschxp	%v0, %v0, %v0, 0        # encoding: [0xe6,0x00,0x00,0x00,0x40,0x74]
+#CHECK: vschxp	%v0, %v0, %v0, 12       # encoding: [0xe6,0x00,0x00,0xc0,0x40,0x74]
+#CHECK: vschxp	%v0, %v0, %v15, 0       # encoding: [0xe6,0x00,0xf0,0x00,0x40,0x74]
+#CHECK: vschxp	%v0, %v0, %v31, 0       # encoding: [0xe6,0x00,0xf0,0x00,0x42,0x74]
+#CHECK: vschxp	%v0, %v15, %v0, 0       # encoding: [0xe6,0x0f,0x00,0x00,0x40,0x74]
+#CHECK: vschxp	%v0, %v31, %v0, 0       # encoding: [0xe6,0x0f,0x00,0x00,0x44,0x74]
+#CHECK: vschxp	%v15, %v0, %v0, 0       # encoding: [0xe6,0xf0,0x00,0x00,0x40,0x74]
+#CHECK: vschxp	%v31, %v0, %v0, 0       # encoding: [0xe6,0xf0,0x00,0x00,0x48,0x74]
+#CHECK: vschxp	%v18, %v3, %v20, 0      # encoding: [0xe6,0x23,0x40,0x00,0x4a,0x74]
+
+	vschxp	%v0, %v0, %v0, 0
+	vschxp	%v0, %v0, %v0, 0
+	vschxp	%v0, %v0, %v0, 12
+	vschxp	%v0, %v0, %v15, 0
+	vschxp	%v0, %v0, %v31, 0
+	vschxp	%v0, %v15, %v0, 0
+	vschxp	%v0, %v31, %v0, 0
+	vschxp	%v15, %v0, %v0, 0
+	vschxp	%v31, %v0, %v0, 0
+	vschxp	%v18, %v3, %v20, 0
+
+#CHECK: vscshp	%v0, %v0, %v0           # encoding: [0xe6,0x00,0x00,0x00,0x00,0x7c]
+#CHECK: vscshp	%v0, %v0, %v31          # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x7c]
+#CHECK: vscshp	%v0, %v31, %v0          # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x7c]
+#CHECK: vscshp	%v31, %v0, %v0          # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x7c]
+#CHECK: vscshp	%v18, %v3, %v20         # encoding: [0xe6,0x23,0x40,0x00,0x0a,0x7c]
+
+	vscshp	%v0, %v0, %v0
+	vscshp	%v0, %v0, %v31
+	vscshp	%v0, %v31, %v0
+	vscshp	%v31, %v0, %v0
+	vscshp	%v18, %v3, %v20
+
+#CHECK: vsrpr	%v0, %v0, %v0, 0, 0     # encoding: [0xe6,0x00,0x00,0x00,0x00,0x72]
+#CHECK: vsrpr	%v0, %v0, %v0, 0, 15    # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x72]
+#CHECK: vsrpr	%v0, %v0, %v0, 255, 0   # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x72]
+#CHECK: vsrpr	%v0, %v0, %v31, 0, 0    # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x72]
+#CHECK: vsrpr	%v0, %v31, %v0, 0, 0    # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x72]
+#CHECK: vsrpr	%v31, %v0, %v0, 0, 0    # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x72]
+#CHECK: vsrpr	%v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x72]
+
+	vsrpr	%v0, %v0, %v0, 0, 0
+	vsrpr	%v0, %v0, %v0, 0, 15
+	vsrpr	%v0, %v0, %v0, 255, 0
+	vsrpr	%v0, %v0, %v31, 0, 0
+	vsrpr	%v0, %v31, %v0, 0, 0
+	vsrpr	%v31, %v0, %v0, 0, 0
+	vsrpr	%v13, %v17, %v21, 0x79, 11
+
+#CHECK: vupkzh	%v0, %v0, 0             # encoding: [0xe6,0x00,0x00,0x00,0x00,0x54]
+#CHECK: vupkzh	%v0, %v0, 15            # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x54]
+#CHECK: vupkzh	%v0, %v15, 0            # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x54]
+#CHECK: vupkzh	%v0, %v31, 0            # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x54]
+#CHECK: vupkzh	%v15, %v0, 0            # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x54]
+#CHECK: vupkzh	%v31, %v0, 0            # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x54]
+#CHECK: vupkzh	%v18, %v3, 12           # encoding: [0xe6,0x23,0x00,0xc0,0x08,0x54]
+
+	vupkzh	%v0, %v0, 0
+	vupkzh	%v0, %v0, 15
+	vupkzh	%v0, %v15, 0
+	vupkzh	%v0, %v31, 0
+	vupkzh	%v15, %v0, 0
+	vupkzh	%v31, %v0, 0
+	vupkzh	%v18, %v3, 12
+
+#CHECK: vupkzl	%v0, %v0, 0             # encoding: [0xe6,0x00,0x00,0x00,0x00,0x5c]
+#CHECK: vupkzl	%v0, %v0, 15            # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x5c]
+#CHECK: vupkzl	%v0, %v15, 0            # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x5c]
+#CHECK: vupkzl	%v0, %v31, 0            # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x5c]
+#CHECK: vupkzl	%v15, %v0, 0            # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x5c]
+#CHECK: vupkzl	%v31, %v0, 0            # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x5c]
+#CHECK: vupkzl	%v18, %v3, 12           # encoding: [0xe6,0x23,0x00,0xc0,0x08,0x5c]
+
+	vupkzl	%v0, %v0, 0
+	vupkzl	%v0, %v0, 15
+	vupkzl	%v0, %v15, 0
+	vupkzl	%v0, %v31, 0
+	vupkzl	%v15, %v0, 0
+	vupkzl	%v31, %v0, 0
+	vupkzl	%v18, %v3, 12
diff --git a/unittests/Support/Host.cpp b/unittests/Support/Host.cpp
index 6e7f95e228a..0d6e36b0ae7 100644
--- a/unittests/Support/Host.cpp
+++ b/unittests/Support/Host.cpp
@@ -312,10 +312,14 @@ CPU revision    : 0
 
 TEST(getLinuxHostCPUName, s390x) {
   SmallVector<std::string> ModelIDs(
-      {"8561", "3906", "2964", "2827", "2817", "2097", "2064"});
+      {"3931", "8561", "3906", "2964", "2827", "2817", "2097", "2064"});
   SmallVector<std::string> VectorSupport({"", "vx"});
   SmallVector<StringRef> ExpectedCPUs;
 
+  // Model Id: 3931
+  ExpectedCPUs.push_back("zEC12");
+  ExpectedCPUs.push_back("arch14");
+
   // Model Id: 8561
   ExpectedCPUs.push_back("zEC12");
   ExpectedCPUs.push_back("z15");