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[X86] Remove an isel pattern than can never match. Remove bitcasts of loads from a few others.

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This commit is contained in:
Craig Topper 2020-06-30 00:17:52 -07:00
parent 9dd94e95f6
commit 81bbddcf65
1 changed files with 9 additions and 9 deletions
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18
lib/Target/X86/X86InstrXOP.td
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@ -335,13 +335,13 @@ multiclass xop4op_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
[(set RC:$dst, (VT (or (and RC:$src3, RC:$src1), [(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
(X86andnp RC:$src3, RC:$src2))))]>, XOP_4V, (X86andnp RC:$src3, RC:$src2))))]>, XOP_4V,
Sched<[sched]>; Sched<[sched]>;
// FIXME: This pattern can't match. // FIXME: We can't write a pattern for this in tablegen.
let hasSideEffects = 0, mayLoad = 1 in
def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs RC:$dst), def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs RC:$dst),
(ins RC:$src1, RC:$src2, x86memop:$src3), (ins RC:$src1, RC:$src2, x86memop:$src3),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set RC:$dst, (VT (or (and (load addr:$src3), RC:$src1), []>,
(X86andnp (load addr:$src3), RC:$src2))))]>,
XOP_4V, VEX_W, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; XOP_4V, VEX_W, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>;
def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs RC:$dst), def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, x86memop:$src2, RC:$src3), (ins RC:$src1, x86memop:$src2, RC:$src3),
@ -383,13 +383,13 @@ let Predicates = [HasXOP] in {
(VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>; (VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;
def : Pat<(or (and VR128:$src3, VR128:$src1), def : Pat<(or (and VR128:$src3, VR128:$src1),
(X86andnp VR128:$src3, (bc_v16i8 (loadv2i64 addr:$src2)))), (X86andnp VR128:$src3, (loadv16i8 addr:$src2))),
(VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>; (VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>;
def : Pat<(or (and VR128:$src3, VR128:$src1), def : Pat<(or (and VR128:$src3, VR128:$src1),
(X86andnp VR128:$src3, (bc_v8i16 (loadv2i64 addr:$src2)))), (X86andnp VR128:$src3, (loadv8i16 addr:$src2))),
(VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>; (VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>;
def : Pat<(or (and VR128:$src3, VR128:$src1), def : Pat<(or (and VR128:$src3, VR128:$src1),
(X86andnp VR128:$src3, (bc_v4i32 (loadv2i64 addr:$src2)))), (X86andnp VR128:$src3, (loadv4i32 addr:$src2))),
(VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>; (VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>;
def : Pat<(v32i8 (or (and VR256:$src3, VR256:$src1), def : Pat<(v32i8 (or (and VR256:$src3, VR256:$src1),
@ -403,13 +403,13 @@ let Predicates = [HasXOP] in {
(VPCMOVYrrr VR256:$src1, VR256:$src2, VR256:$src3)>; (VPCMOVYrrr VR256:$src1, VR256:$src2, VR256:$src3)>;
def : Pat<(or (and VR256:$src3, VR256:$src1), def : Pat<(or (and VR256:$src3, VR256:$src1),
(X86andnp VR256:$src3, (bc_v32i8 (loadv4i64 addr:$src2)))), (X86andnp VR256:$src3, (loadv32i8 addr:$src2))),
(VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>; (VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>;
def : Pat<(or (and VR256:$src3, VR256:$src1), def : Pat<(or (and VR256:$src3, VR256:$src1),
(X86andnp VR256:$src3, (bc_v16i16 (loadv4i64 addr:$src2)))), (X86andnp VR256:$src3, (loadv16i16 addr:$src2))),
(VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>; (VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>;
def : Pat<(or (and VR256:$src3, VR256:$src1), def : Pat<(or (and VR256:$src3, VR256:$src1),
(X86andnp VR256:$src3, (bc_v8i32 (loadv4i64 addr:$src2)))), (X86andnp VR256:$src3, (loadv8i32 addr:$src2))),
(VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>; (VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>;
} }