From 8205c3a802133f3479f6fb3cdbd1de6d27497f01 Mon Sep 17 00:00:00 2001
From: Sam Elliott <selliott@lowrisc.org>
Date: Tue, 9 Jul 2019 16:24:16 +0000
Subject: [PATCH] [RISCV] Fix ICE in isDesirableToCommuteWithShift

Summary:
There was an error being thrown from isDesirableToCommuteWithShift in
some tests. This was tracked down to the method being called before
legalisation, with an extended value type, not a machine value type.

In the case I diagnosed, the error was only hit with an instruction sequence
involving `i24`s in the add and shift. `i24` is not a Machine ValueType, it is
instead an Extended ValueType which was causing the issue.

I have added a test to cover this case, and fixed the error in the callback.

Reviewers: asb, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64425

llvm-svn: 365511
---
 lib/Target/RISCV/RISCVISelLowering.cpp |  2 +-
 test/CodeGen/RISCV/add-before-shl.ll   | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/lib/Target/RISCV/RISCVISelLowering.cpp b/lib/Target/RISCV/RISCVISelLowering.cpp
index 9befd022a17..5d8a2b0a650 100644
--- a/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -995,7 +995,7 @@ bool RISCVTargetLowering::isDesirableToCommuteWithShift(
   //   (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
   //   (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)
   SDValue N0 = N->getOperand(0);
-  MVT Ty = N0.getSimpleValueType();
+  EVT Ty = N0.getValueType();
   if (Ty.isScalarInteger() &&
       (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR)) {
     auto *C1 = dyn_cast<ConstantSDNode>(N0->getOperand(1));
diff --git a/test/CodeGen/RISCV/add-before-shl.ll b/test/CodeGen/RISCV/add-before-shl.ll
index 1a2148c9a57..05bcc191b6c 100644
--- a/test/CodeGen/RISCV/add-before-shl.ll
+++ b/test/CodeGen/RISCV/add-before-shl.ll
@@ -72,3 +72,22 @@ define signext i32 @add_huge_const(i32 signext %a) nounwind {
   %3 = ashr i32 %2, 16
   ret i32 %3
 }
+
+define signext i24 @add_non_machine_type(i24 signext %a) nounwind {
+; RV32I-LABEL: add_non_machine_type:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, 256
+; RV32I-NEXT:    slli a0, a0, 20
+; RV32I-NEXT:    srai a0, a0, 8
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add_non_machine_type:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, 256
+; RV64I-NEXT:    slli a0, a0, 52
+; RV64I-NEXT:    srai a0, a0, 40
+; RV64I-NEXT:    ret
+  %1 = add i24 %a, 256
+  %2 = shl i24 %1, 12
+  ret i24 %2
+}