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[X86] Add WriteRotate schedule class, splitting off from WriteShift.

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NFCI for now, but it should make it easier to remove a lot of unnecessary overrides in a future commit.

Now that funnel shift intrinsics are coming online we need to get this cleaned up to make vectorization costs from scalar rotate patterns more straightforward.

llvm-svn: 342837
This commit is contained in:
Simon Pilgrim 2018-09-23 15:12:10 +00:00
parent 87dca03df6
commit 82107f05bf
11 changed files with 27 additions and 16 deletions
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16
lib/Target/X86/X86InstrShiftRotate.td
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@ -325,7 +325,7 @@ def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
//===----------------------------------------------------------------------===//
let hasSideEffects = 0 in {
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
let Constraints = "$src1 = $dst", SchedRW = [WriteRotate] in {
let Uses = [CL, EFLAGS] in {
def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
@ -389,7 +389,7 @@ def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
} // Constraints = "$src = $dst"
let SchedRW = [WriteShiftLd, WriteRMW], mayStore = 1 in {
let SchedRW = [WriteRotateLd, WriteRMW], mayStore = 1 in {
let Uses = [EFLAGS] in {
def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
"rcl{b}\t$dst", []>;
@ -452,7 +452,7 @@ def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
} // SchedRW
} // hasSideEffects = 0
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
let Constraints = "$src1 = $dst", SchedRW = [WriteRotate] in {
// FIXME: provide shorter instructions when imm8 == 1
let Uses = [CL] in {
def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
@ -498,7 +498,7 @@ def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
[(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
} // Constraints = "$src = $dst", SchedRW
let SchedRW = [WriteShiftLd, WriteRMW] in {
let SchedRW = [WriteRotateLd, WriteRMW] in {
let Uses = [CL] in {
def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
"rol{b}\t{%cl, $dst|$dst, cl}",
@ -548,7 +548,7 @@ def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
Requires<[In64BitMode]>;
} // SchedRW
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
let Constraints = "$src1 = $dst", SchedRW = [WriteRotate] in {
let Uses = [CL] in {
def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
"ror{b}\t{%cl, $dst|$dst, cl}",
@ -595,7 +595,7 @@ def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
[(set GR64:$dst, (rotl GR64:$src1, (i8 63)))]>;
} // Constraints = "$src = $dst", SchedRW
let SchedRW = [WriteShiftLd, WriteRMW] in {
let SchedRW = [WriteRotateLd, WriteRMW] in {
let Uses = [CL] in {
def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
"ror{b}\t{%cl, $dst|$dst, cl}",
@ -826,12 +826,12 @@ multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {
let hasSideEffects = 0 in {
def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2),
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, TAXD, VEX, Sched<[WriteShift]>;
[]>, TAXD, VEX, Sched<[WriteRotate]>;
let mayLoad = 1 in
def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
(ins x86memop:$src1, u8imm:$src2),
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, TAXD, VEX, Sched<[WriteShiftLd]>;
[]>, TAXD, VEX, Sched<[WriteRotateLd]>;
}
}

3
lib/Target/X86/X86SchedBroadwell.td
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@ -150,7 +150,8 @@ defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>;
defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>;
// Integer shifts and rotates.
defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
defm : BWWriteResPair<WriteRotate, [BWPort06], 1>;
// SHLD/SHRD.
defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>;

1
lib/Target/X86/X86SchedHaswell.td
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@ -134,6 +134,7 @@ def : WriteRes<WriteIMulH, []> { let Latency = 3; }
// Integer shifts and rotates.
defm : HWWriteResPair<WriteShift, [HWPort06], 1>;
defm : HWWriteResPair<WriteRotate, [HWPort06], 1>;
// SHLD/SHRD.
defm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>;

4
lib/Target/X86/X86SchedSandyBridge.td
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@ -135,7 +135,9 @@ defm : X86WriteRes<WriteSHDrrcl,[SBPort05, SBPort015], 4, [3, 1], 4>;
defm : X86WriteRes<WriteSHDmri, [SBPort4,SBPort23,SBPort05,SBPort015], 8, [1, 2, 1, 1], 5>;
defm : X86WriteRes<WriteSHDmrcl,[SBPort4,SBPort23,SBPort05,SBPort015], 10, [1, 2, 3, 1], 7>;
defm : SBWriteResPair<WriteShift, [SBPort05], 1>;
defm : SBWriteResPair<WriteShift, [SBPort05], 1>;
defm : SBWriteResPair<WriteRotate, [SBPort05], 1>;
defm : SBWriteResPair<WriteJump, [SBPort5], 1>;
defm : SBWriteResPair<WriteCRC32, [SBPort1], 3, [1], 1, 5>;

3
lib/Target/X86/X86SchedSkylakeClient.td
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@ -149,7 +149,8 @@ defm : SKLWriteResPair<WriteTZCNT, [SKLPort1], 3>;
defm : SKLWriteResPair<WritePOPCNT, [SKLPort1], 3>;
// Integer shifts and rotates.
defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>;
defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>;
defm : SKLWriteResPair<WriteRotate, [SKLPort06], 1>;
// SHLD/SHRD.
defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;

5
lib/Target/X86/X86SchedSkylakeServer.td
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@ -139,10 +139,11 @@ def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
let NumMicroOps = 3;
}
def : WriteRes<WriteLAHFSAHF, [SKXPort06]>;
def : WriteRes<WriteBitTest,[SKXPort06]>; //
def : WriteRes<WriteBitTest, [SKXPort06]>; //
// Integer shifts and rotates.
defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;
defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;
defm : SKXWriteResPair<WriteRotate, [SKXPort06], 1>;
// SHLD/SHRD.
defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;

1
lib/Target/X86/X86Schedule.td
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@ -149,6 +149,7 @@ def WriteBitTest : SchedWrite; // Bit Test - TODO add memory folding support
// Integer shifts and rotates.
defm WriteShift : X86SchedWritePair;
defm WriteRotate : X86SchedWritePair;
// Double shift instructions.
def WriteSHDrri : SchedWrite;

3
lib/Target/X86/X86ScheduleAtom.td
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@ -153,7 +153,8 @@ defm : X86WriteResPairUnsupported<WriteBZHI>;
// Integer shifts and rotates.
////////////////////////////////////////////////////////////////////////////////
defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>;
defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>;
defm : AtomWriteResPair<WriteRotate, [AtomPort0], [AtomPort0]>;
defm : X86WriteRes<WriteSHDrri, [AtomPort01], 2, [2], 1>;
defm : X86WriteRes<WriteSHDrrcl,[AtomPort01], 2, [2], 1>;

3
lib/Target/X86/X86ScheduleBtVer2.td
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@ -212,7 +212,8 @@ defm : X86WriteResPairUnsupported<WriteBZHI>;
// Integer shifts and rotates.
////////////////////////////////////////////////////////////////////////////////
defm : JWriteResIntPair<WriteShift, [JALU01], 1>;
defm : JWriteResIntPair<WriteShift, [JALU01], 1>;
defm : JWriteResIntPair<WriteRotate, [JALU01], 1>;
// SHLD/SHRD.
defm : X86WriteRes<WriteSHDrri, [JALU01], 3, [6], 6>;

1
lib/Target/X86/X86ScheduleSLM.td
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@ -105,6 +105,7 @@ defm : X86WriteRes<WriteCMPXCHGRMW, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1, 2], 2>;
defm : X86WriteRes<WriteXCHG, [SLM_IEC_RSV01], 1, [1], 1>;
defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>;
defm : SLMWriteResPair<WriteRotate, [SLM_IEC_RSV0], 1>;
defm : X86WriteRes<WriteSHDrri, [SLM_IEC_RSV0], 1, [1], 1>;
defm : X86WriteRes<WriteSHDrrcl,[SLM_IEC_RSV0], 1, [1], 1>;

3
lib/Target/X86/X86ScheduleZnver1.td
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@ -186,7 +186,8 @@ defm : X86WriteRes<WriteCMPXCHG, [ZnALU], 1, [1], 1>;
defm : X86WriteRes<WriteCMPXCHGRMW,[ZnALU,ZnAGU], 8, [1,1], 5>;
defm : X86WriteRes<WriteXCHG, [ZnALU], 1, [2], 2>;
defm : ZnWriteResPair<WriteShift, [ZnALU], 1>;
defm : ZnWriteResPair<WriteShift, [ZnALU], 1>;
defm : ZnWriteResPair<WriteRotate, [ZnALU], 1>;
defm : X86WriteRes<WriteSHDrri, [ZnALU], 1, [1], 1>;
defm : X86WriteResUnsupported<WriteSHDrrcl>;