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AMDGPU: Set HasExtractBitInsn
This currently does not have the control over the bitwidth, and there are missing optimizations to reduce the integer to 32-bit if it can be. But in most situations we do want the sinking to occur. llvm-svn: 262296
This commit is contained in:
Matt Arsenault
parent
f7676c3bd3
commit
8238b5c22c
@ -295,6 +295,17 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
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setOperationAction(ISD::CTLZ, MVT::i64, Custom);
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setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
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// We only really have 32-bit BFE instructions (and 16-bit on VI).
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//
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// On SI+ there are 64-bit BFEs, but they are scalar only and there isn't any
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// effort to match them now. We want this to be false for i64 cases when the
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// extraction isn't restricted to the upper or lower half. Ideally we would
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// have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
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// span the midpoint are probably relatively rare, so don't worry about them
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// for now.
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if (Subtarget->hasBFE())
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setHasExtractBitsInsn(true);
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static const MVT::SimpleValueType VectorIntTypes[] = {
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MVT::v2i32, MVT::v4i32
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};
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303
test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
Normal file
303
test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
Normal file
@ -0,0 +1,303 @@
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; RUN: opt -S -mtriple=amdgcn-- -codegenprepare < %s | FileCheck -check-prefix=OPT %s
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -codegenprepare < %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; This particular case will actually be worse in terms of code size
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; from sinking into both.
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; OPT-LABEL: @sink_ubfe_i32(
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; OPT: entry:
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; OPT-NEXT: br i1
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; OPT: bb0:
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; OPT: %0 = lshr i32 %arg1, 8
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; OPT-NEXT: %val0 = and i32 %0, 255
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; OPT: br label
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; OPT: bb1:
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; OPT: %1 = lshr i32 %arg1, 8
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; OPT-NEXT: %val1 = and i32 %1, 127
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; OPT: br label
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; OPT: ret:
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; OPT: store
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; OPT: ret
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; GCN-LABEL: {{^}}sink_ubfe_i32:
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; GCN-NOT: lshr
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; GCN: s_cbranch_vccnz
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008
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; GCN: BB0_2:
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70008
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; GCN: BB0_3:
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; GCN: buffer_store_dword
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; GCN: s_endpgm
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define void @sink_ubfe_i32(i32 addrspace(1)* %out, i32 %arg1) #0 {
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entry:
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%shr = lshr i32 %arg1, 8
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br i1 undef, label %bb0, label %bb1
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bb0:
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%val0 = and i32 %shr, 255
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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bb1:
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%val1 = and i32 %shr, 127
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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ret:
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%phi = phi i32 [ %val0, %bb0 ], [ %val1, %bb1 ]
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store i32 %phi, i32 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @sink_sbfe_i32(
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; OPT: entry:
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; OPT-NEXT: br i1
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; OPT: bb0:
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; OPT: %0 = ashr i32 %arg1, 8
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; OPT-NEXT: %val0 = and i32 %0, 255
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; OPT: br label
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; OPT: bb1:
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; OPT: %1 = ashr i32 %arg1, 8
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; OPT-NEXT: %val1 = and i32 %1, 127
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; OPT: br label
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; OPT: ret:
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; OPT: store
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; OPT: ret
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; GCN-LABEL: {{^}}sink_sbfe_i32:
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define void @sink_sbfe_i32(i32 addrspace(1)* %out, i32 %arg1) #0 {
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entry:
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%shr = ashr i32 %arg1, 8
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br i1 undef, label %bb0, label %bb1
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bb0:
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%val0 = and i32 %shr, 255
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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bb1:
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%val1 = and i32 %shr, 127
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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ret:
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%phi = phi i32 [ %val0, %bb0 ], [ %val1, %bb1 ]
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store i32 %phi, i32 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @sink_ubfe_i16(
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; OPT: entry:
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; OPT-NEXT: br i1
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; OPT: bb0:
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; OPT: %0 = lshr i16 %arg1, 4
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; OPT-NEXT: %val0 = and i16 %0, 255
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; OPT: br label
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; OPT: bb1:
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; OPT: %1 = lshr i16 %arg1, 4
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; OPT-NEXT: %val1 = and i16 %1, 127
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; OPT: br label
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; OPT: ret:
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; OPT: store
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; OPT: ret
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; GCN-LABEL: {{^}}sink_ubfe_i16:
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; GCN-NOT: lshr
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; GCN: s_cbranch_vccnz
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80004
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; GCN: BB2_2:
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70004
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; GCN: BB2_3:
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; GCN: buffer_store_short
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; GCN: s_endpgm
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define void @sink_ubfe_i16(i16 addrspace(1)* %out, i16 %arg1) #0 {
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entry:
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%shr = lshr i16 %arg1, 4
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br i1 undef, label %bb0, label %bb1
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bb0:
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%val0 = and i16 %shr, 255
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store volatile i16 0, i16 addrspace(1)* undef
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br label %ret
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bb1:
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%val1 = and i16 %shr, 127
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store volatile i16 0, i16 addrspace(1)* undef
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br label %ret
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ret:
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%phi = phi i16 [ %val0, %bb0 ], [ %val1, %bb1 ]
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store i16 %phi, i16 addrspace(1)* %out
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ret void
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}
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; We don't really want to sink this one since it isn't reducible to a
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; 32-bit BFE on one half of the integer.
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; OPT-LABEL: @sink_ubfe_i64_span_midpoint(
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; OPT: entry:
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; OPT-NOT: lshr
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; OPT: br i1
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; OPT: bb0:
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; OPT: %0 = lshr i64 %arg1, 30
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; OPT-NEXT: %val0 = and i64 %0, 255
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; OPT: bb1:
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; OPT: %1 = lshr i64 %arg1, 30
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; OPT-NEXT: %val1 = and i64 %1, 127
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; OPT: ret:
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; OPT: store
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; OPT: ret
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; GCN-LABEL: {{^}}sink_ubfe_i64_span_midpoint:
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; GCN: s_cbranch_vccnz BB3_2
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; GCN: s_lshr_b64 s{{\[}}[[LO:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 30
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; GCN: s_and_b32 s{{[0-9]+}}, s[[LO]], 0xff
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; GCN: BB3_2:
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; GCN: s_lshr_b64 s{{\[}}[[LO:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 30
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; GCN: s_and_b32 s{{[0-9]+}}, s[[LO]], 0x7f
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; GCN: BB3_3:
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; GCN: buffer_store_dwordx2
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define void @sink_ubfe_i64_span_midpoint(i64 addrspace(1)* %out, i64 %arg1) #0 {
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entry:
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%shr = lshr i64 %arg1, 30
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br i1 undef, label %bb0, label %bb1
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bb0:
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%val0 = and i64 %shr, 255
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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bb1:
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%val1 = and i64 %shr, 127
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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ret:
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%phi = phi i64 [ %val0, %bb0 ], [ %val1, %bb1 ]
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store i64 %phi, i64 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @sink_ubfe_i64_low32(
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; OPT: entry:
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; OPT-NOT: lshr
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; OPT: br i1
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; OPT: bb0:
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; OPT: %0 = lshr i64 %arg1, 15
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; OPT-NEXT: %val0 = and i64 %0, 255
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; OPT: bb1:
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; OPT: %1 = lshr i64 %arg1, 15
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; OPT-NEXT: %val1 = and i64 %1, 127
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; OPT: ret:
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; OPT: store
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; OPT: ret
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; GCN-LABEL: {{^}}sink_ubfe_i64_low32:
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; GCN: s_cbranch_vccnz BB4_2
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; GCN: s_lshr_b64 s{{\[}}[[LO:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 15
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; GCN: s_and_b32 s{{[0-9]+}}, s[[LO]], 0xff
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; GCN: BB4_2:
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; GCN: s_lshr_b64 s{{\[}}[[LO:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 15
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; GCN: s_and_b32 s{{[0-9]+}}, s[[LO]], 0x7f
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; GCN: BB4_3:
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; GCN: buffer_store_dwordx2
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define void @sink_ubfe_i64_low32(i64 addrspace(1)* %out, i64 %arg1) #0 {
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entry:
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%shr = lshr i64 %arg1, 15
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br i1 undef, label %bb0, label %bb1
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bb0:
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%val0 = and i64 %shr, 255
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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bb1:
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%val1 = and i64 %shr, 127
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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ret:
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%phi = phi i64 [ %val0, %bb0 ], [ %val1, %bb1 ]
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store i64 %phi, i64 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @sink_ubfe_i64_high32(
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; OPT: entry:
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; OPT-NOT: lshr
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; OPT: br i1
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; OPT: bb0:
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; OPT: %0 = lshr i64 %arg1, 35
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; OPT-NEXT: %val0 = and i64 %0, 255
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; OPT: bb1:
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; OPT: %1 = lshr i64 %arg1, 35
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; OPT-NEXT: %val1 = and i64 %1, 127
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; OPT: ret:
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; OPT: store
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; OPT: ret
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; GCN-LABEL: {{^}}sink_ubfe_i64_high32:
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; GCN: s_cbranch_vccnz BB5_2
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80003
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; GCN: BB5_2:
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70003
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; GCN: BB5_3:
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; GCN: buffer_store_dwordx2
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define void @sink_ubfe_i64_high32(i64 addrspace(1)* %out, i64 %arg1) #0 {
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entry:
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%shr = lshr i64 %arg1, 35
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br i1 undef, label %bb0, label %bb1
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bb0:
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%val0 = and i64 %shr, 255
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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bb1:
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%val1 = and i64 %shr, 127
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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ret:
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%phi = phi i64 [ %val0, %bb0 ], [ %val1, %bb1 ]
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store i64 %phi, i64 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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