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AMDGPU: Use v_med3_{f16|i16|u16}
llvm-svn: 296401
This commit is contained in:
Matt Arsenault
parent
f2e8848268
commit
824e186e4d
@ -664,9 +664,10 @@ class ROTRPattern <Instruction BIT_ALIGN> : Pat <
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class IntMed3Pat<Instruction med3Inst,
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SDPatternOperator max,
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SDPatternOperator max_oneuse,
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SDPatternOperator min_oneuse> : Pat<
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(max (min_oneuse i32:$src0, i32:$src1),
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(min_oneuse (max_oneuse i32:$src0, i32:$src1), i32:$src2)),
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SDPatternOperator min_oneuse,
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ValueType vt = i32> : Pat<
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(max (min_oneuse vt:$src0, vt:$src1),
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(min_oneuse (max_oneuse vt:$src0, vt:$src1), vt:$src2)),
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(med3Inst $src0, $src1, $src2)
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>;
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@ -276,6 +276,10 @@ public:
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return (getGeneration() >= EVERGREEN);
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}
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bool hasMed3_16() const {
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return getGeneration() >= GFX9;
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}
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bool hasCARRY() const {
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return (getGeneration() >= EVERGREEN);
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}
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@ -4069,8 +4069,9 @@ static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
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}
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}
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static SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
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SDValue Op0, SDValue Op1, bool Signed) {
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SDValue SITargetLowering::performIntMed3ImmCombine(
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SelectionDAG &DAG, const SDLoc &SL,
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SDValue Op0, SDValue Op1, bool Signed) const {
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ConstantSDNode *K1 = dyn_cast<ConstantSDNode>(Op1);
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if (!K1)
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return SDValue();
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@ -4088,23 +4089,22 @@ static SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
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}
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EVT VT = K0->getValueType(0);
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unsigned Med3Opc = Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3;
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if (VT == MVT::i32 || (VT == MVT::i16 && Subtarget->hasMed3_16())) {
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return DAG.getNode(Med3Opc, SL, VT,
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Op0.getOperand(0), SDValue(K0, 0), SDValue(K1, 0));
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}
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// If there isn't a 16-bit med3 operation, convert to 32-bit.
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MVT NVT = MVT::i32;
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unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
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SDValue Tmp1, Tmp2, Tmp3;
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Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0));
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Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1));
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Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1);
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SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0));
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SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1));
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SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1);
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if (VT == MVT::i16) {
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Tmp1 = DAG.getNode(Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3, SL, NVT,
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Tmp1, Tmp2, Tmp3);
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return DAG.getNode(ISD::TRUNCATE, SL, VT, Tmp1);
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} else
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return DAG.getNode(Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3, SL, VT,
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Op0.getOperand(0), SDValue(K0, 0), SDValue(K1, 0));
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SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3);
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return DAG.getNode(ISD::TRUNCATE, SL, VT, Med3);
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}
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static bool isKnownNeverSNan(SelectionDAG &DAG, SDValue Op) {
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@ -4141,9 +4141,8 @@ SDValue SITargetLowering::performFPMed3ImmCombine(SelectionDAG &DAG,
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return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Op0.getOperand(0));
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}
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// No med3 for f16, but clamp is possible.
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// TODO: gfx9 has med3 f16
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if (VT == MVT::f16 || VT == MVT::f64)
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// med3 for f16 is only available on gfx9+.
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if (VT == MVT::f64 || (VT == MVT::f16 && !Subtarget->hasMed3_16()))
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return SDValue();
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// This isn't safe with signaling NaNs because in IEEE mode, min/max on a
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@ -86,6 +86,8 @@ class SITargetLowering final : public AMDGPUTargetLowering {
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SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
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SDValue Op0, SDValue Op1) const;
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SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
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SDValue Op0, SDValue Op1, bool Signed) const;
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SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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@ -1321,7 +1321,7 @@ def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i16, untyped]>;
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def VOP_F16_F16_I32 : VOPProfile <[f16, f16, i32, untyped]>;
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def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
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def VOP_I16_I16_I16_I16 : VOPProfile <[i32, i32, i32, i32, untyped]>;
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def VOP_I16_I16_I16_I16 : VOPProfile <[i16, i16, i16, i16, untyped]>;
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def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
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def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>;
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@ -1216,6 +1216,14 @@ def : Pat <
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// Miscellaneous Optimization Patterns
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//============================================================================//
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// Undo sub x, c -> add x, -c canonicalization since c is more likely
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// an inline immediate than -c.
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// TODO: Also do for 64-bit.
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def : Pat<
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(add i32:$src0, (i32 NegSubInlineConst32:$src1)),
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(S_SUB_I32 $src0, NegSubInlineConst32:$src1)
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>;
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def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>;
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def : IntMed3Pat<V_MED3_I32, smax, smax_oneuse, smin_oneuse>;
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@ -1235,14 +1243,11 @@ class FPMed3Pat<ValueType vt,
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def : FPMed3Pat<f32, V_MED3_F32>;
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// Undo sub x, c -> add x, -c canonicalization since c is more likely
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// an inline immediate than -c.
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// TODO: Also do for 64-bit.
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def : Pat<
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(add i32:$src0, (i32 NegSubInlineConst32:$src1)),
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(S_SUB_I32 $src0, NegSubInlineConst32:$src1)
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>;
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let Predicates = [isGFX9] in {
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def : FPMed3Pat<f16, V_MED3_F16>;
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def : IntMed3Pat<V_MED3_I16, smax, smax_oneuse, smin_oneuse, i16>;
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def : IntMed3Pat<V_MED3_U16, umax, umax_oneuse, umin_oneuse, i16>;
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} // End Predicates = [isGFX9]
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//============================================================================//
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// Assembler aliases
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@ -258,8 +258,8 @@ def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
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let Predicates = [isVI] in {
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multiclass Tenary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
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Instruction inst, SDPatternOperator op3> {
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multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
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Instruction inst, SDPatternOperator op3> {
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def : Pat<
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(op2 (op1 i16:$src0, i16:$src1), i16:$src2),
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(inst i16:$src0, i16:$src1, i16:$src2)
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@ -278,8 +278,8 @@ def : Pat<
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>;
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}
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defm: Tenary_i16_Pats<mul, add, V_MAD_U16, zext>;
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defm: Tenary_i16_Pats<mul, add, V_MAD_I16, sext>;
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defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>;
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defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>;
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} // End Predicates = [isVI]
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@ -291,6 +291,10 @@ def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
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def V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
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def V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
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def V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
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def V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUfmed3>;
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def V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16>, AMDGPUsmed3>;
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def V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16>, AMDGPUumed3>;
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}
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@ -487,3 +491,7 @@ defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>;
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defm V_AND_OR_B32 : VOP3_Real_vi <0x201>;
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defm V_OR3_B32 : VOP3_Real_vi <0x202>;
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defm V_PACK_B32_F16 : VOP3_Real_vi <0x2a0>;
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defm V_MED3_F16 : VOP3_Real_vi <0x1fa>;
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defm V_MED3_I16 : VOP3_Real_vi <0x1fb>;
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defm V_MED3_U16 : VOP3_Real_vi <0x1fc>;
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@ -1,5 +1,10 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 %s
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; RUN: llc -march=amdgcn -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s
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; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s
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; GCN-LABEL: {{^}}v_test_nnan_input_fmed3_r_i_i_f32:
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; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, v{{[0-9]+}}
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@ -688,8 +693,8 @@ define void @v_test_global_nnans_med3_f32_pat15(float addrspace(1)* %out, float
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; ---------------------------------------------------------------------
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; GCN-LABEL: {{^}}v_test_safe_med3_f32_pat0_multi_use0:
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; GCN: v_min_f32
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; GCN: v_max_f32
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; GCN-DAG: v_min_f32
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; GCN-DAG: v_max_f32
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; GCN: v_min_f32
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; GCN: v_max_f32
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define void @v_test_safe_med3_f32_pat0_multi_use0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #1 {
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@ -884,12 +889,86 @@ define void @v_test_global_nnans_min_max_f32(float addrspace(1)* %out, float add
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ret void
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}
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; GCN-LABEL: {{^}}v_test_nnan_input_fmed3_r_i_i_f16:
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; SI: v_cvt_f32_f16
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; SI: v_add_f32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}
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; SI: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0
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; SI: v_cvt_f16_f32
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; VI: v_add_f16_e32 v{{[0-9]+}}, 1.0
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; VI: v_max_f16_e32 v{{[0-9]+}}, 2.0
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; VI: v_min_f16_e32 v{{[0-9]+}}, 4.0
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; GFX9: v_add_f16_e32 v{{[0-9]+}}, 1.0
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; GFX9: v_med3_f16 v{{[0-9]+}}, [[ADD]], 2.0, 4.0
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define void @v_test_nnan_input_fmed3_r_i_i_f16(half addrspace(1)* %out, half addrspace(1)* %aptr) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr half, half addrspace(1)* %aptr, i32 %tid
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%outgep = getelementptr half, half addrspace(1)* %out, i32 %tid
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%a = load half, half addrspace(1)* %gep0
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%a.add = fadd nnan half %a, 1.0
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%max = call half @llvm.maxnum.f16(half %a.add, half 2.0)
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%med = call half @llvm.minnum.f16(half %max, half 4.0)
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store half %med, half addrspace(1)* %outgep
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ret void
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}
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; GCN-LABEL: {{^}}v_nnan_inputs_med3_f16_pat0:
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; GCN: {{buffer_|flat_}}load_ushort [[A:v[0-9]+]]
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; GCN: {{buffer_|flat_}}load_ushort [[B:v[0-9]+]]
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; GCN: {{buffer_|flat_}}load_ushort [[C:v[0-9]+]]
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; SI: v_cvt_f32_f16
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; SI: v_cvt_f32_f16
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; SI: v_add_f32_e32
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; SI: v_add_f32_e32
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; SI: v_add_f32_e32
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; SI: v_med3_f32
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; SI: v_cvt_f16_f32_e32
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; GFX89-DAG: v_add_f16_e32 [[A_ADD:v[0-9]+]], 1.0, [[A]]
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; GFX89-DAG: v_add_f16_e32 [[B_ADD:v[0-9]+]], 2.0, [[B]]
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; GFX89-DAG: v_add_f16_e32 [[C_ADD:v[0-9]+]], 4.0, [[C]]
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; VI-DAG: v_min_f16
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; VI-DAG: v_max_f16
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; VI: v_min_f16
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; VI: v_max_f16
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; GFX9: v_med3_f16 v{{[0-9]+}}, [[A_ADD]], [[B_ADD]], [[C_ADD]]
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define void @v_nnan_inputs_med3_f16_pat0(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr half, half addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr half, half addrspace(1)* %bptr, i32 %tid
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%gep2 = getelementptr half, half addrspace(1)* %cptr, i32 %tid
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%outgep = getelementptr half, half addrspace(1)* %out, i32 %tid
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%a = load volatile half, half addrspace(1)* %gep0
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%b = load volatile half, half addrspace(1)* %gep1
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%c = load volatile half, half addrspace(1)* %gep2
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%a.nnan = fadd nnan half %a, 1.0
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%b.nnan = fadd nnan half %b, 2.0
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%c.nnan = fadd nnan half %c, 4.0
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%tmp0 = call half @llvm.minnum.f16(half %a.nnan, half %b.nnan)
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%tmp1 = call half @llvm.maxnum.f16(half %a.nnan, half %b.nnan)
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%tmp2 = call half @llvm.minnum.f16(half %tmp1, half %c.nnan)
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%med3 = call half @llvm.maxnum.f16(half %tmp0, half %tmp2)
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store half %med3, half addrspace(1)* %outgep
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare float @llvm.fabs.f32(float) #0
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declare float @llvm.minnum.f32(float, float) #0
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declare float @llvm.maxnum.f32(float, float) #0
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declare double @llvm.minnum.f64(double, double) #0
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declare double @llvm.maxnum.f64(double, double) #0
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declare half @llvm.fabs.f16(half) #0
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declare half @llvm.minnum.f16(half, half) #0
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declare half @llvm.maxnum.f16(half, half) #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind "unsafe-fp-math"="false" "no-nans-fp-math"="false" }
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39
test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.f16.ll
Normal file
39
test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.f16.ll
Normal file
@ -0,0 +1,39 @@
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; RUN: llc -march=amdgcn -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_fmed3_f16:
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; GCN: v_med3_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define void @test_fmed3_f16(half addrspace(1)* %out, i32 %src0.arg, i32 %src1.arg, i32 %src2.arg) #1 {
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%src0.f16 = trunc i32 %src0.arg to i16
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%src0 = bitcast i16 %src0.f16 to half
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%src1.f16 = trunc i32 %src1.arg to i16
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%src1 = bitcast i16 %src1.f16 to half
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%src2.f16 = trunc i32 %src2.arg to i16
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%src2 = bitcast i16 %src2.f16 to half
|
||||
%mad = call half @llvm.amdgcn.fmed3.f16(half %src0, half %src1, half %src2)
|
||||
store half %mad, half addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_fmed3_srcmods_f16:
|
||||
; GCN: v_med3_f16 v{{[0-9]+}}, -s{{[0-9]+}}, |v{{[0-9]+}}|, -|v{{[0-9]+}}|
|
||||
define void @test_fmed3_srcmods_f16(half addrspace(1)* %out, i32 %src0.arg, i32 %src1.arg, i32 %src2.arg) #1 {
|
||||
%src0.f16 = trunc i32 %src0.arg to i16
|
||||
%src0 = bitcast i16 %src0.f16 to half
|
||||
%src1.f16 = trunc i32 %src1.arg to i16
|
||||
%src1 = bitcast i16 %src1.f16 to half
|
||||
%src2.f16 = trunc i32 %src2.arg to i16
|
||||
%src2 = bitcast i16 %src2.f16 to half
|
||||
%src0.fneg = fsub half -0.0, %src0
|
||||
%src1.fabs = call half @llvm.fabs.f16(half %src1)
|
||||
%src2.fabs = call half @llvm.fabs.f16(half %src2)
|
||||
%src2.fneg.fabs = fsub half -0.0, %src2.fabs
|
||||
%mad = call half @llvm.amdgcn.fmed3.f16(half %src0.fneg, half %src1.fabs, half %src2.fneg.fabs)
|
||||
store half %mad, half addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
declare half @llvm.amdgcn.fmed3.f16(half, half, half) #0
|
||||
declare half @llvm.fabs.f16(half) #0
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind }
|
||||
@ -1,12 +1,13 @@
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=SI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=VI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
|
||||
|
||||
declare i32 @llvm.r600.read.tidig.x() #0
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #0
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i32:
|
||||
; GCN: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
|
||||
define void @v_test_smed3_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
@ -25,7 +26,7 @@ define void @v_test_smed3_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a
|
||||
; GCN: v_max_i32
|
||||
; GCN: v_min_i32
|
||||
define void @v_test_smed3_multi_use_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
@ -45,7 +46,7 @@ define void @v_test_smed3_multi_use_r_i_i_i32(i32 addrspace(1)* %out, i32 addrsp
|
||||
; GCN: v_max_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
|
||||
; GCN: v_min_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
|
||||
define void @v_test_smed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
@ -64,7 +65,7 @@ define void @v_test_smed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 a
|
||||
; GCN: v_max_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
|
||||
; GCN: v_min_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
|
||||
define void @v_test_smed3_r_i_i_sign_mismatch_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
@ -83,7 +84,7 @@ define void @v_test_smed3_r_i_i_sign_mismatch_i32(i32 addrspace(1)* %out, i32 ad
|
||||
; GCN: v_cmp_lt_i64
|
||||
; GCN: v_cmp_gt_i64
|
||||
define void @v_test_smed3_r_i_i_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
||||
%a = load i64, i64 addrspace(1)* %gep0
|
||||
@ -99,9 +100,10 @@ define void @v_test_smed3_r_i_i_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i16:
|
||||
; GCN: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
|
||||
; SICIVI: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
|
||||
; GFX9: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
|
||||
define void @v_test_smed3_r_i_i_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
|
||||
%a = load i16, i16 addrspace(1)* %gep0
|
||||
@ -362,6 +364,7 @@ bb:
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME: Should keep scalar or not promote
|
||||
; GCN-LABEL: {{^}}s_test_smed3_i16_pat_0:
|
||||
; GCN: s_sext_i32_i16
|
||||
; GCN: s_sext_i32_i16
|
||||
@ -444,6 +447,35 @@ bb:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_smed3_i16_pat_0:
|
||||
; SI: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
|
||||
; FIXME: VI not matching med3
|
||||
; VI: v_min_i16
|
||||
; VI: v_max_i16
|
||||
; VI: v_min_i16
|
||||
; VI: v_max_i16
|
||||
|
||||
; GFX9: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
define void @v_test_smed3_i16_pat_0(i16 addrspace(1)* %arg, i16 addrspace(1)* %out, i16 addrspace(1)* %a.ptr) #1 {
|
||||
bb:
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr inbounds i16, i16 addrspace(1)* %a.ptr, i32 %tid
|
||||
%gep1 = getelementptr inbounds i16, i16 addrspace(1)* %gep0, i32 3
|
||||
%gep2 = getelementptr inbounds i16, i16 addrspace(1)* %gep0, i32 8
|
||||
%out.gep = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid
|
||||
%x = load i16, i16 addrspace(1)* %gep0
|
||||
%y = load i16, i16 addrspace(1)* %gep1
|
||||
%z = load i16, i16 addrspace(1)* %gep2
|
||||
|
||||
%tmp0 = call i16 @smin16(i16 %x, i16 %y)
|
||||
%tmp1 = call i16 @smax16(i16 %x, i16 %y)
|
||||
%tmp2 = call i16 @smin16(i16 %tmp1, i16 %z)
|
||||
%tmp3 = call i16 @smax16(i16 %tmp0, i16 %tmp2)
|
||||
store i16 %tmp3, i16 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind }
|
||||
attributes #2 = { nounwind readnone alwaysinline }
|
||||
|
||||
@ -1,12 +1,13 @@
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=SI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=VI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
|
||||
|
||||
declare i32 @llvm.r600.read.tidig.x() #0
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #0
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_umed3_r_i_i_i32:
|
||||
; GCN: v_med3_u32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
|
||||
define void @v_test_umed3_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
@ -25,7 +26,7 @@ define void @v_test_umed3_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a
|
||||
; GCN: v_max_u32
|
||||
; GCN: v_min_u32
|
||||
define void @v_test_umed3_multi_use_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
@ -45,7 +46,7 @@ define void @v_test_umed3_multi_use_r_i_i_i32(i32 addrspace(1)* %out, i32 addrsp
|
||||
; GCN: v_max_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
|
||||
; GCN: v_min_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
|
||||
define void @v_test_umed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
@ -64,7 +65,7 @@ define void @v_test_umed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 a
|
||||
; GCN: v_max_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
|
||||
; GCN: v_min_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
|
||||
define void @v_test_umed3_r_i_i_sign_mismatch_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32, i32 addrspace(1)* %gep0
|
||||
@ -83,7 +84,7 @@ define void @v_test_umed3_r_i_i_sign_mismatch_i32(i32 addrspace(1)* %out, i32 ad
|
||||
; GCN: v_cmp_lt_u64
|
||||
; GCN: v_cmp_gt_u64
|
||||
define void @v_test_umed3_r_i_i_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
||||
%a = load i64, i64 addrspace(1)* %gep0
|
||||
@ -99,9 +100,10 @@ define void @v_test_umed3_r_i_i_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_umed3_r_i_i_i16:
|
||||
; GCN: v_med3_u32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
|
||||
; SICIVI: v_med3_u32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
|
||||
; GFX9: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
|
||||
define void @v_test_umed3_r_i_i_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr) #1 {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x()
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
|
||||
%outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
|
||||
%a = load i16, i16 addrspace(1)* %gep0
|
||||
@ -479,6 +481,35 @@ bb:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_test_umed3_i16_pat_0:
|
||||
; SI: v_med3_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
|
||||
; FIXME: VI not matching med3
|
||||
; VI: v_min_u16
|
||||
; VI: v_max_u16
|
||||
; VI: v_min_u16
|
||||
; VI: v_max_u16
|
||||
|
||||
; GFX9: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
define void @v_test_umed3_i16_pat_0(i16 addrspace(1)* %arg, i16 addrspace(1)* %out, i16 addrspace(1)* %a.ptr) #1 {
|
||||
bb:
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr inbounds i16, i16 addrspace(1)* %a.ptr, i32 %tid
|
||||
%gep1 = getelementptr inbounds i16, i16 addrspace(1)* %gep0, i32 3
|
||||
%gep2 = getelementptr inbounds i16, i16 addrspace(1)* %gep0, i32 8
|
||||
%out.gep = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid
|
||||
%x = load i16, i16 addrspace(1)* %gep0
|
||||
%y = load i16, i16 addrspace(1)* %gep1
|
||||
%z = load i16, i16 addrspace(1)* %gep2
|
||||
|
||||
%tmp0 = call i16 @umin16(i16 %x, i16 %y)
|
||||
%tmp1 = call i16 @umax16(i16 %x, i16 %y)
|
||||
%tmp2 = call i16 @umin16(i16 %tmp1, i16 %z)
|
||||
%tmp3 = call i16 @umax16(i16 %tmp0, i16 %tmp2)
|
||||
store i16 %tmp3, i16 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind }
|
||||
attributes #2 = { nounwind readnone alwaysinline }
|
||||
|
||||
@ -30,3 +30,15 @@ v_or3_b32 v1, v2, v3, v4
|
||||
v_pack_b32_f16 v1, v2, v3
|
||||
// GFX9: v_pack_b32_f16 v1, v2, v3 ; encoding: [0x01,0x00,0xa0,0xd2,0x02,0x07,0x02,0x00]
|
||||
// NOVI: :1: error: instruction not supported on this GPU
|
||||
|
||||
v_med3_f16 v1, v2, v3, v4
|
||||
// GFX9: v_med3_f16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xfa,0xd1,0x02,0x07,0x12,0x04]
|
||||
// NOVI: :1: error: instruction not supported on this GPU
|
||||
|
||||
v_med3_i16 v1, v2, v3, v4
|
||||
// GFX9: v_med3_i16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xfb,0xd1,0x02,0x07,0x12,0x04]
|
||||
// NOVI: :1: error: instruction not supported on this GPU
|
||||
|
||||
v_med3_u16 v1, v2, v3, v4
|
||||
// GFX9: v_med3_u16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xfc,0xd1,0x02,0x07,0x12,0x04]
|
||||
// NOVI: :1: error: instruction not supported on this GPU
|
||||
|
||||
Loading…
Reference in New Issue
Block a user