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Fix MRS encoding for arm and thumb.

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llvm-svn: 123778
This commit is contained in:
Bruno Cardoso Lopes 2011-01-18 21:31:35 +00:00
parent 6e4c5af01e
commit 82c6fe3dfe
4 changed files with 13 additions and 5 deletions
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12
lib/Target/ARM/ARMInstrInfo.td
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@ -3827,15 +3827,19 @@ def MRRC2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc,
// Move between special register and ARM core register -- for disassembly only
//
def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
[/* For disassembly only; pattern left blank */]> {
let Inst{23-20} = 0b0000;
bits<4> Rd;
let Inst{23-16} = 0b00001111;
let Inst{15-12} = Rd;
let Inst{7-4} = 0b0000;
}
def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
[/* For disassembly only; pattern left blank */]> {
let Inst{23-20} = 0b0100;
bits<4> Rd;
let Inst{23-16} = 0b01001111;
let Inst{15-12} = Rd;
let Inst{7-4} = 0b0000;
}

1
lib/Target/ARM/ARMInstrThumb2.td
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@ -3290,6 +3290,7 @@ class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
: T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
let Inst{11-8} = Rd;
let Inst{19-16} = 0b1111;
}
def t2MRS : T2MRS<0b111100111110, 0b10, 0,

2
test/MC/ARM/arm_instructions.s
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@ -133,3 +133,5 @@
@ CHECK: isb @ encoding: [0x6f,0xf0,0x7f,0xf5]
isb
@ CHECK: mrs r8, cpsr @ encoding: [0x00,0x80,0x0f,0xe1]
mrs r8, cpsr

3
test/MC/ARM/thumb2.s
View File

@ -166,4 +166,5 @@
bfi r0, r0, #5, #7
@ CHECK: isb @ encoding: [0xbf,0xf3,0x6f,0x8f]
isb
@ CHECK: mrs r0, cpsr @ encoding: [0xef,0xf3,0x00,0x80]
mrs r0, cpsr