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https://github.com/RPCS3/llvm-mirror.git
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Revert r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses."
Caused a hang and eventually an assertion failure in LTO builds of 7zip-benchmark on aarch64 iOS targets. http://green.lab.llvm.org/green/job/lnt-ctmark-aarch64-O3-flto/2024/ llvm-svn: 330063
This commit is contained in:
Peter Collingbourne
parent
ad72037b93
commit
82ccce4b49
@ -743,16 +743,14 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
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if (!GAN)
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return true;
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if (GAN->getOffset() % Size == 0) {
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const GlobalValue *GV = GAN->getGlobal();
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unsigned Alignment = GV->getAlignment();
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Type *Ty = GV->getValueType();
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if (Alignment == 0 && Ty->isSized())
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Alignment = DL.getABITypeAlignment(Ty);
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const GlobalValue *GV = GAN->getGlobal();
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unsigned Alignment = GV->getAlignment();
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Type *Ty = GV->getValueType();
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if (Alignment == 0 && Ty->isSized())
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Alignment = DL.getABITypeAlignment(Ty);
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if (Alignment >= Size)
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return true;
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}
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if (Alignment >= Size)
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return true;
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}
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if (CurDAG->isBaseWithConstantOffset(N)) {
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@ -577,8 +577,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
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setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
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setTargetDAGCombine(ISD::GlobalAddress);
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MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
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MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
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MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
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@ -3679,8 +3677,7 @@ AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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SDValue AArch64TargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
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SelectionDAG &DAG,
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unsigned Flag) const {
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return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty,
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N->getOffset(), Flag);
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return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
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}
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SDValue AArch64TargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
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@ -3755,9 +3752,8 @@ SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
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unsigned char OpFlags =
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Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
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if (OpFlags != AArch64II::MO_NO_FLAG)
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assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
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"unexpected offset in global node");
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assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
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"unexpected offset in global node");
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// This also catches the large code model case for Darwin.
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if ((OpFlags & AArch64II::MO_GOT) != 0) {
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@ -4995,8 +4991,10 @@ SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
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bool AArch64TargetLowering::isOffsetFoldingLegal(
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const GlobalAddressSDNode *GA) const {
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// Offsets are folded in the DAG combine rather than here so that we can
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// intelligently choose an offset based on the uses.
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DEBUG(dbgs() << "Skipping offset folding global address: ");
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DEBUG(GA->dump());
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DEBUG(dbgs() << "AArch64 doesn't support folding offsets into global "
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"addresses\n");
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return false;
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}
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@ -10619,53 +10617,6 @@ static SDValue performNVCASTCombine(SDNode *N) {
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return SDValue();
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}
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// If all users of the globaladdr are of the form (globaladdr + constant), find
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// the smallest constant, fold it into the globaladdr's offset and rewrite the
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// globaladdr as (globaladdr + constant) - constant.
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static SDValue performGlobalAddressCombine(SDNode *N, SelectionDAG &DAG,
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const AArch64Subtarget *Subtarget,
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const TargetMachine &TM) {
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auto *GN = dyn_cast<GlobalAddressSDNode>(N);
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if (!GN || Subtarget->ClassifyGlobalReference(GN->getGlobal(), TM) !=
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AArch64II::MO_NO_FLAG)
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return SDValue();
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uint64_t MinOffset = -1ull;
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for (SDNode *N : GN->uses()) {
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if (N->getOpcode() != ISD::ADD)
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return SDValue();
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auto *C = dyn_cast<ConstantSDNode>(N->getOperand(0));
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if (!C)
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C = dyn_cast<ConstantSDNode>(N->getOperand(1));
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if (!C)
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return SDValue();
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MinOffset = std::min(MinOffset, C->getZExtValue());
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}
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uint64_t Offset = MinOffset + GN->getOffset();
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// Check whether folding this offset is legal. It must not go out of bounds of
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// the referenced object to avoid violating the code model, and must be
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// smaller than 2^21 because this is the largest offset expressible in all
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// object formats.
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//
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// This check also prevents us from folding negative offsets, which will end
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// up being treated in the same way as large positive ones. They could also
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// cause code model violations, and aren't really common enough to matter.
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if (Offset >= (1 << 21))
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return SDValue();
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const GlobalValue *GV = GN->getGlobal();
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Type *T = GV->getValueType();
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if (!T->isSized() ||
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Offset > GV->getParent()->getDataLayout().getTypeAllocSize(T))
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return SDValue();
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SDLoc DL(GN);
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SDValue Result = DAG.getGlobalAddress(GV, DL, MVT::i64, Offset);
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return DAG.getNode(ISD::SUB, DL, MVT::i64, Result,
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DAG.getConstant(MinOffset, DL, MVT::i64));
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}
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SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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@ -10753,8 +10704,6 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
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default:
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break;
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}
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case ISD::GlobalAddress:
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return performGlobalAddressCombine(N, DAG, Subtarget, getTargetMachine());
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}
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return SDValue();
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}
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@ -5,31 +5,32 @@
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; base + offset (imm9)
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; CHECK: @t1
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; CHECK: ldr xzr, [x0, #8]
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; CHECK: ldr xzr, [x{{[0-9]+}}, #8]
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; CHECK: ret
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define void @t1(i64* %object) {
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%incdec.ptr = getelementptr inbounds i64, i64* %object, i64 1
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define void @t1() {
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%incdec.ptr = getelementptr inbounds i64, i64* @object, i64 1
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%tmp = load volatile i64, i64* %incdec.ptr, align 8
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ret void
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}
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; base + offset (> imm9)
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; CHECK: @t2
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; CHECK: sub [[ADDREG:x[0-9]+]], x0, #264
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; CHECK: sub [[ADDREG:x[0-9]+]], x{{[0-9]+}}, #264
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; CHECK: ldr xzr, [
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; CHECK: [[ADDREG]]]
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; CHECK: ret
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define void @t2(i64* %object) {
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%incdec.ptr = getelementptr inbounds i64, i64* %object, i64 -33
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define void @t2() {
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%incdec.ptr = getelementptr inbounds i64, i64* @object, i64 -33
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%tmp = load volatile i64, i64* %incdec.ptr, align 8
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ret void
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}
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; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes)
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; CHECK: @t3
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; CHECK: ldr xzr, [x0, #32760]
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; CHECK: ldr xzr, [x{{[0-9]+}}, #32760]
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; CHECK: ret
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define void @t3(i64* %object) {
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%incdec.ptr = getelementptr inbounds i64, i64* %object, i64 4095
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define void @t3() {
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%incdec.ptr = getelementptr inbounds i64, i64* @object, i64 4095
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%tmp = load volatile i64, i64* %incdec.ptr, align 8
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ret void
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}
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@ -37,10 +38,10 @@ define void @t3(i64* %object) {
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; base + unsigned offset (> imm12 * size of type in bytes)
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; CHECK: @t4
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; CHECK: orr w[[NUM:[0-9]+]], wzr, #0x8000
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; CHECK: ldr xzr, [x0, x[[NUM]]]
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; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
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; CHECK: ret
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define void @t4(i64* %object) {
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%incdec.ptr = getelementptr inbounds i64, i64* %object, i64 4096
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define void @t4() {
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%incdec.ptr = getelementptr inbounds i64, i64* @object, i64 4096
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%tmp = load volatile i64, i64* %incdec.ptr, align 8
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ret void
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}
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@ -57,12 +58,12 @@ define void @t5(i64 %a) {
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; base + reg + imm
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; CHECK: @t6
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; CHECK: add [[ADDREG:x[0-9]+]], x1, x0, lsl #3
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; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, x{{[0-9]+}}, lsl #3
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; CHECK-NEXT: orr w[[NUM:[0-9]+]], wzr, #0x8000
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; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
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; CHECK: ret
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define void @t6(i64 %a, i64* %object) {
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%tmp1 = getelementptr inbounds i64, i64* %object, i64 %a
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define void @t6(i64 %a) {
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%tmp1 = getelementptr inbounds i64, i64* @object, i64 %a
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%incdec.ptr = getelementptr inbounds i64, i64* %tmp1, i64 4096
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%tmp = load volatile i64, i64* %incdec.ptr, align 8
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ret void
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@ -264,196 +264,149 @@ entry:
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; Add a bunch of tests for rdar://13258794: Match LDUR/STUR for D and Q
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; registers for unscaled vector accesses
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@str = global [63 x i8] c"Test case for rdar://13258794: LDUR/STUR for D and Q registers\00", align 1
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define <1 x i64> @fct0(i8* %str) nounwind readonly ssp {
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define <1 x i64> @fct0() nounwind readonly ssp {
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entry:
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; CHECK-LABEL: fct0:
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; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
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%p = getelementptr inbounds i8, i8* %str, i64 3
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%q = bitcast i8* %p to <1 x i64>*
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%0 = load <1 x i64>, <1 x i64>* %q, align 8
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%0 = load <1 x i64>, <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <1 x i64>*), align 8
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ret <1 x i64> %0
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}
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define <2 x i32> @fct1(i8* %str) nounwind readonly ssp {
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define <2 x i32> @fct1() nounwind readonly ssp {
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entry:
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; CHECK-LABEL: fct1:
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; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
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%p = getelementptr inbounds i8, i8* %str, i64 3
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%q = bitcast i8* %p to <2 x i32>*
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%0 = load <2 x i32>, <2 x i32>* %q, align 8
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%0 = load <2 x i32>, <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <2 x i32>*), align 8
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ret <2 x i32> %0
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}
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define <4 x i16> @fct2(i8* %str) nounwind readonly ssp {
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define <4 x i16> @fct2() nounwind readonly ssp {
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entry:
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; CHECK-LABEL: fct2:
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; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
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%p = getelementptr inbounds i8, i8* %str, i64 3
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%q = bitcast i8* %p to <4 x i16>*
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%0 = load <4 x i16>, <4 x i16>* %q, align 8
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%0 = load <4 x i16>, <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <4 x i16>*), align 8
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ret <4 x i16> %0
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}
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define <8 x i8> @fct3(i8* %str) nounwind readonly ssp {
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define <8 x i8> @fct3() nounwind readonly ssp {
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entry:
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; CHECK-LABEL: fct3:
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; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
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%p = getelementptr inbounds i8, i8* %str, i64 3
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%q = bitcast i8* %p to <8 x i8>*
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%0 = load <8 x i8>, <8 x i8>* %q, align 8
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%0 = load <8 x i8>, <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <8 x i8>*), align 8
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ret <8 x i8> %0
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}
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define <2 x i64> @fct4(i8* %str) nounwind readonly ssp {
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define <2 x i64> @fct4() nounwind readonly ssp {
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entry:
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; CHECK-LABEL: fct4:
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; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
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%p = getelementptr inbounds i8, i8* %str, i64 3
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%q = bitcast i8* %p to <2 x i64>*
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%0 = load <2 x i64>, <2 x i64>* %q, align 16
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%0 = load <2 x i64>, <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <2 x i64>*), align 16
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ret <2 x i64> %0
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}
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define <4 x i32> @fct5(i8* %str) nounwind readonly ssp {
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define <4 x i32> @fct5() nounwind readonly ssp {
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entry:
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; CHECK-LABEL: fct5:
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; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
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%p = getelementptr inbounds i8, i8* %str, i64 3
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%q = bitcast i8* %p to <4 x i32>*
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%0 = load <4 x i32>, <4 x i32>* %q, align 16
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%0 = load <4 x i32>, <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <4 x i32>*), align 16
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ret <4 x i32> %0
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}
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define <8 x i16> @fct6(i8* %str) nounwind readonly ssp {
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define <8 x i16> @fct6() nounwind readonly ssp {
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entry:
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; CHECK-LABEL: fct6:
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; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
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%p = getelementptr inbounds i8, i8* %str, i64 3
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%q = bitcast i8* %p to <8 x i16>*
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%0 = load <8 x i16>, <8 x i16>* %q, align 16
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%0 = load <8 x i16>, <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <8 x i16>*), align 16
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ret <8 x i16> %0
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}
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define <16 x i8> @fct7(i8* %str) nounwind readonly ssp {
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define <16 x i8> @fct7() nounwind readonly ssp {
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entry:
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; CHECK-LABEL: fct7:
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; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
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%p = getelementptr inbounds i8, i8* %str, i64 3
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%q = bitcast i8* %p to <16 x i8>*
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%0 = load <16 x i8>, <16 x i8>* %q, align 16
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%0 = load <16 x i8>, <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <16 x i8>*), align 16
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ret <16 x i8> %0
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}
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define void @fct8(i8* %str) nounwind ssp {
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define void @fct8() nounwind ssp {
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entry:
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; CHECK-LABEL: fct8:
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; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
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; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
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%p = getelementptr inbounds i8, i8* %str, i64 3
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%q = bitcast i8* %p to <1 x i64>*
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%0 = load <1 x i64>, <1 x i64>* %q, align 8
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%p2 = getelementptr inbounds i8, i8* %str, i64 4
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%q2 = bitcast i8* %p2 to <1 x i64>*
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store <1 x i64> %0, <1 x i64>* %q2, align 8
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%0 = load <1 x i64>, <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <1 x i64>*), align 8
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store <1 x i64> %0, <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <1 x i64>*), align 8
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ret void
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}
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define void @fct9(i8* %str) nounwind ssp {
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define void @fct9() nounwind ssp {
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entry:
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; CHECK-LABEL: fct9:
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; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
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; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
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%p = getelementptr inbounds i8, i8* %str, i64 3
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%q = bitcast i8* %p to <2 x i32>*
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%0 = load <2 x i32>, <2 x i32>* %q, align 8
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%p2 = getelementptr inbounds i8, i8* %str, i64 4
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%q2 = bitcast i8* %p2 to <2 x i32>*
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store <2 x i32> %0, <2 x i32>* %q2, align 8
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%0 = load <2 x i32>, <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <2 x i32>*), align 8
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store <2 x i32> %0, <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <2 x i32>*), align 8
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ret void
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}
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define void @fct10(i8* %str) nounwind ssp {
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define void @fct10() nounwind ssp {
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entry:
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; CHECK-LABEL: fct10:
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; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
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; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
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%p = getelementptr inbounds i8, i8* %str, i64 3
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%q = bitcast i8* %p to <4 x i16>*
|
||||
%0 = load <4 x i16>, <4 x i16>* %q, align 8
|
||||
%p2 = getelementptr inbounds i8, i8* %str, i64 4
|
||||
%q2 = bitcast i8* %p2 to <4 x i16>*
|
||||
store <4 x i16> %0, <4 x i16>* %q2, align 8
|
||||
%0 = load <4 x i16>, <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <4 x i16>*), align 8
|
||||
store <4 x i16> %0, <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <4 x i16>*), align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fct11(i8* %str) nounwind ssp {
|
||||
define void @fct11() nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: fct11:
|
||||
; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
|
||||
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
|
||||
%p = getelementptr inbounds i8, i8* %str, i64 3
|
||||
%q = bitcast i8* %p to <8 x i8>*
|
||||
%0 = load <8 x i8>, <8 x i8>* %q, align 8
|
||||
%p2 = getelementptr inbounds i8, i8* %str, i64 4
|
||||
%q2 = bitcast i8* %p2 to <8 x i8>*
|
||||
store <8 x i8> %0, <8 x i8>* %q2, align 8
|
||||
%0 = load <8 x i8>, <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <8 x i8>*), align 8
|
||||
store <8 x i8> %0, <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <8 x i8>*), align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fct12(i8* %str) nounwind ssp {
|
||||
define void @fct12() nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: fct12:
|
||||
; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
|
||||
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
|
||||
%p = getelementptr inbounds i8, i8* %str, i64 3
|
||||
%q = bitcast i8* %p to <2 x i64>*
|
||||
%0 = load <2 x i64>, <2 x i64>* %q, align 16
|
||||
%p2 = getelementptr inbounds i8, i8* %str, i64 4
|
||||
%q2 = bitcast i8* %p2 to <2 x i64>*
|
||||
store <2 x i64> %0, <2 x i64>* %q2, align 16
|
||||
%0 = load <2 x i64>, <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <2 x i64>*), align 16
|
||||
store <2 x i64> %0, <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <2 x i64>*), align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fct13(i8* %str) nounwind ssp {
|
||||
define void @fct13() nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: fct13:
|
||||
; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
|
||||
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
|
||||
%p = getelementptr inbounds i8, i8* %str, i64 3
|
||||
%q = bitcast i8* %p to <4 x i32>*
|
||||
%0 = load <4 x i32>, <4 x i32>* %q, align 16
|
||||
%p2 = getelementptr inbounds i8, i8* %str, i64 4
|
||||
%q2 = bitcast i8* %p2 to <4 x i32>*
|
||||
store <4 x i32> %0, <4 x i32>* %q2, align 16
|
||||
%0 = load <4 x i32>, <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <4 x i32>*), align 16
|
||||
store <4 x i32> %0, <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <4 x i32>*), align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fct14(i8* %str) nounwind ssp {
|
||||
define void @fct14() nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: fct14:
|
||||
; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
|
||||
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
|
||||
%p = getelementptr inbounds i8, i8* %str, i64 3
|
||||
%q = bitcast i8* %p to <8 x i16>*
|
||||
%0 = load <8 x i16>, <8 x i16>* %q, align 16
|
||||
%p2 = getelementptr inbounds i8, i8* %str, i64 4
|
||||
%q2 = bitcast i8* %p2 to <8 x i16>*
|
||||
store <8 x i16> %0, <8 x i16>* %q2, align 16
|
||||
%0 = load <8 x i16>, <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <8 x i16>*), align 16
|
||||
store <8 x i16> %0, <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <8 x i16>*), align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fct15(i8* %str) nounwind ssp {
|
||||
define void @fct15() nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: fct15:
|
||||
; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
|
||||
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
|
||||
%p = getelementptr inbounds i8, i8* %str, i64 3
|
||||
%q = bitcast i8* %p to <16 x i8>*
|
||||
%0 = load <16 x i8>, <16 x i8>* %q, align 16
|
||||
%p2 = getelementptr inbounds i8, i8* %str, i64 4
|
||||
%q2 = bitcast i8* %p2 to <16 x i8>*
|
||||
store <16 x i8> %0, <16 x i8>* %q2, align 16
|
||||
%0 = load <16 x i8>, <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <16 x i8>*), align 16
|
||||
store <16 x i8> %0, <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <16 x i8>*), align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
@ -1,59 +0,0 @@
|
||||
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s
|
||||
|
||||
@x1 = external hidden global [2 x i64]
|
||||
@x2 = external hidden global [16777216 x i64]
|
||||
|
||||
define i64 @f1() {
|
||||
; CHECK: f1:
|
||||
; CHECK: adrp x8, x1+16
|
||||
; CHECK: ldr x0, [x8, :lo12:x1+16]
|
||||
%l = load i64, i64* getelementptr ([2 x i64], [2 x i64]* @x1, i64 0, i64 2)
|
||||
ret i64 %l
|
||||
}
|
||||
|
||||
define i64 @f2() {
|
||||
; CHECK: f2:
|
||||
; CHECK: adrp x8, x1
|
||||
; CHECK: add x8, x8, :lo12:x1
|
||||
; CHECK: ldr x0, [x8, #24]
|
||||
%l = load i64, i64* getelementptr ([2 x i64], [2 x i64]* @x1, i64 0, i64 3)
|
||||
ret i64 %l
|
||||
}
|
||||
|
||||
define i64 @f3() {
|
||||
; CHECK: f3:
|
||||
; CHECK: adrp x8, x1+1
|
||||
; CHECK: add x8, x8, :lo12:x1+1
|
||||
; CHECK: ldr x0, [x8]
|
||||
%l = load i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast ([2 x i64]* @x1 to i8*), i64 1) to i64*)
|
||||
ret i64 %l
|
||||
}
|
||||
|
||||
define [2 x i64] @f4() {
|
||||
; CHECK: f4:
|
||||
; CHECK: adrp x8, x2+8
|
||||
; CHECK: add x8, x8, :lo12:x2+8
|
||||
; CHECK: ldp x0, x1, [x8]
|
||||
%l = load [2 x i64], [2 x i64]* bitcast (i8* getelementptr (i8, i8* bitcast ([16777216 x i64]* @x2 to i8*), i64 8) to [2 x i64]*)
|
||||
ret [2 x i64] %l
|
||||
}
|
||||
|
||||
define i64 @f5() {
|
||||
; CHECK: f5:
|
||||
; CHECK: adrp x8, x2+2097144
|
||||
; CHECK: ldr x0, [x8, :lo12:x2+2097144]
|
||||
; CHECK: ret
|
||||
%l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 262143)
|
||||
ret i64 %l
|
||||
}
|
||||
|
||||
define i64 @f6() {
|
||||
; CHECK: f6:
|
||||
; CHECK: adrp x8, x2
|
||||
; CHECK: add x8, x8, :lo12:x2
|
||||
; CHECK: orr w9, wzr, #0x200000
|
||||
; CHECK: ldr x0, [x8, x9]
|
||||
; CHECK: ret
|
||||
%l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 262144)
|
||||
ret i64 %l
|
||||
}
|
||||
@ -10,8 +10,8 @@ define void @f1(i32 %a1, i32 %a2, i32 %a3) {
|
||||
;CHECK-APPLE-IOS: adrp x8, __MergedGlobals_x@PAGE
|
||||
;CHECK-APPLE-IOS-NOT: adrp
|
||||
;CHECK-APPLE-IOS: add x8, x8, __MergedGlobals_x@PAGEOFF
|
||||
;CHECK-APPLE-IOS: adrp x9, __MergedGlobals_y@PAGE+12
|
||||
;CHECK-APPLE-IOS: str w1, [x9, __MergedGlobals_y@PAGEOFF+12]
|
||||
;CHECK-APPLE-IOS: adrp x9, __MergedGlobals_y@PAGE
|
||||
;CHECK-APPLE-IOS: add x9, x9, __MergedGlobals_y@PAGEOFF
|
||||
%x3 = getelementptr inbounds [1000 x i32], [1000 x i32]* @x, i32 0, i64 3
|
||||
%y3 = getelementptr inbounds [1000 x i32], [1000 x i32]* @y, i32 0, i64 3
|
||||
store i32 %a1, i32* %x3, align 4
|
||||
|
||||
@ -44,9 +44,9 @@ define void @f2(i32 %a1, i32 %a2) nounwind {
|
||||
|
||||
; CHECK-LABEL: f3:
|
||||
define void @f3(i32 %a1, i32 %a2) minsize nounwind {
|
||||
; CHECK-NEXT: adrp x8, [[SET]]@PAGE+8
|
||||
; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF+8
|
||||
; CHECK-NEXT: stp w0, w1, [x8]
|
||||
; CHECK-NEXT: adrp x8, [[SET]]@PAGE
|
||||
; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
|
||||
; CHECK-NEXT: stp w0, w1, [x8, #8]
|
||||
; CHECK-NEXT: ret
|
||||
store i32 %a1, i32* @m3, align 4
|
||||
store i32 %a2, i32* @n3, align 4
|
||||
@ -57,9 +57,10 @@ define void @f3(i32 %a1, i32 %a2) minsize nounwind {
|
||||
|
||||
; CHECK-LABEL: f4:
|
||||
define void @f4(i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: adrp x8, [[SET]]@PAGE+8
|
||||
; CHECK-NEXT: adrp x8, [[SET]]@PAGE
|
||||
; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
|
||||
; CHECK-NEXT: adrp x9, _n4@PAGE
|
||||
; CHECK-NEXT: str w0, [x8, [[SET]]@PAGEOFF+8]
|
||||
; CHECK-NEXT: str w0, [x8, #8]
|
||||
; CHECK-NEXT: str w1, [x9, _n4@PAGEOFF]
|
||||
; CHECK-NEXT: ret
|
||||
store i32 %a1, i32* @m3, align 4
|
||||
|
||||
@ -38,9 +38,9 @@ define void @f2(i32 %a1, i32 %a2, i32 %a3) #0 {
|
||||
|
||||
; CHECK-LABEL: f3:
|
||||
define void @f3(i32 %a1, i32 %a2) #0 {
|
||||
; CHECK-NEXT: adrp x8, [[SET]]@PAGE+12
|
||||
; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF+12
|
||||
; CHECK-NEXT: stp w0, w1, [x8]
|
||||
; CHECK-NEXT: adrp x8, [[SET]]@PAGE
|
||||
; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
|
||||
; CHECK-NEXT: stp w0, w1, [x8, #12]
|
||||
; CHECK-NEXT: ret
|
||||
store i32 %a1, i32* @m2, align 4
|
||||
store i32 %a2, i32* @n2, align 4
|
||||
|
||||
Loading…
Reference in New Issue
Block a user