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[InstCombine, ARM] Convert vld1 to llvm load
Convert a vector load intrinsic into an llvm load instruction. This is beneficial when the underlying object being addressed comes from a constant, since we get constant-folding for free. Differential Revision: https://reviews.llvm.org/D46273 llvm-svn: 333643
This commit is contained in:
Alexandros Lamprineas
parent
99716a5b0e
commit
832288a5c9
@ -1427,6 +1427,28 @@ static Value *simplifyNeonTbl1(const IntrinsicInst &II,
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return Builder.CreateShuffleVector(V1, V2, ShuffleMask);
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return Builder.CreateShuffleVector(V1, V2, ShuffleMask);
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}
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}
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/// Convert a vector load intrinsic into a simple llvm load instruction.
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/// This is beneficial when the underlying object being addressed comes
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/// from a constant, since we get constant-folding for free.
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static Value *simplifyNeonVld1(const IntrinsicInst &II,
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unsigned MemAlign,
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InstCombiner::BuilderTy &Builder) {
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auto *IntrAlign = dyn_cast<ConstantInt>(II.getArgOperand(1));
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if (!IntrAlign)
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return nullptr;
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unsigned Alignment = IntrAlign->getLimitedValue() < MemAlign ?
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MemAlign : IntrAlign->getLimitedValue();
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if (!isPowerOf2_32(Alignment))
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return nullptr;
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auto *BCastInst = Builder.CreateBitCast(II.getArgOperand(0),
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PointerType::get(II.getType(), 0));
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return Builder.CreateAlignedLoad(BCastInst, Alignment);
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}
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// Returns true iff the 2 intrinsics have the same operands, limiting the
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// Returns true iff the 2 intrinsics have the same operands, limiting the
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// comparison to the first NumOperands.
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// comparison to the first NumOperands.
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static bool haveSameOperands(const IntrinsicInst &I, const IntrinsicInst &E,
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static bool haveSameOperands(const IntrinsicInst &I, const IntrinsicInst &E,
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@ -2941,7 +2963,14 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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}
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}
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break;
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break;
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case Intrinsic::arm_neon_vld1:
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case Intrinsic::arm_neon_vld1: {
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unsigned MemAlign = getKnownAlignment(II->getArgOperand(0),
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DL, II, &AC, &DT);
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if (Value *V = simplifyNeonVld1(*II, MemAlign, Builder))
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return replaceInstUsesWith(*II, V);
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break;
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}
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case Intrinsic::arm_neon_vld2:
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case Intrinsic::arm_neon_vld2:
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case Intrinsic::arm_neon_vld3:
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case Intrinsic::arm_neon_vld3:
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case Intrinsic::arm_neon_vld4:
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case Intrinsic::arm_neon_vld4:
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118
test/Transforms/InstCombine/ARM/vld1.ll
Normal file
118
test/Transforms/InstCombine/ARM/vld1.ll
Normal file
@ -0,0 +1,118 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "armv8-arm-none-eabi"
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; Turning a vld1 intrinsic into an llvm load is beneficial
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; when the underlying object being addressed comes from a
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; constant, since we get constant-folding for free.
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; Bail the optimization if the alignment is not a constant.
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define <2 x i64> @vld1_align(i8* %ptr, i32 %align) {
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; CHECK-LABEL: @vld1_align(
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; CHECK-NEXT: [[VLD1:%.*]] = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* [[PTR:%.*]], i32 [[ALIGN:%.*]])
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; CHECK-NEXT: ret <2 x i64> [[VLD1]]
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;
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%vld1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* %ptr, i32 %align)
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ret <2 x i64> %vld1
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}
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; Bail the optimization if the alignment is not power of 2.
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define <2 x i64> @vld1_align_pow2(i8* %ptr) {
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; CHECK-LABEL: @vld1_align_pow2(
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; CHECK-NEXT: [[VLD1:%.*]] = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* [[PTR:%.*]], i32 3)
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; CHECK-NEXT: ret <2 x i64> [[VLD1]]
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;
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%vld1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* %ptr, i32 3)
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ret <2 x i64> %vld1
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}
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define <8 x i8> @vld1_8x8(i8* %ptr) {
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; CHECK-LABEL: @vld1_8x8(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[PTR:%.*]] to <8 x i8>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
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; CHECK-NEXT: ret <8 x i8> [[TMP2]]
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;
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%vld1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %ptr, i32 1)
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ret <8 x i8> %vld1
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}
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define <4 x i16> @vld1_4x16(i8* %ptr) {
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; CHECK-LABEL: @vld1_4x16(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[PTR:%.*]] to <4 x i16>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, <4 x i16>* [[TMP1]], align 2
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; CHECK-NEXT: ret <4 x i16> [[TMP2]]
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;
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%vld1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %ptr, i32 2)
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ret <4 x i16> %vld1
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}
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define <2 x i32> @vld1_2x32(i8* %ptr) {
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; CHECK-LABEL: @vld1_2x32(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[PTR:%.*]] to <2 x i32>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, <2 x i32>* [[TMP1]], align 4
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; CHECK-NEXT: ret <2 x i32> [[TMP2]]
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;
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%vld1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %ptr, i32 4)
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ret <2 x i32> %vld1
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}
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define <1 x i64> @vld1_1x64(i8* %ptr) {
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; CHECK-LABEL: @vld1_1x64(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[PTR:%.*]] to <1 x i64>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, <1 x i64>* [[TMP1]], align 8
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; CHECK-NEXT: ret <1 x i64> [[TMP2]]
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;
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%vld1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %ptr, i32 8)
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ret <1 x i64> %vld1
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}
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define <8 x i16> @vld1_8x16(i8* %ptr) {
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; CHECK-LABEL: @vld1_8x16(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[PTR:%.*]] to <8 x i16>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
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; CHECK-NEXT: ret <8 x i16> [[TMP2]]
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;
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%vld1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %ptr, i32 2)
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ret <8 x i16> %vld1
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}
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define <16 x i8> @vld1_16x8(i8* %ptr) {
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; CHECK-LABEL: @vld1_16x8(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[PTR:%.*]] to <16 x i8>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* [[TMP1]], align 1
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; CHECK-NEXT: ret <16 x i8> [[TMP2]]
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;
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%vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %ptr, i32 1)
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ret <16 x i8> %vld1
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}
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define <4 x i32> @vld1_4x32(i8* %ptr) {
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; CHECK-LABEL: @vld1_4x32(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[PTR:%.*]] to <4 x i32>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
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; CHECK-NEXT: ret <4 x i32> [[TMP2]]
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;
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%vld1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8* %ptr, i32 4)
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ret <4 x i32> %vld1
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}
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define <2 x i64> @vld1_2x64(i8* %ptr) {
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; CHECK-LABEL: @vld1_2x64(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[PTR:%.*]] to <2 x i64>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 8
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; CHECK-NEXT: ret <2 x i64> [[TMP2]]
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;
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%vld1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* %ptr, i32 8)
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ret <2 x i64> %vld1
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}
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declare <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8*, i32)
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declare <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8*, i32)
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declare <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32)
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declare <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8*, i32)
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declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8*, i32)
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declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8*, i32)
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declare <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8*, i32)
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declare <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8*, i32)
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