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[X86] Swap the 0 and the fudge factor in the constant pool for the 32-bit mode i64->f32/f64/f80 uint_to_fp algorithm.

Browse Source 
This allows us to generate better code for selecting the fixup
to load.

Previously when the sign was set we had to load offset 0. And
when it was clear we had to load offset 4. This required a testl,
setns, zero extend, and finally a mul by 4. By switching the offsets
we can just shift the sign bit into the lsb and multiply it by 4.
This commit is contained in:
Craig Topper 2020-01-14 16:56:17 -08:00
parent 78a5d52036
commit 835f91f74c
15 changed files with 90 additions and 165 deletions
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8
lib/Target/X86/X86ISelLowering.cpp
View File

@ -19377,21 +19377,21 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
MVT::i64, MMO);
Chain = Fild.getValue(1);
APInt FF(32, 0x5F800000ULL);
// Check whether the sign bit is set.
SDValue SignSet = DAG.getSetCC(
dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
Op.getOperand(OpNo), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
// Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
// Build a 64 bit pair (FF, 0) in the constant pool, with FF in the hi bits.
APInt FF(64, 0x5F80000000000000ULL);
SDValue FudgePtr = DAG.getConstantPool(
ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
ConstantInt::get(*DAG.getContext(), FF), PtrVT);
// Get a pointer to FF if the sign bit was set, or to 0 otherwise.
SDValue Zero = DAG.getIntPtrConstant(0, dl);
SDValue Four = DAG.getIntPtrConstant(4, dl);
SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet, Zero, Four);
SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet, Four, Zero);
FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
// Load the value out, extending it from f32 to f80.

6
test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
View File

@ -1886,11 +1886,9 @@ define <4 x float> @test_mm_cvtu64_ss(<4 x float> %__A, i64 %__B) {
; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X86-NEXT: vmovq %xmm1, {{[0-9]+}}(%esp)
; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: testl %eax, %eax
; X86-NEXT: setns %cl
; X86-NEXT: shrl $31, %eax
; X86-NEXT: fildll {{[0-9]+}}(%esp)
; X86-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X86-NEXT: fstps {{[0-9]+}}(%esp)
; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]

6
test/CodeGen/X86/fildll.ll
View File

@ -34,11 +34,9 @@ define fastcc double @uint64_to_fp(i64 %X) {
; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ecx, (%esp)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testl %edx, %edx
; CHECK-NEXT: setns %al
; CHECK-NEXT: shrl $31, %edx
; CHECK-NEXT: fildll (%esp)
; CHECK-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; CHECK-NEXT: fadds {{\.LCPI.*}}(,%edx,4)
; CHECK-NEXT: fstpl {{[0-9]+}}(%esp)
; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ebp, %esp

16
test/CodeGen/X86/fp-cvt.ll
View File

@ -829,11 +829,9 @@ define x86_fp80 @uitofp_fp80_i64(i64 %a0) nounwind {
; X86-NEXT: movl 12(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: setns %al
; X86-NEXT: shrl $31, %ecx
; X86-NEXT: fildll (%esp)
; X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X86-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
; X86-NEXT: retl
@ -843,7 +841,7 @@ define x86_fp80 @uitofp_fp80_i64(i64 %a0) nounwind {
; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: testq %rdi, %rdi
; X64-NEXT: setns %al
; X64-NEXT: sets %al
; X64-NEXT: fildll -{{[0-9]+}}(%rsp)
; X64-NEXT: fadds {{\.LCPI.*}}(,%rax,4)
; X64-NEXT: retq
@ -863,11 +861,9 @@ define x86_fp80 @uitofp_fp80_i64_ld(i64 *%a0) nounwind {
; X86-NEXT: movl 4(%eax), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl %ecx, (%esp)
; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: testl %eax, %eax
; X86-NEXT: setns %cl
; X86-NEXT: shrl $31, %eax
; X86-NEXT: fildll (%esp)
; X86-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
; X86-NEXT: retl
@ -878,7 +874,7 @@ define x86_fp80 @uitofp_fp80_i64_ld(i64 *%a0) nounwind {
; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: testq %rax, %rax
; X64-NEXT: setns %cl
; X64-NEXT: sets %cl
; X64-NEXT: fildll -{{[0-9]+}}(%rsp)
; X64-NEXT: fadds {{\.LCPI.*}}(,%rcx,4)
; X64-NEXT: retq

17
test/CodeGen/X86/fp-intrinsics.ll
View File

@ -2410,11 +2410,9 @@ define double @uifdl(i64 %x) #0 {
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: xorl %eax, %eax
; X87-NEXT: testl %ecx, %ecx
; X87-NEXT: setns %al
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll (%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: addl $20, %esp
@ -2612,11 +2610,9 @@ define float @uiffl(i64 %x) #0 {
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: xorl %eax, %eax
; X87-NEXT: testl %ecx, %ecx
; X87-NEXT: setns %al
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; X87-NEXT: fstps {{[0-9]+}}(%esp)
; X87-NEXT: flds {{[0-9]+}}(%esp)
; X87-NEXT: addl $20, %esp
@ -2627,11 +2623,10 @@ define float @uiffl(i64 %x) #0 {
; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 24
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: setns %al
; X86-SSE-NEXT: shrl $31, %eax
; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp)

22
test/CodeGen/X86/fp-strict-scalar-inttofp.ll
View File

@ -551,11 +551,10 @@ define float @uitofp_i64tof32(i64 %x) #0 {
; SSE-X86-NEXT: .cfi_def_cfa_register %ebp
; SSE-X86-NEXT: andl $-8, %esp
; SSE-X86-NEXT: subl $16, %esp
; SSE-X86-NEXT: movl 12(%ebp), %eax
; SSE-X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE-X86-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; SSE-X86-NEXT: xorl %eax, %eax
; SSE-X86-NEXT: cmpl $0, 12(%ebp)
; SSE-X86-NEXT: setns %al
; SSE-X86-NEXT: shrl $31, %eax
; SSE-X86-NEXT: fildll {{[0-9]+}}(%esp)
; SSE-X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; SSE-X86-NEXT: fstps {{[0-9]+}}(%esp)
@ -592,11 +591,10 @@ define float @uitofp_i64tof32(i64 %x) #0 {
; AVX-X86-NEXT: .cfi_def_cfa_register %ebp
; AVX-X86-NEXT: andl $-8, %esp
; AVX-X86-NEXT: subl $16, %esp
; AVX-X86-NEXT: movl 12(%ebp), %eax
; AVX-X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-X86-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX-X86-NEXT: xorl %eax, %eax
; AVX-X86-NEXT: cmpl $0, 12(%ebp)
; AVX-X86-NEXT: setns %al
; AVX-X86-NEXT: shrl $31, %eax
; AVX-X86-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX-X86-NEXT: fstps {{[0-9]+}}(%esp)
@ -642,11 +640,9 @@ define float @uitofp_i64tof32(i64 %x) #0 {
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: xorl %eax, %eax
; X87-NEXT: testl %ecx, %ecx
; X87-NEXT: setns %al
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; X87-NEXT: fstps {{[0-9]+}}(%esp)
; X87-NEXT: flds {{[0-9]+}}(%esp)
; X87-NEXT: movl %ebp, %esp
@ -1285,11 +1281,9 @@ define double @uitofp_i64tof64(i64 %x) #0 {
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: xorl %eax, %eax
; X87-NEXT: testl %ecx, %ecx
; X87-NEXT: setns %al
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll (%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: movl %ebp, %esp

8
test/CodeGen/X86/fp80-strict-scalar.ll
View File

@ -846,11 +846,9 @@ define x86_fp80 @uint64_to_fp80(i64 %x) #0 {
; X86-NEXT: movl 12(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: setns %al
; X86-NEXT: shrl $31, %ecx
; X86-NEXT: fildll (%esp)
; X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X86-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
; X86-NEXT: .cfi_def_cfa %esp, 4
@ -861,7 +859,7 @@ define x86_fp80 @uint64_to_fp80(i64 %x) #0 {
; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: testq %rdi, %rdi
; X64-NEXT: setns %al
; X64-NEXT: sets %al
; X64-NEXT: fildll -{{[0-9]+}}(%rsp)
; X64-NEXT: fadds {{\.LCPI.*}}(,%rax,4)
; X64-NEXT: retq

5
test/CodeGen/X86/half.ll
View File

@ -362,11 +362,10 @@ define void @test_uitofp_i64(i64 %a, half* %p) #0 {
; CHECK-I686-NEXT: pushl %esi
; CHECK-I686-NEXT: subl $24, %esp
; CHECK-I686-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-I686-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-I686-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-I686-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; CHECK-I686-NEXT: xorl %eax, %eax
; CHECK-I686-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; CHECK-I686-NEXT: setns %al
; CHECK-I686-NEXT: shrl $31, %eax
; CHECK-I686-NEXT: fildll {{[0-9]+}}(%esp)
; CHECK-I686-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; CHECK-I686-NEXT: fstps (%esp)

12
test/CodeGen/X86/pr15309.ll
View File

@ -17,16 +17,12 @@ define void @test_convert_float2_ulong2(<2 x i64>* nocapture %src, <2 x float>*
; CHECK-NEXT: movl %edi, (%esp)
; CHECK-NEXT: movl %esi, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: testl %ecx, %ecx
; CHECK-NEXT: setns %dl
; CHECK-NEXT: shrl $31, %ecx
; CHECK-NEXT: fildll (%esp)
; CHECK-NEXT: fadds {{\.LCPI.*}}(,%edx,4)
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl %esi, %esi
; CHECK-NEXT: setns %cl
; CHECK-NEXT: fildll {{[0-9]+}}(%esp)
; CHECK-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; CHECK-NEXT: shrl $31, %esi
; CHECK-NEXT: fildll {{[0-9]+}}(%esp)
; CHECK-NEXT: fadds {{\.LCPI.*}}(,%esi,4)
; CHECK-NEXT: fstps 84(%eax)
; CHECK-NEXT: fstps 80(%eax)
; CHECK-NEXT: addl $20, %esp

6
test/CodeGen/X86/pr44396.ll
View File

@ -17,13 +17,11 @@ define double @c() nounwind {
; CHECK-NEXT: subl %eax, %esi
; CHECK-NEXT: sbbl %ecx, %edx
; CHECK-NEXT: setb %al
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl %edx, %edx
; CHECK-NEXT: setns %cl
; CHECK-NEXT: movl %esi, (%esp)
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: shrl $31, %edx
; CHECK-NEXT: fildll (%esp)
; CHECK-NEXT: fadds LCPI0_0(,%ecx,4)
; CHECK-NEXT: fadds LCPI0_0(,%edx,4)
; CHECK-NEXT: fstpl {{[0-9]+}}(%esp)
; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
; CHECK-NEXT: fldz

36
test/CodeGen/X86/scalar-int-to-fp.ll
View File

@ -323,11 +323,10 @@ define float @u64_to_f(i64 %a) nounwind {
; AVX512F_32-NEXT: movl %esp, %ebp
; AVX512F_32-NEXT: andl $-8, %esp
; AVX512F_32-NEXT: subl $16, %esp
; AVX512F_32-NEXT: movl 12(%ebp), %eax
; AVX512F_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512F_32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX512F_32-NEXT: xorl %eax, %eax
; AVX512F_32-NEXT: cmpl $0, 12(%ebp)
; AVX512F_32-NEXT: setns %al
; AVX512F_32-NEXT: shrl $31, %eax
; AVX512F_32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F_32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX512F_32-NEXT: fstps {{[0-9]+}}(%esp)
@ -344,11 +343,10 @@ define float @u64_to_f(i64 %a) nounwind {
; SSE2_32-NEXT: movl %esp, %ebp
; SSE2_32-NEXT: andl $-8, %esp
; SSE2_32-NEXT: subl $16, %esp
; SSE2_32-NEXT: movl 12(%ebp), %eax
; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2_32-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; SSE2_32-NEXT: xorl %eax, %eax
; SSE2_32-NEXT: cmpl $0, 12(%ebp)
; SSE2_32-NEXT: setns %al
; SSE2_32-NEXT: shrl $31, %eax
; SSE2_32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE2_32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; SSE2_32-NEXT: fstps {{[0-9]+}}(%esp)
@ -385,11 +383,9 @@ define float @u64_to_f(i64 %a) nounwind {
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: xorl %eax, %eax
; X87-NEXT: testl %ecx, %ecx
; X87-NEXT: setns %al
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; X87-NEXT: fstps {{[0-9]+}}(%esp)
; X87-NEXT: flds {{[0-9]+}}(%esp)
; X87-NEXT: movl %ebp, %esp
@ -656,11 +652,9 @@ define double @u64_to_d(i64 %a) nounwind {
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: xorl %eax, %eax
; X87-NEXT: testl %ecx, %ecx
; X87-NEXT: setns %al
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll (%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: movl %ebp, %esp
@ -760,11 +754,9 @@ define double @u64_to_d_optsize(i64 %a) nounwind optsize {
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: xorl %eax, %eax
; X87-NEXT: testl %ecx, %ecx
; X87-NEXT: setns %al
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll (%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: movl %ebp, %esp
@ -975,11 +967,9 @@ define x86_fp80 @u64_to_x(i64 %a) nounwind {
; CHECK32-NEXT: movl 12(%ebp), %ecx
; CHECK32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; CHECK32-NEXT: movl %eax, (%esp)
; CHECK32-NEXT: xorl %eax, %eax
; CHECK32-NEXT: testl %ecx, %ecx
; CHECK32-NEXT: setns %al
; CHECK32-NEXT: shrl $31, %ecx
; CHECK32-NEXT: fildll (%esp)
; CHECK32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; CHECK32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; CHECK32-NEXT: movl %ebp, %esp
; CHECK32-NEXT: popl %ebp
; CHECK32-NEXT: retl
@ -989,7 +979,7 @@ define x86_fp80 @u64_to_x(i64 %a) nounwind {
; CHECK64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
; CHECK64-NEXT: xorl %eax, %eax
; CHECK64-NEXT: testq %rdi, %rdi
; CHECK64-NEXT: setns %al
; CHECK64-NEXT: sets %al
; CHECK64-NEXT: fildll -{{[0-9]+}}(%rsp)
; CHECK64-NEXT: fadds {{\.LCPI.*}}(,%rax,4)
; CHECK64-NEXT: retq

5
test/CodeGen/X86/uint64-to-float.ll
View File

@ -13,11 +13,10 @@ define float @test(i64 %a) nounwind {
; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $16, %esp
; X86-NEXT: movl 12(%ebp), %eax
; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: cmpl $0, 12(%ebp)
; X86-NEXT: setns %al
; X86-NEXT: shrl $31, %eax
; X86-NEXT: fildll {{[0-9]+}}(%esp)
; X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; X86-NEXT: fstps {{[0-9]+}}(%esp)

36
test/CodeGen/X86/vec-strict-inttofp-128.ll
View File

@ -273,19 +273,15 @@ define <2 x float> @uitofp_v2i64_v2f32(<2 x i64> %x) #0 {
; SSE-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)
; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
; SSE-32-NEXT: movd %xmm1, %eax
; SSE-32-NEXT: xorl %ecx, %ecx
; SSE-32-NEXT: testl %eax, %eax
; SSE-32-NEXT: setns %cl
; SSE-32-NEXT: shrl $31, %eax
; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; SSE-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; SSE-32-NEXT: fstps (%esp)
; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
; SSE-32-NEXT: movd %xmm0, %eax
; SSE-32-NEXT: xorl %ecx, %ecx
; SSE-32-NEXT: testl %eax, %eax
; SSE-32-NEXT: setns %cl
; SSE-32-NEXT: shrl $31, %eax
; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; SSE-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; SSE-32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@ -344,19 +340,15 @@ define <2 x float> @uitofp_v2i64_v2f32(<2 x i64> %x) #0 {
; SSE41-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)
; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
; SSE41-32-NEXT: movd %xmm1, %eax
; SSE41-32-NEXT: xorl %ecx, %ecx
; SSE41-32-NEXT: testl %eax, %eax
; SSE41-32-NEXT: setns %cl
; SSE41-32-NEXT: shrl $31, %eax
; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE41-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; SSE41-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; SSE41-32-NEXT: fstps (%esp)
; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
; SSE41-32-NEXT: movd %xmm0, %eax
; SSE41-32-NEXT: xorl %ecx, %ecx
; SSE41-32-NEXT: testl %eax, %eax
; SSE41-32-NEXT: setns %cl
; SSE41-32-NEXT: shrl $31, %eax
; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE41-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; SSE41-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; SSE41-32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE41-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE41-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@ -414,18 +406,14 @@ define <2 x float> @uitofp_v2i64_v2f32(<2 x i64> %x) #0 {
; AVX-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractps $1, %xmm0, %eax
; AVX-32-NEXT: xorl %ecx, %ecx
; AVX-32-NEXT: testl %eax, %eax
; AVX-32-NEXT: setns %cl
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractps $3, %xmm0, %eax
; AVX-32-NEXT: xorl %ecx, %ecx
; AVX-32-NEXT: testl %eax, %eax
; AVX-32-NEXT: setns %cl
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX-32-NEXT: fstps (%esp)
; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]

24
test/CodeGen/X86/vec-strict-inttofp-256.ll
View File

@ -1004,32 +1004,24 @@ define <4 x float> @uitofp_v4i64_v4f32(<4 x i64> %x) #0 {
; AVX-32-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[2,3,0,1]
; AVX-32-NEXT: vmovlps %xmm2, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractps $1, %xmm0, %eax
; AVX-32-NEXT: xorl %ecx, %ecx
; AVX-32-NEXT: testl %eax, %eax
; AVX-32-NEXT: setns %cl
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX-32-NEXT: fstps (%esp)
; AVX-32-NEXT: vextractps $3, %xmm0, %eax
; AVX-32-NEXT: xorl %ecx, %ecx
; AVX-32-NEXT: testl %eax, %eax
; AVX-32-NEXT: setns %cl
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractps $1, %xmm1, %eax
; AVX-32-NEXT: xorl %ecx, %ecx
; AVX-32-NEXT: testl %eax, %eax
; AVX-32-NEXT: setns %cl
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractps $3, %xmm1, %eax
; AVX-32-NEXT: xorl %ecx, %ecx
; AVX-32-NEXT: testl %eax, %eax
; AVX-32-NEXT: setns %cl
; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]

48
test/CodeGen/X86/vec-strict-inttofp-512.ll
View File

@ -510,60 +510,44 @@ define <8 x float> @uitofp_v8i64_v8f32(<8 x i64> %x) #0 {
; NODQ-32-NEXT: vpermilps {{.*#+}} xmm4 = xmm1[2,3,0,1]
; NODQ-32-NEXT: vmovlps %xmm4, {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vextractps $1, %xmm0, %eax
; NODQ-32-NEXT: xorl %ecx, %ecx
; NODQ-32-NEXT: testl %eax, %eax
; NODQ-32-NEXT: setns %cl
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; NODQ-32-NEXT: fstps (%esp)
; NODQ-32-NEXT: vextractps $3, %xmm0, %eax
; NODQ-32-NEXT: xorl %ecx, %ecx
; NODQ-32-NEXT: testl %eax, %eax
; NODQ-32-NEXT: setns %cl
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vextractps $1, %xmm3, %eax
; NODQ-32-NEXT: xorl %ecx, %ecx
; NODQ-32-NEXT: testl %eax, %eax
; NODQ-32-NEXT: setns %cl
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vextractps $3, %xmm3, %eax
; NODQ-32-NEXT: xorl %ecx, %ecx
; NODQ-32-NEXT: testl %eax, %eax
; NODQ-32-NEXT: setns %cl
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vextractps $1, %xmm2, %eax
; NODQ-32-NEXT: xorl %ecx, %ecx
; NODQ-32-NEXT: testl %eax, %eax
; NODQ-32-NEXT: setns %cl
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vextractps $3, %xmm2, %eax
; NODQ-32-NEXT: xorl %ecx, %ecx
; NODQ-32-NEXT: testl %eax, %eax
; NODQ-32-NEXT: setns %cl
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vextractps $1, %xmm1, %eax
; NODQ-32-NEXT: xorl %ecx, %ecx
; NODQ-32-NEXT: testl %eax, %eax
; NODQ-32-NEXT: setns %cl
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vextractps $3, %xmm1, %eax
; NODQ-32-NEXT: xorl %ecx, %ecx
; NODQ-32-NEXT: testl %eax, %eax
; NODQ-32-NEXT: setns %cl
; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]