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ARM: try harder to detect non-IT eligible instructions

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For many Thumb-1 register register instructions, setting the CPSR is not
permitted inside an IT block.  We would not correctly flag those instructions.
The previous change to identify this scenario was insufficient as it did not
actually catch all the instances.  The current list is formed by manual
inspection of the ARMv6M ARM.

The change to the Thumb2 IT block test is due to the fact that the new more
stringent checking of the MIs results in the If Conversion pass being prevented
from executing (since not all the instructions in the BB are predicable).  This
results in code gen changes.

Thanks to Tim Northover for pointing out that the previous patch was
insufficient and hinting that the use of the v6M ARM would be much easier to use
than the v7 or v8!

llvm-svn: 215382
This commit is contained in:
Saleem Abdulrasool 2014-08-11 20:13:25 +00:00
parent bbd64cd25c
commit 8388ecd074
2 changed files with 49 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -520,11 +520,40 @@ bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
static bool isCPSRDefined(const MachineInstr *MI) {
for (const auto &MO : MI->operands())
if (MO.isReg() && MO.getReg() == ARM::CPSR && (MO.isDef() || !MO.isDead()))
if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef())
return true;
return false;
}
static bool isEligibleForITBlock(const MachineInstr *MI) {
switch (MI->getOpcode()) {
default: return true;
case ARM::tADC: // ADC (register) T1
case ARM::tADDi3: // ADD (immediate) T1
case ARM::tADDi8: // ADD (immediate) T2
case ARM::tADDrr: // ADD (register) T1
case ARM::tAND: // AND (register) T1
case ARM::tASRri: // ASR (immediate) T1
case ARM::tASRrr: // ASR (register) T1
case ARM::tBIC: // BIC (register) T1
case ARM::tEOR: // EOR (register) T1
case ARM::tLSLri: // LSL (immediate) T1
case ARM::tLSLrr: // LSL (register) T1
case ARM::tLSRri: // LSR (immediate) T1
case ARM::tLSRrr: // LSR (register) T1
case ARM::tMUL: // MUL T1
case ARM::tMVN: // MVN (register) T1
case ARM::tORR: // ORR (register) T1
case ARM::tROR: // ROR (register) T1
case ARM::tRSB: // RSB (immediate) T1
case ARM::tSBC: // SBC (register) T1
case ARM::tSUBi3: // SUB (immediate) T1
case ARM::tSUBi8: // SUB (immediate) T2
case ARM::tSUBrr: // SUB (register) T1
return !isCPSRDefined(MI);
}
}
/// isPredicable - Return true if the specified instruction can be predicated.
/// By default, this returns true for every instruction with a
/// PredicateOperand.
@ -532,12 +561,8 @@ bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
if (!MI->isPredicable())
return false;
// The ARM Architecture Reference Manual states that the CPSR may only be
// accessed by MUL in Thumb mode if it is outside an IT block. Thus, if CPSR
// is defined (or clobbered) by this instruction, it is not predicable.
if (MI->getOpcode() == ARM::tMUL || MI->getOpcode() == ARM::t2MUL)
if (isCPSRDefined(MI))
return false;
if (!isEligibleForITBlock(MI))
return false;
ARMFunctionInfo *AFI =
MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();

25
test/CodeGen/ARM/thumb2-it-block.ll
View File

@ -1,15 +1,9 @@
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck -check-prefix CHECK-V7 %s
; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s -check-prefix CHECK-V8
; PR11107
define i32 @test(i32 %a, i32 %b) {
entry:
; CHECK: cmp
; CHECK-NEXT: it mi
; CHECK-NEXT: rsb{{s?}}mi
; CHECK-NEXT: cmp
; CHECK-NEXT: it mi
; CHECK-NEXT: rsb{{s?}}mi
%cmp1 = icmp slt i32 %a, 0
%sub1 = sub nsw i32 0, %a
%abs1 = select i1 %cmp1, i32 %sub1, i32 %a
@ -19,3 +13,18 @@ entry:
%add = add nsw i32 %abs1, %abs2
ret i32 %add
}
; CHECK-V7: cmp
; CHECK-V7-NEXT: it mi
; CHECK-V7-NEXT: rsbmi
; CHECK-V7-NEXT: cmp
; CHECK-V7-NEXT: it mi
; CHECK-V7-NEXT: rsbmi
; CHECK-V8: cmp
; CHECK-V8-NEXT: bpl
; CHECK-V8: rsbs
; CHECK-V8: cmp
; CHECK-V8-NEXT: bpl
; CHECK-V8: rsbs