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[GlobalISel] Allow different types for G_SBFX and G_UBFX operands

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Change the definition of G_SBFX and G_UBFX so that the lsb and width
can have different types than the src and dst operands.

Differential Revision: https://reviews.llvm.org/D99739
This commit is contained in:
Brendon Cahoon 2021-03-30 11:19:29 -04:00
parent 08587aa237
commit 83a227f986
7 changed files with 16 additions and 15 deletions
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4
include/llvm/Target/GenericOpcodes.td
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@ -1382,14 +1382,14 @@ def G_BZERO : GenericInstruction {
// Generic signed bitfield extraction.
def G_SBFX : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src, type0:$lsb, type0:$width);
let InOperandList = (ins type0:$src, type1:$lsb, type1:$width);
let hasSideEffects = false;
}
// Generic unsigned bitfield extraction.
def G_UBFX : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src, type0:$lsb, type0:$width);
let InOperandList = (ins type0:$src, type1:$lsb, type1:$width);
let hasSideEffects = false;
}

3
lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
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@ -715,7 +715,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.lower();
getActionDefinitionsBuilder(G_ROTL).lower();
getActionDefinitionsBuilder({G_SBFX, G_UBFX}).customFor({s32, s64});
getActionDefinitionsBuilder({G_SBFX, G_UBFX})
.customFor({{s32, s32}, {s64, s64}});
computeTables();
verify(*ST.getInstrInfo());

4
test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir
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@ -16,7 +16,7 @@ body: |
; CHECK: %x:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
; CHECK: %sext_inreg:_(s32) = G_SBFX %x, [[C]], [[C1]]
; CHECK: %sext_inreg:_(s32) = G_SBFX %x, [[C]](s32), [[C1]]
; CHECK: $w0 = COPY %sext_inreg(s32)
; CHECK: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
@ -39,7 +39,7 @@ body: |
; CHECK: %x:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
; CHECK: %sext_inreg:_(s32) = G_SBFX %x, [[C]], [[C1]]
; CHECK: %sext_inreg:_(s32) = G_SBFX %x, [[C]](s32), [[C1]]
; CHECK: $w0 = COPY %sext_inreg(s32)
; CHECK: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0

4
test/CodeGen/AArch64/GlobalISel/legalize-sbfx.mir
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@ -10,7 +10,7 @@ body: |
; CHECK: %copy:_(s32) = COPY $w0
; CHECK: %lsb:_(s32) = G_CONSTANT i32 1
; CHECK: %width:_(s32) = G_CONSTANT i32 2
; CHECK: %sbfx:_(s32) = G_SBFX %copy, %lsb, %width
; CHECK: %sbfx:_(s32) = G_SBFX %copy, %lsb(s32), %width
; CHECK: $w0 = COPY %sbfx(s32)
%copy:_(s32) = COPY $w0
%lsb:_(s32) = G_CONSTANT i32 1
@ -27,7 +27,7 @@ body: |
; CHECK: %copy:_(s64) = COPY $x0
; CHECK: %lsb:_(s64) = G_CONSTANT i64 1
; CHECK: %width:_(s64) = G_CONSTANT i64 2
; CHECK: %sbfx:_(s64) = G_SBFX %copy, %lsb, %width
; CHECK: %sbfx:_(s64) = G_SBFX %copy, %lsb(s64), %width
; CHECK: $x0 = COPY %sbfx(s64)
%copy:_(s64) = COPY $x0
%lsb:_(s64) = G_CONSTANT i64 1

4
test/CodeGen/AArch64/GlobalISel/legalize-ubfx.mir
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@ -10,7 +10,7 @@ body: |
; CHECK: %copy:_(s32) = COPY $w0
; CHECK: %lsb:_(s32) = G_CONSTANT i32 1
; CHECK: %width:_(s32) = G_CONSTANT i32 2
; CHECK: %ubfx:_(s32) = G_UBFX %copy, %lsb, %width
; CHECK: %ubfx:_(s32) = G_UBFX %copy, %lsb(s32), %width
; CHECK: $w0 = COPY %ubfx(s32)
%copy:_(s32) = COPY $w0
%lsb:_(s32) = G_CONSTANT i32 1
@ -27,7 +27,7 @@ body: |
; CHECK: %copy:_(s64) = COPY $x0
; CHECK: %lsb:_(s64) = G_CONSTANT i64 1
; CHECK: %width:_(s64) = G_CONSTANT i64 2
; CHECK: %ubfx:_(s64) = G_UBFX %copy, %lsb, %width
; CHECK: %ubfx:_(s64) = G_UBFX %copy, %lsb(s64), %width
; CHECK: $x0 = COPY %ubfx(s64)
%copy:_(s64) = COPY $x0
%lsb:_(s64) = G_CONSTANT i64 1

8
test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
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@ -684,12 +684,12 @@
# DEBUG-NEXT: G_VECREDUCE_UMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_SBFX (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: G_SBFX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_UBFX (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: G_UBFX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# CHECK-NOT: ill-defined

4
unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
View File

@ -414,8 +414,8 @@ TEST_F(AArch64GISelMITest, BuildBitfieldExtract) {
; CHECK: [[COPY0:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: [[UBFX:%[0-9]+]]:_(s64) = G_UBFX [[COPY0]]:_, [[COPY1]]:_, [[COPY2]]:_
; CHECK: [[SBFX:%[0-9]+]]:_(s64) = G_SBFX [[UBFX]]:_, [[COPY0]]:_, [[COPY2]]:_
; CHECK: [[UBFX:%[0-9]+]]:_(s64) = G_UBFX [[COPY0]]:_, [[COPY1]]:_(s64), [[COPY2]]:_
; CHECK: [[SBFX:%[0-9]+]]:_(s64) = G_SBFX [[UBFX]]:_, [[COPY0]]:_(s64), [[COPY2]]:_
)";
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;