mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 11:42:57 +01:00
Several important bug fixes:
(1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops.
(2) Conditional move instructions must distinguish signed and unsigned
condition codes, e.g., MOVLE vs. MOVLEU.
(3) Conditional-move-on-register was using the cond-move-on-cc opcodes,
which produces a valid-looking instruction with bogus registers!
(4) Here's a really cute one: dividing-by-2^k for negative numbers needs to
add 2^k-1 before shifting, not add 1 after shifting. Sadly, these
are the same when k=0 so our poor test case worked fine.
(5) Casting between signed and unsigned values was not correct:
completely reimplemented.
(6) Zero-extension on unsigned values was bogus: I was only doing the
SRL and not the SLLX before it. Don't know WHAT I was thinking!
(7) And the most important class of changes: Sign-extensions on signed values.
Signed values are not sign-extended after ordinary operations,
so they must be sign-extended before the following cases:
-- passing to an external or unknown function
-- returning from a function
-- using as operand 2 of DIV or REM
-- using as either operand of condition-code setting operation
(currently only SUBCC), with smaller than 32-bit operands
Also, a couple of improvements:
(1) Fold cast-to-bool into Not(bool). Need to do this for And, Or, XOR also.
(2) Convert SetCC-Const into a conditional-move-on-register (case 41)
if the constant is 0. This was only being done for branch-on-SetCC-Const
when the branch is folded with the SetCC-Const.
llvm-svn: 7159
This commit is contained in:
Vikram S. Adve
parent
87e97308fd
commit
83dc6ef841
@ -25,6 +25,7 @@
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#include "llvm/Intrinsics.h"
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#include "Support/MathExtras.h"
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#include <math.h>
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#include <algorithm>
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static inline void Add3OperandInstr(unsigned Opcode, InstructionNode* Node,
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std::vector<MachineInstr*>& mvec) {
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@ -429,13 +430,8 @@ ChooseMovFpcciInstruction(const InstructionNode* instrNode)
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}
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// Assumes that SUBcc v1, v2 -> v3 has been executed.
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// In most cases, we want to clear v3 and then follow it by instruction
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// MOVcc 1 -> v3.
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// Set mustClearReg=false if v3 need not be cleared before conditional move.
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// Set valueToMove=0 if we want to conditionally move 0 instead of 1
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// (i.e., we want to test inverse of a condition)
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// (The latter two cases do not seem to arise because SetNE needs nothing.)
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// ChooseMovpcciForSetCC -- Choose a conditional-move instruction
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// based on the type of SetCC operation.
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//
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// WARNING: since this function has only one caller, it always returns
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// the opcode that expects an immediate and a register. If this function
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@ -444,25 +440,58 @@ ChooseMovFpcciInstruction(const InstructionNode* instrNode)
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//
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// It will be necessary to expand convertOpcodeFromRegToImm() to handle the
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// new cases of opcodes.
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//
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static MachineOpCode
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ChooseMovpcciAfterSub(const InstructionNode* instrNode)
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ChooseMovpcciForSetCC(const InstructionNode* instrNode)
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{
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MachineOpCode opCode = V9::INVALID_OPCODE;
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const Type* opType = instrNode->leftChild()->getValue()->getType();
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assert(opType->isIntegral() || isa<PointerType>(opType));
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bool noSign = opType->isUnsigned() || isa<PointerType>(opType);
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switch(instrNode->getInstruction()->getOpcode())
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{
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case Instruction::SetEQ: opCode = V9::MOVEi; break;
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case Instruction::SetLE: opCode = noSign? V9::MOVLEUi : V9::MOVLEi; break;
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case Instruction::SetGE: opCode = noSign? V9::MOVCCi : V9::MOVGEi; break;
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case Instruction::SetLT: opCode = noSign? V9::MOVCSi : V9::MOVLi; break;
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case Instruction::SetGT: opCode = noSign? V9::MOVGUi : V9::MOVGi; break;
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case Instruction::SetNE: opCode = V9::MOVNEi; break;
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default: assert(0 && "Unrecognized LLVM instr!"); break;
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}
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return opCode;
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}
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// ChooseMovpregiForSetCC -- Choose a conditional-move-on-register-value
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// instruction based on the type of SetCC operation. These instructions
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// compare a register with 0 and perform the move is the comparison is true.
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//
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// WARNING: like the previous function, this function it always returns
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// the opcode that expects an immediate and a register. See above.
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//
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static MachineOpCode
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ChooseMovpregiForSetCC(const InstructionNode* instrNode)
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{
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MachineOpCode opCode = V9::INVALID_OPCODE;
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switch(instrNode->getInstruction()->getOpcode())
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{
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case Instruction::SetEQ: opCode = V9::MOVEi; break;
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case Instruction::SetLE: opCode = V9::MOVLEi; break;
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case Instruction::SetGE: opCode = V9::MOVGEi; break;
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case Instruction::SetLT: opCode = V9::MOVLi; break;
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case Instruction::SetGT: opCode = V9::MOVGi; break;
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case Instruction::SetNE: opCode = V9::MOVNEi; break;
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case Instruction::SetEQ: opCode = V9::MOVRZi; break;
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case Instruction::SetLE: opCode = V9::MOVRLEZi; break;
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case Instruction::SetGE: opCode = V9::MOVRGEZi; break;
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case Instruction::SetLT: opCode = V9::MOVRLZi; break;
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case Instruction::SetGT: opCode = V9::MOVRGZi; break;
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case Instruction::SetNE: opCode = V9::MOVRNZi; break;
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default: assert(0 && "Unrecognized VM instr!"); break;
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}
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return opCode;
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}
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static inline MachineOpCode
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ChooseConvertToFloatInstr(OpLabel vopCode, const Type* opType)
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{
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@ -963,27 +992,46 @@ CreateDivConstInstruction(TargetMachine &target,
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Value* shiftOperand;
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if (resultType->isSigned()) {
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// The result may be negative and we need to add one before shifting
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// a negative value. Use:
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// srl i0, 31, x0; add x0, i0, i1 (if i0 is <= 32 bits)
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// or
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// srlx i0, 63, x0; add x0, i0, i1 (if i0 is 64 bits)
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// to compute i1=i0+1 if i0 < 0 and i1=i0 otherwise.
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// For N / 2^k, if the operand N is negative,
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// we need to add (2^k - 1) before right-shifting by k, i.e.,
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//
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TmpInstruction *srlTmp, *addTmp;
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// (N / 2^k) = N >> k, if N >= 0;
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// (N + 2^k - 1) >> k, if N < 0
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//
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// If N is <= 32 bits, use:
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// sra N, 31, t1 // t1 = ~0, if N < 0, 0 else
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// srl t1, 32-k, t2 // t2 = 2^k - 1, if N < 0, 0 else
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// add t2, N, t3 // t3 = N + 2^k -1, if N < 0, N else
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// sra t3, k, result // result = N / 2^k
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//
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// If N is 64 bits, use:
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// srax N, k-1, t1 // t1 = sign bit in high k positions
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// srlx t1, 64-k, t2 // t2 = 2^k - 1, if N < 0, 0 else
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// add t2, N, t3 // t3 = N + 2^k -1, if N < 0, N else
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// sra t3, k, result // result = N / 2^k
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//
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TmpInstruction *sraTmp, *srlTmp, *addTmp;
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MachineCodeForInstruction& mcfi
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= MachineCodeForInstruction::get(destVal);
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srlTmp = new TmpInstruction(mcfi, resultType, LHS, 0, "getSign");
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sraTmp = new TmpInstruction(mcfi, resultType, LHS, 0, "getSign");
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srlTmp = new TmpInstruction(mcfi, resultType, LHS, 0, "getPlus2km1");
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addTmp = new TmpInstruction(mcfi, resultType, LHS, srlTmp,"incIfNeg");
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// Create the SRA or SRAX instruction to get the sign bit
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mvec.push_back(BuildMI((resultType==Type::LongTy) ?
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V9::SRAXi6 : V9::SRAi5, 3)
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.addReg(LHS)
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.addSImm((resultType==Type::LongTy)? pow-1 : 31)
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.addRegDef(sraTmp));
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// Create the SRL or SRLX instruction to get the sign bit
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mvec.push_back(BuildMI((resultType==Type::LongTy) ?
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V9::SRLXi6 : V9::SRLi5, 3)
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.addReg(LHS)
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.addSImm((resultType==Type::LongTy)? 63 : 31)
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.addReg(sraTmp)
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.addSImm((resultType==Type::LongTy)? 64-pow : 32-pow)
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.addRegDef(srlTmp));
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// Create the ADD instruction to add 1 for negative values
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// Create the ADD instruction to add 2^pow-1 for negative values
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mvec.push_back(BuildMI(V9::ADDr, 3).addReg(LHS).addReg(srlTmp)
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.addRegDef(addTmp));
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@ -1441,6 +1489,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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unsigned allocaSize = 0;
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MachineInstr* M, *M2;
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unsigned L;
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bool foldCase = false;
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mvec.clear();
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@ -1489,9 +1538,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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BuildMI(V9::JMPLRETi, 3).addReg(returnAddrTmp).addSImm(8)
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.addMReg(target.getRegInfo().getZeroRegNum(), MOTy::Def);
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// Insert a copy to copy the return value to the appropriate register
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// -- For FP values, create a FMOVS or FMOVD instruction
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// -- For non-FP values, create an add-with-0 instruction
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// If ther is a value to return, we need to:
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// (a) Sign-extend the value if it is smaller than 8 bytes (reg size)
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// (b) Insert a copy to copy the return value to the appropriate reg.
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// -- For FP values, create a FMOVS or FMOVD instruction
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// -- For non-FP values, create an add-with-0 instruction
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//
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if (retVal != NULL) {
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const UltraSparcRegInfo& regInfo =
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@ -1503,19 +1554,39 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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: (unsigned) SparcIntRegClass::i0);
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retRegNum = regInfo.getUnifiedRegNum(regClassID, retRegNum);
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// Create a virtual register to represent it and mark
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// this vreg as being an implicit operand of the ret MI
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// () Insert sign-extension instructions for small signed values.
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//
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Value* retValToUse = retVal;
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if (retType->isIntegral() && retType->isSigned()) {
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unsigned retSize = target.getTargetData().getTypeSize(retType);
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if (retSize <= 4) {
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// create a temporary virtual reg. to hold the sign-extension
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retValToUse = new TmpInstruction(mcfi, retVal);
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// sign-extend retVal and put the result in the temporary reg.
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target.getInstrInfo().CreateSignExtensionInstructions
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(target, returnInstr->getParent()->getParent(),
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retVal, retValToUse, 8*retSize, mvec, mcfi);
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}
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}
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// (b) Now, insert a copy to to the appropriate register:
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// -- For FP values, create a FMOVS or FMOVD instruction
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// -- For non-FP values, create an add-with-0 instruction
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//
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// First, create a virtual register to represent the register and
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// mark this vreg as being an implicit operand of the ret MI.
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TmpInstruction* retVReg =
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new TmpInstruction(mcfi, retVal, NULL, "argReg");
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new TmpInstruction(mcfi, retValToUse, NULL, "argReg");
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retMI->addImplicitRef(retVReg);
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if (retType->isFloatingPoint())
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M = (BuildMI(retType==Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
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.addReg(retVal).addReg(retVReg, MOTy::Def));
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.addReg(retValToUse).addReg(retVReg, MOTy::Def));
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else
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M = (BuildMI(ChooseAddInstructionByType(retType), 3)
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.addReg(retVal).addSImm((int64_t) 0)
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.addReg(retValToUse).addSImm((int64_t) 0)
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.addReg(retVReg, MOTy::Def));
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// Mark the operand with the register it should be assigned
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@ -1667,8 +1738,26 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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assert(0 && "VRegList should never be the topmost non-chain rule");
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break;
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case 21: // bool: Not(bool,reg): Both these are implemented as:
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case 421: // reg: BNot(reg,reg): reg = reg XOR-NOT 0
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case 21: // bool: Not(bool,reg): Compute with a conditional-move-on-reg
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{ // First find the unary operand. It may be left or right, usually right.
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Instruction* notI = subtreeRoot->getInstruction();
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Value* notArg = BinaryOperator::getNotArgument(
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cast<BinaryOperator>(subtreeRoot->getInstruction()));
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unsigned ZeroReg = target.getRegInfo().getZeroRegNum();
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// Unconditionally set register to 0
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mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(notI));
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// Now conditionally move 1 into the register.
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// Mark the register as a use (as well as a def) because the old
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// value will be retained if the condition is false.
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mvec.push_back(BuildMI(V9::MOVRZi, 3).addReg(notArg).addZImm(1)
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.addReg(notI, MOTy::UseAndDef));
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break;
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}
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case 421: // reg: BNot(reg,reg): Compute as reg = reg XOR-NOT 0
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{ // First find the unary operand. It may be left or right, usually right.
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Value* notArg = BinaryOperator::getNotArgument(
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cast<BinaryOperator>(subtreeRoot->getInstruction()));
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@ -1678,11 +1767,28 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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break;
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}
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case 322: // reg: Not(tobool, reg):
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// Fold CAST-TO-BOOL with NOT by inverting the sense of cast-to-bool
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foldCase = true;
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// Just fall through!
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case 22: // reg: ToBoolTy(reg):
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{
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const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
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assert(opType->isIntegral() || isa<PointerType>(opType));
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forwardOperandNum = 0; // forward first operand to user
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Instruction* castI = subtreeRoot->getInstruction();
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Value* opVal = subtreeRoot->leftChild()->getValue();
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assert(opVal->getType()->isIntegral() ||
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isa<PointerType>(opVal->getType()));
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// Unconditionally set register to 0
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mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(castI));
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// Now conditionally move 1 into the register.
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// Mark the register as a use (as well as a def) because the old
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// value will be retained if the condition is false.
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MachineOpCode opCode = foldCase? V9::MOVRZi : V9::MOVRNZi;
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mvec.push_back(BuildMI(opCode, 3).addReg(opVal).addZImm(1)
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.addReg(castI, MOTy::UseAndDef));
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break;
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}
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@ -1692,6 +1798,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 26: // reg: ToShortTy(reg)
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case 27: // reg: ToUIntTy(reg)
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case 28: // reg: ToIntTy(reg)
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case 29: // reg: ToULongTy(reg)
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case 30: // reg: ToLongTy(reg)
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{
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//======================================================================
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// Rules for integer conversions:
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@ -1713,64 +1821,87 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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//
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// Since we assume 2s complement representations, this implies:
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//
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// -- if operand is smaller than destination, zero-extend or sign-extend
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// according to the signedness of the *operand*: source decides.
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// ==> we have to do nothing here!
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// -- If operand is smaller than destination, zero-extend or sign-extend
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// according to the signedness of the *operand*: source decides:
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// (1) If operand is signed, sign-extend it.
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// If dest is unsigned, zero-ext the result!
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// (2) If operand is unsigned, our current invariant is that
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// it's high bits are correct, so zero-extension is not needed.
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//
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// -- if operand is same size as or larger than destination, and the
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// destination is *unsigned*, zero-extend the operand: dest. decides
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//
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// -- if operand is same size as or larger than destination, and the
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// destination is *signed*, the choice is implementation defined:
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// we sign-extend the operand: i.e., again dest. decides.
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// Note: this matches both Sun's cc and gcc3.2.
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// -- If operand is same size as or larger than destination,
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// zero-extend or sign-extend according to the signedness of
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// the *destination*: destination decides:
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// (1) If destination is signed, sign-extend (truncating if needed)
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// This choice is implementation defined. We sign-extend the
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// operand, which matches both Sun's cc and gcc3.2.
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// (2) If destination is unsigned, zero-extend (truncating if needed)
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//======================================================================
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Instruction* destI = subtreeRoot->getInstruction();
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Function* currentFunc = destI->getParent()->getParent();
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MachineCodeForInstruction& mcfi=MachineCodeForInstruction::get(destI);
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Value* opVal = subtreeRoot->leftChild()->getValue();
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const Type* opType = opVal->getType();
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if (opType->isIntegral() || isa<PointerType>(opType)) {
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unsigned opSize = target.getTargetData().getTypeSize(opType);
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unsigned destSize =
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target.getTargetData().getTypeSize(destI->getType());
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if (opSize >= destSize) {
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// Operand is same size as or larger than dest:
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// zero- or sign-extend, according to the signeddness of
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// the destination (see above).
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if (destI->getType()->isSigned())
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target.getInstrInfo().CreateSignExtensionInstructions(target,
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destI->getParent()->getParent(), opVal, destI, 8*destSize,
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mvec, MachineCodeForInstruction::get(destI));
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else
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target.getInstrInfo().CreateZeroExtensionInstructions(target,
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destI->getParent()->getParent(), opVal, destI, 8*destSize,
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mvec, MachineCodeForInstruction::get(destI));
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} else
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forwardOperandNum = 0; // forward first operand to user
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const Type* destType = destI->getType();
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unsigned opSize = target.getTargetData().getTypeSize(opType);
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unsigned destSize = target.getTargetData().getTypeSize(destType);
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bool isIntegral = opType->isIntegral() || isa<PointerType>(opType);
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if (opType == Type::BoolTy ||
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opType == destType ||
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isIntegral && opSize == destSize && opSize == 8) {
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// nothing to do in all these cases
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forwardOperandNum = 0; // forward first operand to user
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} else if (opType->isFloatingPoint()) {
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CreateCodeToConvertFloatToInt(target, opVal, destI, mvec,
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MachineCodeForInstruction::get(destI));
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CreateCodeToConvertFloatToInt(target, opVal, destI, mvec, mcfi);
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if (destI->getType()->isUnsigned())
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maskUnsignedResult = true; // not handled by fp->int code
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} else
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assert(0 && "Unrecognized operand type for convert-to-unsigned");
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break;
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}
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} else if (isIntegral) {
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bool opSigned = opType->isSigned();
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||||
bool destSigned = destType->isSigned();
|
||||
unsigned extSourceInBits = 8 * std::min<unsigned>(opSize, destSize);
|
||||
|
||||
assert(! (opSize == destSize && opSigned == destSigned) &&
|
||||
"How can different int types have same size and signedness?");
|
||||
|
||||
bool signExtend = (opSize < destSize && opSigned ||
|
||||
opSize >= destSize && destSigned);
|
||||
|
||||
bool signAndZeroExtend = (opSize < destSize && destSize < 8u &&
|
||||
opSigned && !destSigned);
|
||||
assert(!signAndZeroExtend || signExtend);
|
||||
|
||||
bool zeroExtendOnly = opSize >= destSize && !destSigned;
|
||||
assert(!zeroExtendOnly || !signExtend);
|
||||
|
||||
if (signExtend) {
|
||||
Value* signExtDest = (signAndZeroExtend
|
||||
? new TmpInstruction(mcfi, destType, opVal)
|
||||
: destI);
|
||||
|
||||
target.getInstrInfo().CreateSignExtensionInstructions
|
||||
(target, currentFunc,opVal,signExtDest,extSourceInBits,mvec,mcfi);
|
||||
|
||||
if (signAndZeroExtend)
|
||||
target.getInstrInfo().CreateZeroExtensionInstructions
|
||||
(target, currentFunc, signExtDest, destI, 8*destSize, mvec, mcfi);
|
||||
}
|
||||
else if (zeroExtendOnly) {
|
||||
target.getInstrInfo().CreateZeroExtensionInstructions
|
||||
(target, currentFunc, opVal, destI, extSourceInBits, mvec, mcfi);
|
||||
}
|
||||
else
|
||||
forwardOperandNum = 0; // forward first operand to user
|
||||
|
||||
case 29: // reg: ToULongTy(reg)
|
||||
case 30: // reg: ToLongTy(reg)
|
||||
{
|
||||
Value* opVal = subtreeRoot->leftChild()->getValue();
|
||||
const Type* opType = opVal->getType();
|
||||
if (opType->isIntegral() || isa<PointerType>(opType))
|
||||
forwardOperandNum = 0; // forward first operand to user
|
||||
else if (opType->isFloatingPoint()) {
|
||||
Instruction* destI = subtreeRoot->getInstruction();
|
||||
CreateCodeToConvertFloatToInt(target, opVal, destI, mvec,
|
||||
MachineCodeForInstruction::get(destI));
|
||||
} else
|
||||
assert(0 && "Unrecognized operand type for convert-to-signed");
|
||||
assert(0 && "Unrecognized operand type for convert-to-integer");
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1914,126 +2045,234 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
// ELSE FALL THROUGH
|
||||
|
||||
case 36: // reg: Div(reg, reg)
|
||||
{
|
||||
maskUnsignedResult = true;
|
||||
Add3OperandInstr(ChooseDivInstruction(target, subtreeRoot),
|
||||
subtreeRoot, mvec);
|
||||
|
||||
// If second operand of divide is smaller than 64 bits, we have
|
||||
// to make sure the unused top bits are correct because they affect
|
||||
// the result. These bits are already correct for unsigned values.
|
||||
// They may be incorrect for signed values, so sign extend to fill in.
|
||||
Instruction* divI = subtreeRoot->getInstruction();
|
||||
Value* divOp2 = subtreeRoot->rightChild()->getValue();
|
||||
Value* divOpToUse = divOp2;
|
||||
if (divOp2->getType()->isSigned()) {
|
||||
unsigned opSize=target.getTargetData().getTypeSize(divOp2->getType());
|
||||
if (opSize < 8) {
|
||||
MachineCodeForInstruction& mcfi=MachineCodeForInstruction::get(divI);
|
||||
divOpToUse = new TmpInstruction(mcfi, divOp2);
|
||||
target.getInstrInfo().
|
||||
CreateSignExtensionInstructions(target,
|
||||
divI->getParent()->getParent(),
|
||||
divOp2, divOpToUse,
|
||||
8*opSize, mvec, mcfi);
|
||||
}
|
||||
}
|
||||
|
||||
mvec.push_back(BuildMI(ChooseDivInstruction(target, subtreeRoot), 3)
|
||||
.addReg(subtreeRoot->leftChild()->getValue())
|
||||
.addReg(divOpToUse)
|
||||
.addRegDef(divI));
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case 37: // reg: Rem(reg, reg)
|
||||
case 237: // reg: Rem(reg, Constant)
|
||||
{
|
||||
maskUnsignedResult = true;
|
||||
Instruction* remInstr = subtreeRoot->getInstruction();
|
||||
|
||||
MachineCodeForInstruction& mcfi=MachineCodeForInstruction::get(remInstr);
|
||||
TmpInstruction* quot = new TmpInstruction(mcfi,
|
||||
subtreeRoot->leftChild()->getValue(),
|
||||
subtreeRoot->rightChild()->getValue());
|
||||
TmpInstruction* prod = new TmpInstruction(mcfi,
|
||||
quot,
|
||||
subtreeRoot->rightChild()->getValue());
|
||||
Instruction* remI = subtreeRoot->getInstruction();
|
||||
Value* divOp1 = subtreeRoot->leftChild()->getValue();
|
||||
Value* divOp2 = subtreeRoot->rightChild()->getValue();
|
||||
|
||||
MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(remI);
|
||||
|
||||
M = BuildMI(ChooseDivInstruction(target, subtreeRoot), 3)
|
||||
.addReg(subtreeRoot->leftChild()->getValue())
|
||||
.addReg(subtreeRoot->rightChild()->getValue())
|
||||
.addRegDef(quot);
|
||||
mvec.push_back(M);
|
||||
// If second operand of divide is smaller than 64 bits, we have
|
||||
// to make sure the unused top bits are correct because they affect
|
||||
// the result. These bits are already correct for unsigned values.
|
||||
// They may be incorrect for signed values, so sign extend to fill in.
|
||||
//
|
||||
Value* divOpToUse = divOp2;
|
||||
if (divOp2->getType()->isSigned()) {
|
||||
unsigned opSize=target.getTargetData().getTypeSize(divOp2->getType());
|
||||
if (opSize < 8) {
|
||||
divOpToUse = new TmpInstruction(mcfi, divOp2);
|
||||
target.getInstrInfo().
|
||||
CreateSignExtensionInstructions(target,
|
||||
remI->getParent()->getParent(),
|
||||
divOp2, divOpToUse,
|
||||
8*opSize, mvec, mcfi);
|
||||
}
|
||||
}
|
||||
|
||||
// Now compute: result = rem V1, V2 as:
|
||||
// result = V1 - (V1 / signExtend(V2)) * signExtend(V2)
|
||||
//
|
||||
TmpInstruction* quot = new TmpInstruction(mcfi, divOp1, divOpToUse);
|
||||
TmpInstruction* prod = new TmpInstruction(mcfi, quot, divOpToUse);
|
||||
|
||||
mvec.push_back(BuildMI(ChooseDivInstruction(target, subtreeRoot), 3)
|
||||
.addReg(divOp1).addReg(divOpToUse).addRegDef(quot));
|
||||
|
||||
unsigned MulOpcode =
|
||||
ChooseMulInstructionByType(subtreeRoot->getInstruction()->getType());
|
||||
Value *MulRHS = subtreeRoot->rightChild()->getValue();
|
||||
M = BuildMI(MulOpcode, 3).addReg(quot).addReg(MulRHS).addReg(prod,
|
||||
MOTy::Def);
|
||||
mvec.push_back(M);
|
||||
mvec.push_back(BuildMI(ChooseMulInstructionByType(remI->getType()), 3)
|
||||
.addReg(quot).addReg(divOpToUse).addRegDef(prod));
|
||||
|
||||
mvec.push_back(BuildMI(ChooseSubInstructionByType(remI->getType()), 3)
|
||||
.addReg(divOp1).addReg(prod).addRegDef(remI));
|
||||
|
||||
unsigned Opcode = ChooseSubInstructionByType(
|
||||
subtreeRoot->getInstruction()->getType());
|
||||
M = BuildMI(Opcode, 3).addReg(subtreeRoot->leftChild()->getValue())
|
||||
.addReg(prod).addRegDef(subtreeRoot->getValue());
|
||||
mvec.push_back(M);
|
||||
break;
|
||||
}
|
||||
|
||||
case 38: // bool: And(bool, bool)
|
||||
case 138: // bool: And(bool, not)
|
||||
case 238: // bool: And(bool, boolconst)
|
||||
case 338: // reg : BAnd(reg, reg)
|
||||
case 538: // reg : BAnd(reg, Constant)
|
||||
Add3OperandInstr(V9::ANDr, subtreeRoot, mvec);
|
||||
break;
|
||||
|
||||
case 138: // bool: And(bool, not)
|
||||
case 438: // bool: BAnd(bool, bnot)
|
||||
{ // Use the argument of NOT as the second argument!
|
||||
// Mark the NOT node so that no code is generated for it.
|
||||
// If the type is boolean, set 1 or 0 in the result register.
|
||||
InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild();
|
||||
Value* notArg = BinaryOperator::getNotArgument(
|
||||
cast<BinaryOperator>(notNode->getInstruction()));
|
||||
notNode->markFoldedIntoParent();
|
||||
Value *LHS = subtreeRoot->leftChild()->getValue();
|
||||
Value *Dest = subtreeRoot->getValue();
|
||||
mvec.push_back(BuildMI(V9::ANDNr, 3).addReg(LHS).addReg(notArg)
|
||||
.addReg(Dest, MOTy::Def));
|
||||
Value *lhs = subtreeRoot->leftChild()->getValue();
|
||||
Value *dest = subtreeRoot->getValue();
|
||||
mvec.push_back(BuildMI(V9::ANDNr, 3).addReg(lhs).addReg(notArg)
|
||||
.addReg(dest, MOTy::Def));
|
||||
|
||||
if (notArg->getType() == Type::BoolTy)
|
||||
{ // set 1 in result register if result of above is non-zero
|
||||
mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
|
||||
.addReg(dest, MOTy::UseAndDef));
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case 39: // bool: Or(bool, bool)
|
||||
case 139: // bool: Or(bool, not)
|
||||
case 239: // bool: Or(bool, boolconst)
|
||||
case 339: // reg : BOr(reg, reg)
|
||||
case 539: // reg : BOr(reg, Constant)
|
||||
Add3OperandInstr(V9::ORr, subtreeRoot, mvec);
|
||||
break;
|
||||
|
||||
case 139: // bool: Or(bool, not)
|
||||
case 439: // bool: BOr(bool, bnot)
|
||||
{ // Use the argument of NOT as the second argument!
|
||||
// Mark the NOT node so that no code is generated for it.
|
||||
// If the type is boolean, set 1 or 0 in the result register.
|
||||
InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild();
|
||||
Value* notArg = BinaryOperator::getNotArgument(
|
||||
cast<BinaryOperator>(notNode->getInstruction()));
|
||||
notNode->markFoldedIntoParent();
|
||||
Value *LHS = subtreeRoot->leftChild()->getValue();
|
||||
Value *Dest = subtreeRoot->getValue();
|
||||
mvec.push_back(BuildMI(V9::ORNr, 3).addReg(LHS).addReg(notArg)
|
||||
.addReg(Dest, MOTy::Def));
|
||||
Value *lhs = subtreeRoot->leftChild()->getValue();
|
||||
Value *dest = subtreeRoot->getValue();
|
||||
|
||||
mvec.push_back(BuildMI(V9::ORNr, 3).addReg(lhs).addReg(notArg)
|
||||
.addReg(dest, MOTy::Def));
|
||||
|
||||
if (notArg->getType() == Type::BoolTy)
|
||||
{ // set 1 in result register if result of above is non-zero
|
||||
mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
|
||||
.addReg(dest, MOTy::UseAndDef));
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case 40: // bool: Xor(bool, bool)
|
||||
case 140: // bool: Xor(bool, not)
|
||||
case 240: // bool: Xor(bool, boolconst)
|
||||
case 340: // reg : BXor(reg, reg)
|
||||
case 540: // reg : BXor(reg, Constant)
|
||||
Add3OperandInstr(V9::XORr, subtreeRoot, mvec);
|
||||
break;
|
||||
|
||||
case 140: // bool: Xor(bool, not)
|
||||
case 440: // bool: BXor(bool, bnot)
|
||||
{ // Use the argument of NOT as the second argument!
|
||||
// Mark the NOT node so that no code is generated for it.
|
||||
// If the type is boolean, set 1 or 0 in the result register.
|
||||
InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild();
|
||||
Value* notArg = BinaryOperator::getNotArgument(
|
||||
cast<BinaryOperator>(notNode->getInstruction()));
|
||||
notNode->markFoldedIntoParent();
|
||||
Value *LHS = subtreeRoot->leftChild()->getValue();
|
||||
Value *Dest = subtreeRoot->getValue();
|
||||
mvec.push_back(BuildMI(V9::XNORr, 3).addReg(LHS).addReg(notArg)
|
||||
.addReg(Dest, MOTy::Def));
|
||||
Value *lhs = subtreeRoot->leftChild()->getValue();
|
||||
Value *dest = subtreeRoot->getValue();
|
||||
mvec.push_back(BuildMI(V9::XNORr, 3).addReg(lhs).addReg(notArg)
|
||||
.addReg(dest, MOTy::Def));
|
||||
|
||||
if (notArg->getType() == Type::BoolTy)
|
||||
{ // set 1 in result register if result of above is non-zero
|
||||
mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
|
||||
.addReg(dest, MOTy::UseAndDef));
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 41: // boolconst: SetCC(reg, Constant)
|
||||
case 41: // setCCconst: SetCC(reg, Constant)
|
||||
{ // Comparison is with a constant:
|
||||
//
|
||||
// If the SetCC was folded into the user (parent), it will be
|
||||
// caught above. All other cases are the same as case 42,
|
||||
// so just fall through.
|
||||
// If the bool result must be computed into a register (see below),
|
||||
// and the constant is int ZERO, we can use the MOVR[op] instructions
|
||||
// and avoid the SUBcc instruction entirely.
|
||||
// Otherwise this is just the same as case 42, so just fall through.
|
||||
//
|
||||
// The result of the SetCC must be computed and stored in a register if
|
||||
// it is used outside the current basic block (so it must be computed
|
||||
// as a boolreg) or it is used by anything other than a branch.
|
||||
// We will use a conditional move to do this.
|
||||
//
|
||||
Instruction* setCCInstr = subtreeRoot->getInstruction();
|
||||
bool computeBoolVal = (subtreeRoot->parent() == NULL ||
|
||||
! AllUsesAreBranches(setCCInstr));
|
||||
|
||||
if (computeBoolVal)
|
||||
{
|
||||
InstrTreeNode* constNode = subtreeRoot->rightChild();
|
||||
assert(constNode &&
|
||||
constNode->getNodeType() ==InstrTreeNode::NTConstNode);
|
||||
Constant *constVal = cast<Constant>(constNode->getValue());
|
||||
bool isValidConst;
|
||||
|
||||
if ((constVal->getType()->isInteger()
|
||||
|| isa<PointerType>(constVal->getType()))
|
||||
&& GetConstantValueAsSignedInt(constVal, isValidConst) == 0
|
||||
&& isValidConst)
|
||||
{
|
||||
// That constant is an integer zero after all...
|
||||
// Use a MOVR[op] to compute the boolean result
|
||||
// Unconditionally set register to 0
|
||||
mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0)
|
||||
.addRegDef(setCCInstr));
|
||||
|
||||
// Now conditionally move 1 into the register.
|
||||
// Mark the register as a use (as well as a def) because the old
|
||||
// value will be retained if the condition is false.
|
||||
MachineOpCode movOpCode = ChooseMovpregiForSetCC(subtreeRoot);
|
||||
mvec.push_back(BuildMI(movOpCode, 3)
|
||||
.addReg(subtreeRoot->leftChild()->getValue())
|
||||
.addZImm(1).addReg(setCCInstr, MOTy::UseAndDef));
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
// ELSE FALL THROUGH
|
||||
}
|
||||
|
||||
case 42: // bool: SetCC(reg, reg):
|
||||
{
|
||||
// This generates a SUBCC instruction, putting the difference in a
|
||||
// result reg. if needed, and/or setting a condition code if needed.
|
||||
//
|
||||
Instruction* setCCInstr = subtreeRoot->getInstruction();
|
||||
Value* leftVal = subtreeRoot->leftChild()->getValue();
|
||||
bool isFPCompare = leftVal->getType()->isFloatingPoint();
|
||||
Value* leftVal = subtreeRoot->leftChild()->getValue();
|
||||
Value* rightVal = subtreeRoot->rightChild()->getValue();
|
||||
const Type* opType = leftVal->getType();
|
||||
bool isFPCompare = opType->isFloatingPoint();
|
||||
|
||||
// If the boolean result of the SetCC is used outside the current basic
|
||||
// block (so it must be computed as a boolreg) or is used by anything
|
||||
@ -2058,26 +2297,52 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
setCCInstr->getParent()->getParent(),
|
||||
leftVal->getType(),
|
||||
MachineCodeForInstruction::get(setCCInstr));
|
||||
|
||||
// If the operands are signed values smaller than 4 bytes, then they
|
||||
// must be sign-extended in order to do a valid 32-bit comparison
|
||||
// and get the right result in the 32-bit CC register (%icc).
|
||||
//
|
||||
Value* leftOpToUse = leftVal;
|
||||
Value* rightOpToUse = rightVal;
|
||||
if (opType->isIntegral() && opType->isSigned()) {
|
||||
unsigned opSize = target.getTargetData().getTypeSize(opType);
|
||||
if (opSize < 4) {
|
||||
MachineCodeForInstruction& mcfi =
|
||||
MachineCodeForInstruction::get(setCCInstr);
|
||||
|
||||
// create temporary virtual regs. to hold the sign-extensions
|
||||
leftOpToUse = new TmpInstruction(mcfi, leftVal);
|
||||
rightOpToUse = new TmpInstruction(mcfi, rightVal);
|
||||
|
||||
// sign-extend each operand and put the result in the temporary reg.
|
||||
target.getInstrInfo().CreateSignExtensionInstructions
|
||||
(target, setCCInstr->getParent()->getParent(),
|
||||
leftVal, leftOpToUse, 8*opSize, mvec, mcfi);
|
||||
target.getInstrInfo().CreateSignExtensionInstructions
|
||||
(target, setCCInstr->getParent()->getParent(),
|
||||
rightVal, rightOpToUse, 8*opSize, mvec, mcfi);
|
||||
}
|
||||
}
|
||||
|
||||
if (! isFPCompare) {
|
||||
// Integer condition: set CC and discard result.
|
||||
M = BuildMI(V9::SUBccr, 4)
|
||||
.addReg(subtreeRoot->leftChild()->getValue())
|
||||
.addReg(subtreeRoot->rightChild()->getValue())
|
||||
.addMReg(target.getRegInfo().getZeroRegNum(), MOTy::Def)
|
||||
.addCCReg(tmpForCC, MOTy::Def);
|
||||
mvec.push_back(BuildMI(V9::SUBccr, 4)
|
||||
.addReg(leftOpToUse)
|
||||
.addReg(rightOpToUse)
|
||||
.addMReg(target.getRegInfo().getZeroRegNum(),MOTy::Def)
|
||||
.addCCReg(tmpForCC, MOTy::Def));
|
||||
} else {
|
||||
// FP condition: dest of FCMP should be some FCCn register
|
||||
M = BuildMI(ChooseFcmpInstruction(subtreeRoot), 3)
|
||||
.addCCReg(tmpForCC, MOTy::Def)
|
||||
.addReg(subtreeRoot->leftChild()->getValue())
|
||||
.addReg(subtreeRoot->rightChild()->getValue());
|
||||
mvec.push_back(BuildMI(ChooseFcmpInstruction(subtreeRoot), 3)
|
||||
.addCCReg(tmpForCC, MOTy::Def)
|
||||
.addReg(leftOpToUse)
|
||||
.addReg(rightOpToUse));
|
||||
}
|
||||
mvec.push_back(M);
|
||||
|
||||
if (computeBoolVal) {
|
||||
MachineOpCode movOpCode = (isFPCompare
|
||||
? ChooseMovFpcciInstruction(subtreeRoot)
|
||||
: ChooseMovpcciAfterSub(subtreeRoot));
|
||||
: ChooseMovpcciForSetCC(subtreeRoot));
|
||||
|
||||
// Unconditionally set register to 0
|
||||
M = BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(setCCInstr);
|
||||
@ -2172,8 +2437,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
// This can also handle any intrinsics that are just function calls.
|
||||
//
|
||||
if (! specialIntrinsic) {
|
||||
MachineFunction& MF =
|
||||
MachineFunction::get(callInstr->getParent()->getParent());
|
||||
Function* currentFunc = callInstr->getParent()->getParent();
|
||||
MachineFunction& MF = MachineFunction::get(currentFunc);
|
||||
MachineCodeForInstruction& mcfi =
|
||||
MachineCodeForInstruction::get(callInstr);
|
||||
const UltraSparcRegInfo& regInfo =
|
||||
@ -2211,19 +2476,45 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
new CallArgsDescriptor(callInstr, retAddrReg,isVarArgs,noPrototype);
|
||||
assert(callInstr->getOperand(0) == callee
|
||||
&& "This is assumed in the loop below!");
|
||||
|
||||
|
||||
// Insert sign-extension instructions for small signed values,
|
||||
// if this is an unknown function (i.e., called via a funcptr)
|
||||
// or an external one (i.e., which may not be compiled by llc).
|
||||
//
|
||||
if (calledFunc == NULL || calledFunc->isExternal()) {
|
||||
for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i) {
|
||||
Value* argVal = callInstr->getOperand(i);
|
||||
const Type* argType = argVal->getType();
|
||||
if (argType->isIntegral() && argType->isSigned()) {
|
||||
unsigned argSize = target.getTargetData().getTypeSize(argType);
|
||||
if (argSize <= 4) {
|
||||
// create a temporary virtual reg. to hold the sign-extension
|
||||
TmpInstruction* argExtend = new TmpInstruction(mcfi, argVal);
|
||||
|
||||
// sign-extend argVal and put the result in the temporary reg.
|
||||
target.getInstrInfo().CreateSignExtensionInstructions
|
||||
(target, currentFunc, argVal, argExtend,
|
||||
8*argSize, mvec, mcfi);
|
||||
|
||||
// replace argVal with argExtend in CallArgsDescriptor
|
||||
argDesc->getArgInfo(i-1).replaceArgVal(argExtend);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Insert copy instructions to get all the arguments into
|
||||
// all the places that they need to be.
|
||||
//
|
||||
for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i) {
|
||||
int argNo = i-1;
|
||||
Value* argVal = callInstr->getOperand(i);
|
||||
CallArgInfo& argInfo = argDesc->getArgInfo(argNo);
|
||||
Value* argVal = argInfo.getArgVal(); // don't use callInstr arg here
|
||||
const Type* argType = argVal->getType();
|
||||
unsigned regType = regInfo.getRegType(argType);
|
||||
unsigned argSize = target.getTargetData().getTypeSize(argType);
|
||||
int regNumForArg = TargetRegInfo::getInvalidRegNum();
|
||||
unsigned regClassIDOfArgReg;
|
||||
CallArgInfo& argInfo = argDesc->getArgInfo(argNo);
|
||||
|
||||
// Check for FP arguments to varargs functions.
|
||||
// Any such argument in the first $K$ args must be passed in an
|
||||
@ -2346,7 +2637,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
new TmpInstruction(mcfi, argVal, NULL, "argReg");
|
||||
|
||||
callMI->addImplicitRef(argVReg);
|
||||
|
||||
|
||||
// Generate the reg-to-reg copy into the outgoing arg reg.
|
||||
// -- For FP values, create a FMOVS or FMOVD instruction
|
||||
// -- For non-FP values, create an add-with-0 instruction
|
||||
@ -2357,7 +2648,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
M = (BuildMI(ChooseAddInstructionByType(argType), 3)
|
||||
.addReg(argVal).addSImm((int64_t) 0)
|
||||
.addReg(argVReg, MOTy::Def));
|
||||
|
||||
|
||||
// Mark the operand with the register it should be assigned
|
||||
M->SetRegForOperand(M->getNumOperands()-1, regNumForArg);
|
||||
callMI->SetRegForImplicitRef(callMI->getNumImplicitRefs()-1,
|
||||
@ -2505,20 +2796,43 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
if (dest->getType()->isUnsigned()) {
|
||||
unsigned destSize=target.getTargetData().getTypeSize(dest->getType());
|
||||
if (destSize <= 4) {
|
||||
// Mask high bits. Use a TmpInstruction to represent the
|
||||
// Mask high 64 - N bits, where N = 4*destSize.
|
||||
|
||||
// Use a TmpInstruction to represent the
|
||||
// intermediate result before masking. Since those instructions
|
||||
// have already been generated, go back and substitute tmpI
|
||||
// for dest in the result position of each one of them.
|
||||
TmpInstruction *tmpI =
|
||||
new TmpInstruction(MachineCodeForInstruction::get(dest),
|
||||
dest->getType(), dest, NULL, "maskHi");
|
||||
//
|
||||
MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(dest);
|
||||
TmpInstruction *tmpI = new TmpInstruction(mcfi, dest->getType(),
|
||||
dest, NULL, "maskHi");
|
||||
Value* srlArgToUse = tmpI;
|
||||
|
||||
for (unsigned i=0, N=mvec.size(); i < N; ++i)
|
||||
mvec[i]->substituteValue(dest, tmpI);
|
||||
unsigned numSubst = 0;
|
||||
for (unsigned i=0, N=mvec.size(); i < N; ++i) {
|
||||
bool someArgsWereIgnored = false;
|
||||
numSubst += mvec[i]->substituteValue(dest, tmpI, /*defsOnly*/ true,
|
||||
/*defsAndUses*/ false,
|
||||
someArgsWereIgnored);
|
||||
assert(!someArgsWereIgnored &&
|
||||
"Operand `dest' exists but not replaced: probably bogus!");
|
||||
}
|
||||
assert(numSubst > 0 && "Operand `dest' not replaced: probably bogus!");
|
||||
|
||||
// Left shift 32-N if size (N) is less than 32 bits.
|
||||
// Use another tmp. virtual registe to represent this result.
|
||||
if (destSize < 4) {
|
||||
srlArgToUse = new TmpInstruction(mcfi, dest->getType(),
|
||||
tmpI, NULL, "maskHi2");
|
||||
mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpI)
|
||||
.addZImm(8*(4-destSize))
|
||||
.addReg(srlArgToUse, MOTy::Def));
|
||||
}
|
||||
|
||||
// Logical right shift 32-N to get zero extension in top 64-N bits.
|
||||
mvec.push_back(BuildMI(V9::SRLi5, 3).addReg(srlArgToUse)
|
||||
.addZImm(8*(4-destSize)).addReg(dest, MOTy::Def));
|
||||
|
||||
M = BuildMI(V9::SRLi5, 3).addReg(tmpI).addZImm(8*(4-destSize))
|
||||
.addReg(dest, MOTy::Def);
|
||||
mvec.push_back(M);
|
||||
} else if (destSize < 8) {
|
||||
assert(0 && "Unsupported type size: 32 < size < 64 bits");
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user