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[WebAssembly] Add simd128-unimplemented subtarget feature
This is a second attempt at r350778, which was reverted in r350789. The only change is that the unimplemented-simd128 feature has been renamed simd128-unimplemented, since naming it unimplemented-simd128 somehow made the simd128 feature flag enable the unimplemented-simd128 feature on Windows. llvm-svn: 350791
This commit is contained in:
Thomas Lively
parent
74b18e5174
commit
84039ac021
@ -25,6 +25,13 @@ include "llvm/Target/Target.td"
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def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true",
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"Enable 128-bit SIMD">;
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def FeatureSIMD128Unimplemented :
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SubtargetFeature<"simd128-unimplemented",
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"HasSIMD128Unimplemented", "true",
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"Enable 128-bit SIMD not yet implemented in engines",
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[FeatureSIMD128]>;
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def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
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"Enable Atomics">;
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def FeatureNontrappingFPToInt :
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@ -44,8 +44,6 @@ using namespace PatternMatch;
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#define DEBUG_TYPE "wasm-fastisel"
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extern cl::opt<bool> EnableUnimplementedWasmSIMDInstrs;
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namespace {
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class WebAssemblyFastISel final : public FastISel {
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@ -145,7 +143,7 @@ private:
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break;
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case MVT::v2i64:
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case MVT::v2f64:
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if (Subtarget->hasSIMD128() && EnableUnimplementedWasmSIMDInstrs)
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if (Subtarget->hasSIMD128Unimplemented())
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return VT;
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break;
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default:
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@ -25,8 +25,6 @@ using namespace llvm;
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#define DEBUG_TYPE "wasm-isel"
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extern cl::opt<bool> EnableUnimplementedWasmSIMDInstrs;
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//===--------------------------------------------------------------------===//
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/// WebAssembly-specific code to select WebAssembly machine instructions for
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/// SelectionDAG operations.
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@ -37,12 +37,6 @@ using namespace llvm;
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#define DEBUG_TYPE "wasm-lower"
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// Emit proposed instructions that may not have been implemented in engines
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cl::opt<bool> EnableUnimplementedWasmSIMDInstrs(
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"wasm-enable-unimplemented-simd",
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cl::desc("Emit potentially-unimplemented WebAssembly SIMD instructions"),
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cl::init(false));
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WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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const TargetMachine &TM, const WebAssemblySubtarget &STI)
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: TargetLowering(TM), Subtarget(&STI) {
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@ -70,7 +64,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
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addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
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addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
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if (EnableUnimplementedWasmSIMDInstrs) {
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if (Subtarget->hasSIMD128Unimplemented()) {
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addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
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addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
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}
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@ -135,7 +129,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) {
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setOperationAction(Op, T, Expand);
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}
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if (EnableUnimplementedWasmSIMDInstrs) {
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if (Subtarget->hasSIMD128Unimplemented()) {
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setOperationAction(Op, MVT::v2i64, Expand);
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}
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}
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@ -149,7 +143,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) {
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setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
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}
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if (EnableUnimplementedWasmSIMDInstrs) {
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if (Subtarget->hasSIMD128Unimplemented()) {
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
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}
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@ -160,7 +154,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
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for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL})
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setOperationAction(Op, T, Custom);
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if (EnableUnimplementedWasmSIMDInstrs)
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if (Subtarget->hasSIMD128Unimplemented())
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for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL})
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setOperationAction(Op, MVT::v2i64, Custom);
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}
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@ -170,7 +164,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) {
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for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
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setOperationAction(Op, T, Expand);
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if (EnableUnimplementedWasmSIMDInstrs)
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if (Subtarget->hasSIMD128Unimplemented())
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for (auto T : {MVT::v2i64, MVT::v2f64})
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setOperationAction(Op, T, Expand);
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}
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@ -179,8 +173,10 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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// sign-extend from.
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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if (!Subtarget->hasSignExt()) {
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// Sign extends are legal only when extending a vector extract
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auto Action = Subtarget->hasSIMD128() ? Custom : Expand;
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for (auto T : {MVT::i8, MVT::i16, MVT::i32})
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setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, T, Action);
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}
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for (auto T : MVT::integer_vector_valuetypes())
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setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
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@ -225,7 +221,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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}
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// Expand additional SIMD ops that V8 hasn't implemented yet
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if (Subtarget->hasSIMD128() && !EnableUnimplementedWasmSIMDInstrs) {
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if (Subtarget->hasSIMD128() && !Subtarget->hasSIMD128Unimplemented()) {
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setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
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setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
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}
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@ -236,7 +232,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom);
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}
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if (EnableUnimplementedWasmSIMDInstrs) {
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if (Subtarget->hasSIMD128Unimplemented()) {
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for (auto T : {MVT::v2i64, MVT::v2f64}) {
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom);
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@ -900,6 +896,8 @@ SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
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return LowerAccessVectorElement(Op, DAG);
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case ISD::INTRINSIC_VOID:
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return LowerINTRINSIC_VOID(Op, DAG);
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case ISD::SIGN_EXTEND_INREG:
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return LowerSIGN_EXTEND_INREG(Op, DAG);
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case ISD::VECTOR_SHUFFLE:
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return LowerVECTOR_SHUFFLE(Op, DAG);
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case ISD::SHL:
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@ -1101,6 +1099,22 @@ WebAssemblyTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
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}
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}
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SDValue
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WebAssemblyTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
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SelectionDAG &DAG) const {
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// If sign extension operations are disabled, allow sext_inreg only if operand
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// is a vector extract. SIMD does not depend on sign extension operations, but
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// allowing sext_inreg in this context lets us have simple patterns to select
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// extract_lane_s instructions. Expanding sext_inreg everywhere would be
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// simpler in this file, but would necessitate large and brittle patterns to
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// undo the expansion and select extract_lane_s instructions.
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assert(!Subtarget->hasSignExt() && Subtarget->hasSIMD128());
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if (Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT)
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return Op;
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// Otherwise expand
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return SDValue();
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}
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SDValue
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WebAssemblyTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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SelectionDAG &DAG) const {
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@ -99,6 +99,7 @@ private:
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SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerAccessVectorElement(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
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@ -20,7 +20,9 @@ def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
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def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
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def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
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AssemblerPredicate<"FeatureSIMD128", "simd128">;
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def HasUnimplementedSIMD : Predicate<"EnableUnimplementedWasmSIMDInstrs">;
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def HasUnimplementedSIMD :
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Predicate<"Subtarget->hasSIMD128Unimplemented()">,
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AssemblerPredicate<"FeatureSIMD128Unimplemented", "simd128-unimplemented">;
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def HasAtomics : Predicate<"Subtarget->hasAtomics()">,
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AssemblerPredicate<"FeatureAtomics", "atomics">;
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def HasNontrappingFPToInt :
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@ -30,6 +30,7 @@ namespace llvm {
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class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
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bool HasSIMD128;
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bool HasSIMD128Unimplemented;
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bool HasAtomics;
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bool HasNontrappingFPToInt;
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bool HasSignExt;
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@ -78,6 +79,7 @@ public:
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// Predicates used by WebAssemblyInstrInfo.td.
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bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
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bool hasSIMD128() const { return HasSIMD128; }
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bool hasSIMD128Unimplemented() const { return HasSIMD128Unimplemented; }
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bool hasAtomics() const { return HasAtomics; }
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bool hasNontrappingFPToInt() const { return HasNontrappingFPToInt; }
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bool hasSignExt() const { return HasSignExt; }
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@ -1,13 +1,13 @@
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128-unimplemented | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128-unimplemented -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; check that a non-test run (including explicit locals pass) at least finishes
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; RUN: llc < %s -O0 -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext
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; RUN: llc < %s -O2 -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext
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; RUN: llc < %s -O0 -mattr=+simd128-unimplemented
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; RUN: llc < %s -O2 -mattr=+simd128-unimplemented
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; Test that basic SIMD128 arithmetic operations assemble as expected.
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@ -122,22 +122,14 @@ define <16 x i8> @shr_s_v16i8(<16 x i8> %v, i8 %x) {
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; NO-SIMD128-NOT: i8x16
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; SIMD128-NEXT: .functype shr_s_vec_v16i8 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i8x16.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}}
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; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 24{{$}}
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; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
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; SIMD128-NEXT: i32.const $push[[L3:[0-9]+]]=, 24{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
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; SIMD128-NEXT: i8x16.extract_lane_u $push[[L5:[0-9]+]]=, $1, 0{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
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; SIMD128-NEXT: i8x16.splat $push[[L7:[0-9]+]]=, $pop[[L6]]{{$}}
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; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
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; SIMD128-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
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; Skip 14 lanes
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; SIMD128: i8x16.extract_lane_s $push[[L7:[0-9]+]]=, $0, 15{{$}}
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; SIMD128-NEXT: i32.const $push[[L8:[0-9]+]]=, 24{{$}}
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; SIMD128-NEXT: i32.shl $push[[L9:[0-9]+]]=, $pop[[L7]], $pop[[L8]]{{$}}
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; SIMD128-NEXT: i32.const $push[[L10:[0-9]+]]=, 24{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L11:[0-9]+]]=, $pop[[L9]], $pop[[L10]]{{$}}
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; SIMD128-NEXT: i8x16.extract_lane_u $push[[L12:[0-9]+]]=, $1, 15{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L13:[0-9]+]]=, $pop[[L11]], $pop[[L12]]{{$}}
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; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[L14:[0-9]+]], 15, $pop[[L13]]{{$}}
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; SIMD128: i8x16.extract_lane_s $push[[L0:[0-9]+]]=, $0, 15{{$}}
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; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 15{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
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; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop{{[0-9]+}}, 15, $pop[[L2]]{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <16 x i8> @shr_s_vec_v16i8(<16 x i8> %v, <16 x i8> %x) {
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%a = ashr <16 x i8> %v, %x
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@ -343,22 +335,14 @@ define <8 x i16> @shr_s_v8i16(<8 x i16> %v, i16 %x) {
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; NO-SIMD128-NOT: i16x8
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; SIMD128-NEXT: .functype shr_s_vec_v8i16 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i16x8.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}}
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; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
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; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
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; SIMD128-NEXT: i32.const $push[[L3:[0-9]+]]=, 16{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
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; SIMD128-NEXT: i16x8.extract_lane_u $push[[L5:[0-9]+]]=, $1, 0{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
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; SIMD128-NEXT: i16x8.splat $push[[L7:[0-9]+]]=, $pop[[L6]]{{$}}
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; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
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; SIMD128-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
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; Skip 6 lanes
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; SIMD128: i16x8.extract_lane_s $push[[L7:[0-9]+]]=, $0, 7{{$}}
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; SIMD128-NEXT: i32.const $push[[L8:[0-9]+]]=, 16{{$}}
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; SIMD128-NEXT: i32.shl $push[[L9:[0-9]+]]=, $pop[[L7]], $pop[[L8]]{{$}}
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; SIMD128-NEXT: i32.const $push[[L10:[0-9]+]]=, 16{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L11:[0-9]+]]=, $pop[[L9]], $pop[[L10]]{{$}}
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; SIMD128-NEXT: i16x8.extract_lane_u $push[[L12:[0-9]+]]=, $1, 7{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L13:[0-9]+]]=, $pop[[L11]], $pop[[L12]]{{$}}
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; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[L14:[0-9]+]], 7, $pop[[L13]]{{$}}
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; SIMD128: i16x8.extract_lane_s $push[[L0:[0-9]+]]=, $0, 7{{$}}
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; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 7{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
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; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop{{[0-9]+}}, 7, $pop[[L2]]{{$}}
|
||||
; SIMD128-NEXT: return $pop[[R]]{{$}}
|
||||
define <8 x i16> @shr_s_vec_v8i16(<8 x i16> %v, <8 x i16> %x) {
|
||||
%a = ashr <8 x i16> %v, %x
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128-unimplemented | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
|
||||
; Test that bitcasts between vector types are lowered to zero instructions
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128-unimplemented | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
|
||||
; Test SIMD comparison operators
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128-unimplemented | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
|
||||
; Test that vector float-to-int and int-to-float instructions lower correctly
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128-unimplemented | FileCheck %s
|
||||
|
||||
; Check that store in memory with smaller lanes are loaded and stored
|
||||
; as expected. This is a regression test for part of bug 39275.
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128-unimplemented | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128-unimplemented -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
|
||||
; Test that SIMD128 intrinsics lower as expected. These intrinsics are
|
||||
; only expected to lower successfully if the simd128 attribute is
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128-unimplemented | FileCheck %s
|
||||
|
||||
; Test loads and stores with custom alignment values.
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128-unimplemented | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
|
||||
; Test SIMD loads and stores
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128-unimplemented | FileCheck %s
|
||||
|
||||
; Test that vector selects of various varieties lower correctly to bitselects.
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128-unimplemented | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
|
||||
; Test that vector sign extensions lower to shifts
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128-unimplemented,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128
|
||||
|
||||
; Test that basic SIMD128 vector manipulation operations assemble as expected.
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
|
||||
# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+simd128-unimplemented,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
|
||||
# this one is just here to see if it converts to .o without errors, but doesn't check any output:
|
||||
# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s
|
||||
# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+simd128-unimplemented,+nontrapping-fptoint,+exception-handling < %s
|
||||
|
||||
.text
|
||||
.section .text.main,"",@
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# RUN: llvm-mc -show-encoding -triple=wasm32-unkown-unknown -mattr=+sign-ext,+simd128 < %s | FileCheck %s
|
||||
# RUN: llvm-mc -show-encoding -triple=wasm32-unkown-unknown -mattr=+simd128-unimplemented < %s | FileCheck %s
|
||||
|
||||
main:
|
||||
.functype main () -> ()
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc -wasm-enable-unimplemented-simd -mattr=+sign-ext,+simd128 -filetype=obj %s -o - | obj2yaml | FileCheck %s
|
||||
; RUN: llc -mattr=+simd128-unimplemented -filetype=obj %s -o - | obj2yaml | FileCheck %s
|
||||
|
||||
target triple = "wasm32-unknown-unknown"
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user