RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
Code Issues Projects Releases Wiki Activity

[WebAssembly] Replace @llvm.wasm.popcnt with @llvm.ctpop.v16i8

Browse Source 
Use the standard target-independent intrinsic to take advantage of standard
optimizations.

Differential Revision: https://reviews.llvm.org/D106506
This commit is contained in:
Thomas Lively 2021-07-21 16:45:54 -07:00
parent 2ef5dd8386
commit 8403ff42b3
5 changed files with 10 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
include/llvm/IR/IntrinsicsWebAssembly.td
View File

@ -172,11 +172,6 @@ def int_wasm_pmax :
[LLVMMatchType<0>, LLVMMatchType<0>], [LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable]>; [IntrNoMem, IntrSpeculatable]>;
// TODO: Replace this intrinsic with normal ISel patterns once popcnt is merged
// to the proposal.
def int_wasm_popcnt :
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem, IntrSpeculatable]>;
def int_wasm_extmul_low_signed : def int_wasm_extmul_low_signed :
Intrinsic<[llvm_anyvector_ty], Intrinsic<[llvm_anyvector_ty],
[LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>], [LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>],

3
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
View File

@ -212,6 +212,9 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
setOperationAction(Op, T, Legal); setOperationAction(Op, T, Legal);
// And we have popcnt for i8x16
setOperationAction(ISD::CTPOP, MVT::v16i8, Legal);
// Expand float operations supported for scalars but not SIMD // Expand float operations supported for scalars but not SIMD
for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10,
ISD::FEXP, ISD::FEXP2, ISD::FRINT}) ISD::FEXP, ISD::FEXP2, ISD::FRINT})

2
lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
View File

@ -833,7 +833,7 @@ defm ABS : SIMDUnaryInt<abs, "abs", 96>;
defm NEG : SIMDUnaryInt<ivneg, "neg", 97>; defm NEG : SIMDUnaryInt<ivneg, "neg", 97>;
// Population count: popcnt // Population count: popcnt
defm POPCNT : SIMDUnary<I8x16, int_wasm_popcnt, "popcnt", 0x62>; defm POPCNT : SIMDUnary<I8x16, ctpop, "popcnt", 0x62>;
// Any lane true: any_true // Any lane true: any_true
defm ANYTRUE : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), [], defm ANYTRUE : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), [],

4
test/CodeGen/WebAssembly/simd-intrinsics.ll
View File

@ -78,9 +78,9 @@ define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
; CHECK-NEXT: .functype popcnt_v16i8 (v128) -> (v128){{$}} ; CHECK-NEXT: .functype popcnt_v16i8 (v128) -> (v128){{$}}
; CHECK-NEXT: i8x16.popcnt $push[[R:[0-9]+]]=, $0{{$}} ; CHECK-NEXT: i8x16.popcnt $push[[R:[0-9]+]]=, $0{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}} ; CHECK-NEXT: return $pop[[R]]{{$}}
declare <16 x i8> @llvm.wasm.popcnt(<16 x i8>) declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
define <16 x i8> @popcnt_v16i8(<16 x i8> %x) { define <16 x i8> @popcnt_v16i8(<16 x i8> %x) {
%a = call <16 x i8> @llvm.wasm.popcnt(<16 x i8> %x) %a = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %x)
ret <16 x i8> %a ret <16 x i8> %a
} }

17
test/CodeGen/WebAssembly/simd-unsupported.ll
View File

@ -10,7 +10,7 @@ target triple = "wasm32-unknown-unknown"
; ============================================================================== ; ==============================================================================
; CHECK-LABEL: ctlz_v16i8: ; CHECK-LABEL: ctlz_v16i8:
; CHECK: i32.clz ; CHECK: i8x16.popcnt
declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1)
define <16 x i8> @ctlz_v16i8(<16 x i8> %x) { define <16 x i8> @ctlz_v16i8(<16 x i8> %x) {
%v = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x, i1 false) %v = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x, i1 false)
@ -18,14 +18,14 @@ define <16 x i8> @ctlz_v16i8(<16 x i8> %x) {
} }
; CHECK-LABEL: ctlz_v16i8_undef: ; CHECK-LABEL: ctlz_v16i8_undef:
; CHECK: i32.clz ; CHECK: i8x16.popcnt
define <16 x i8> @ctlz_v16i8_undef(<16 x i8> %x) { define <16 x i8> @ctlz_v16i8_undef(<16 x i8> %x) {
%v = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x, i1 true) %v = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x, i1 true)
ret <16 x i8> %v ret <16 x i8> %v
} }
; CHECK-LABEL: cttz_v16i8: ; CHECK-LABEL: cttz_v16i8:
; CHECK: i32.ctz ; CHECK: i8x16.popcnt
declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1) declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1)
define <16 x i8> @cttz_v16i8(<16 x i8> %x) { define <16 x i8> @cttz_v16i8(<16 x i8> %x) {
%v = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %x, i1 false) %v = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %x, i1 false)
@ -33,21 +33,12 @@ define <16 x i8> @cttz_v16i8(<16 x i8> %x) {
} }
; CHECK-LABEL: cttz_v16i8_undef: ; CHECK-LABEL: cttz_v16i8_undef:
; CHECK: i32.ctz ; CHECK: i8x16.popcnt
define <16 x i8> @cttz_v16i8_undef(<16 x i8> %x) { define <16 x i8> @cttz_v16i8_undef(<16 x i8> %x) {
%v = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %x, i1 true) %v = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %x, i1 true)
ret <16 x i8> %v ret <16 x i8> %v
} }
; CHECK-LABEL: ctpop_v16i8:
; Note: expansion does not use i32.popcnt
; CHECK: v128.and
declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
define <16 x i8> @ctpop_v16i8(<16 x i8> %x) {
%v = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %x)
ret <16 x i8> %v
}
; CHECK-LABEL: sdiv_v16i8: ; CHECK-LABEL: sdiv_v16i8:
; CHECK: i32.div_s ; CHECK: i32.div_s
define <16 x i8> @sdiv_v16i8(<16 x i8> %x, <16 x i8> %y) { define <16 x i8> @sdiv_v16i8(<16 x i8> %x, <16 x i8> %y) {