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[PowerPC] Optimize TLS initial-exec sequence to use X-Form loads/stores
This patch adds new load/store instructions for integer scalar types which can be used for X-Form when fed by add with an @tls relocation. Differential Revision: https://reviews.llvm.org/D43315 llvm-svn: 327635
This commit is contained in:
Zaara Syeda
parent
9dafbecd2e
commit
840541d258
@ -101,6 +101,11 @@ static cl::opt<bool> EnableBranchHint(
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cl::desc("Enable static hinting of branches on ppc"),
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cl::Hidden);
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static cl::opt<bool> EnableTLSOpt(
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"ppc-tls-opt", cl::init(true),
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cl::desc("Enable tls optimization peephole"),
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cl::Hidden);
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enum ICmpInGPRType { ICGPR_All, ICGPR_None, ICGPR_I32, ICGPR_I64,
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ICGPR_NonExtIn, ICGPR_Zext, ICGPR_Sext, ICGPR_ZextI32,
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ICGPR_SextI32, ICGPR_ZextI64, ICGPR_SextI64 };
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@ -199,6 +204,14 @@ namespace {
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bool tryBitPermutation(SDNode *N);
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bool tryIntCompareInGPR(SDNode *N);
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// tryTLSXFormLoad - Convert an ISD::LOAD fed by a PPCISD::ADD_TLS into
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// an X-Form load instruction with the offset being a relocation coming from
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// the PPCISD::ADD_TLS.
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bool tryTLSXFormLoad(LoadSDNode *N);
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// tryTLSXFormStore - Convert an ISD::STORE fed by a PPCISD::ADD_TLS into
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// an X-Form store instruction with the offset being a relocation coming from
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// the PPCISD::ADD_TLS.
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bool tryTLSXFormStore(StoreSDNode *N);
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/// SelectCC - Select a comparison of the specified values with the
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/// specified condition code, returning the CR# of the expression.
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SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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@ -582,6 +595,90 @@ bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
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return false;
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}
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bool PPCDAGToDAGISel::tryTLSXFormStore(StoreSDNode *ST) {
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SDValue Base = ST->getBasePtr();
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if (Base.getOpcode() != PPCISD::ADD_TLS)
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return false;
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SDValue Offset = ST->getOffset();
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if (!Offset.isUndef())
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return false;
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SDLoc dl(ST);
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EVT MemVT = ST->getMemoryVT();
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EVT RegVT = ST->getValue().getValueType();
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unsigned Opcode;
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switch (MemVT.getSimpleVT().SimpleTy) {
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default:
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return false;
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case MVT::i8: {
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Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS;
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break;
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}
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case MVT::i16: {
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Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS;
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break;
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}
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case MVT::i32: {
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Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS;
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break;
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}
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case MVT::i64: {
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Opcode = PPC::STDXTLS;
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break;
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}
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}
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SDValue Chain = ST->getChain();
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SDVTList VTs = ST->getVTList();
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SDValue Ops[] = {ST->getValue(), Base.getOperand(0), Base.getOperand(1),
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Chain};
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SDNode *MN = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
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transferMemOperands(ST, MN);
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ReplaceNode(ST, MN);
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return true;
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}
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bool PPCDAGToDAGISel::tryTLSXFormLoad(LoadSDNode *LD) {
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SDValue Base = LD->getBasePtr();
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if (Base.getOpcode() != PPCISD::ADD_TLS)
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return false;
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SDValue Offset = LD->getOffset();
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if (!Offset.isUndef())
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return false;
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SDLoc dl(LD);
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EVT MemVT = LD->getMemoryVT();
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EVT RegVT = LD->getValueType(0);
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unsigned Opcode;
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switch (MemVT.getSimpleVT().SimpleTy) {
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default:
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return false;
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case MVT::i8: {
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Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS;
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break;
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}
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case MVT::i16: {
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Opcode = (RegVT == MVT::i32) ? PPC::LHZXTLS_32 : PPC::LHZXTLS;
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break;
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}
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case MVT::i32: {
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Opcode = (RegVT == MVT::i32) ? PPC::LWZXTLS_32 : PPC::LWZXTLS;
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break;
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}
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case MVT::i64: {
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Opcode = PPC::LDXTLS;
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break;
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}
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}
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SDValue Chain = LD->getChain();
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SDVTList VTs = LD->getVTList();
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SDValue Ops[] = {Base.getOperand(0), Base.getOperand(1), Chain};
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SDNode *MN = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
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transferMemOperands(LD, MN);
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ReplaceNode(LD, MN);
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return true;
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}
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/// Turn an or of two masked values into the rotate left word immediate then
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/// mask insert (rlwimi) instruction.
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bool PPCDAGToDAGISel::tryBitfieldInsert(SDNode *N) {
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@ -3949,14 +4046,28 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
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}
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}
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case ISD::STORE: {
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// Change TLS initial-exec D-form stores to X-form stores.
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StoreSDNode *ST = cast<StoreSDNode>(N);
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if (EnableTLSOpt && PPCSubTarget->isELFv2ABI() &&
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ST->getAddressingMode() != ISD::PRE_INC)
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if (tryTLSXFormStore(ST))
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return;
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break;
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}
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case ISD::LOAD: {
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// Handle preincrement loads.
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LoadSDNode *LD = cast<LoadSDNode>(N);
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EVT LoadedVT = LD->getMemoryVT();
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// Normal loads are handled by code generated from the .td file.
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if (LD->getAddressingMode() != ISD::PRE_INC)
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if (LD->getAddressingMode() != ISD::PRE_INC) {
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// Change TLS initial-exec D-form loads to X-form loads.
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if (EnableTLSOpt && PPCSubTarget->isELFv2ABI())
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if (tryTLSXFormLoad(LD))
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return;
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break;
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}
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SDValue Offset = LD->getOffset();
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if (Offset.getOpcode() == ISD::TargetConstant ||
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@ -499,7 +499,49 @@ defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB),
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"add $rT, $rA, $rB", IIC_IntSimple,
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[(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
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let mayLoad = 1 in {
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def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
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"lbzx $rD, $rA, $rB", IIC_LdStLoad, []>;
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def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
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"lhzx $rD, $rA, $rB", IIC_LdStLoad, []>;
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def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
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"lwzx $rD, $rA, $rB", IIC_LdStLoad, []>;
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def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
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"ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64;
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def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
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"lbzx $rD, $rA, $rB", IIC_LdStLoad, []>;
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def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
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"lhzx $rD, $rA, $rB", IIC_LdStLoad, []>;
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def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
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"lwzx $rD, $rA, $rB", IIC_LdStLoad, []>;
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}
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let mayStore = 1 in {
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def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
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"stbx $rS, $rA, $rB", IIC_LdStStore, []>,
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PPC970_DGroup_Cracked;
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def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
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"sthx $rS, $rA, $rB", IIC_LdStStore, []>,
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PPC970_DGroup_Cracked;
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def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
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"stwx $rS, $rA, $rB", IIC_LdStStore, []>,
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PPC970_DGroup_Cracked;
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def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
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"stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64,
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PPC970_DGroup_Cracked;
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def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
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"stbx $rS, $rA, $rB", IIC_LdStStore, []>,
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PPC970_DGroup_Cracked;
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def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
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"sthx $rS, $rA, $rB", IIC_LdStStore, []>,
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PPC970_DGroup_Cracked;
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def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
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"stwx $rS, $rA, $rB", IIC_LdStStore, []>,
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PPC970_DGroup_Cracked;
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}
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let isCommutable = 1 in
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defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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"addc", "$rT, $rA, $rB", IIC_IntGeneral,
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169
test/CodeGen/PowerPC/tls-pie-xform.ll
Normal file
169
test/CodeGen/PowerPC/tls-pie-xform.ll
Normal file
@ -0,0 +1,169 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s -check-prefix=CHECK
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@var_char = external thread_local local_unnamed_addr global i8, align 1
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@var_short = external thread_local local_unnamed_addr global i16, align 2
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@var_int = external thread_local local_unnamed_addr global i32, align 4
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@var_long_long = external thread_local local_unnamed_addr global i64, align 8
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define dso_local zeroext i8 @test_char_one() {
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; CHECK-LABEL: test_char_one:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis 3, 2, var_char@got@tprel@ha
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; CHECK-NEXT: ld 3, var_char@got@tprel@l(3)
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; CHECK-NEXT: lbzx 3, 3, var_char@tls
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entry:
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%0 = load i8, i8* @var_char, align 1, !tbaa !4
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ret i8 %0
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}
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define dso_local void @test_char_two(i32 signext %a) {
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; CHECK-LABEL: test_char_two:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis 4, 2, var_char@got@tprel@ha
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; CHECK-NEXT: ld 4, var_char@got@tprel@l(4)
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; CHECK-NEXT: stbx 3, 4, var_char@tls
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entry:
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%conv = trunc i32 %a to i8
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store i8 %conv, i8* @var_char, align 1, !tbaa !4
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ret void
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}
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define dso_local zeroext i8 @test_char_three(i8 zeroext %a) {
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; CHECK-LABEL: test_char_three:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis 4, 2, var_char@got@tprel@ha
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; CHECK-NEXT: ld 4, var_char@got@tprel@l(4)
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; CHECK-NEXT: lbzx 5, 4, var_char@tls
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; CHECK: stbx {{[0-9]+}}, 4, var_char@tls
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entry:
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%0 = load i8, i8* @var_char, align 1, !tbaa !4
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%add = add i8 %0, %a
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store i8 %add, i8* @var_char, align 1, !tbaa !4
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ret i8 %add
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}
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define dso_local signext i16 @test_short_one() {
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; CHECK-LABEL: test_short_one:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis 3, 2, var_short@got@tprel@ha
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; CHECK-NEXT: ld 3, var_short@got@tprel@l(3)
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; CHECK-NEXT: lhzx 3, 3, var_short@tls
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entry:
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%0 = load i16, i16* @var_short, align 2, !tbaa !7
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ret i16 %0
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}
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define dso_local void @test_short_two(i32 signext %a) {
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; CHECK-LABEL: test_short_two:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis 4, 2, var_short@got@tprel@ha
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; CHECK-NEXT: ld 4, var_short@got@tprel@l(4)
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; CHECK-NEXT: sthx 3, 4, var_short@tls
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entry:
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%conv = trunc i32 %a to i16
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store i16 %conv, i16* @var_short, align 2, !tbaa !7
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ret void
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}
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define dso_local signext i16 @test_short_three(i16 signext %a) {
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; CHECK-LABEL: test_short_three:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis 4, 2, var_short@got@tprel@ha
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; CHECK-NEXT: ld 4, var_short@got@tprel@l(4)
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; CHECK-NEXT: lhzx 5, 4, var_short@tls
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; CHECK: sthx {{[0-9]+}}, 4, var_short@tls
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entry:
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%0 = load i16, i16* @var_short, align 2, !tbaa !7
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%add = add i16 %0, %a
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store i16 %add, i16* @var_short, align 2, !tbaa !7
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ret i16 %add
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}
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define dso_local signext i32 @test_int_one() {
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; CHECK-LABEL: test_int_one:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis 3, 2, var_int@got@tprel@ha
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; CHECK-NEXT: ld 3, var_int@got@tprel@l(3)
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; CHECK-NEXT: lwzx 3, 3, var_int@tls
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entry:
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%0 = load i32, i32* @var_int, align 4, !tbaa !9
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ret i32 %0
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}
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define dso_local void @test_int_two(i32 signext %a) {
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; CHECK-LABEL: test_int_two:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis 4, 2, var_int@got@tprel@ha
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; CHECK-NEXT: ld 4, var_int@got@tprel@l(4)
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; CHECK-NEXT: stwx 3, 4, var_int@tls
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entry:
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store i32 %a, i32* @var_int, align 4, !tbaa !9
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ret void
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}
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define dso_local signext i32 @test_int_three(i32 signext %a) {
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; CHECK-LABEL: test_int_three:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis 4, 2, var_int@got@tprel@ha
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; CHECK-NEXT: ld 4, var_int@got@tprel@l(4)
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; CHECK-NEXT: lwzx 5, 4, var_int@tls
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; CHECK: stwx {{[0-9]+}}, 4, var_int@tls
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entry:
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%0 = load i32, i32* @var_int, align 4, !tbaa !9
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%add = add nsw i32 %0, %a
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store i32 %add, i32* @var_int, align 4, !tbaa !9
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ret i32 %add
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}
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define dso_local i64 @test_longlong_one() {
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; CHECK-LABEL: test_longlong_one:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis 3, 2, var_long_long@got@tprel@ha
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; CHECK-NEXT: ld 3, var_long_long@got@tprel@l(3)
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; CHECK-NEXT: ldx 3, 3, var_long_long@tls
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entry:
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%0 = load i64, i64* @var_long_long, align 8, !tbaa !11
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ret i64 %0
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}
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define dso_local void @test_longlong_two(i32 signext %a) {
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; CHECK-LABEL: test_longlong_two:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis 4, 2, var_long_long@got@tprel@ha
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; CHECK-NEXT: ld 4, var_long_long@got@tprel@l(4)
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; CHECK-NEXT: stdx 3, 4, var_long_long@tls
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entry:
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%conv = sext i32 %a to i64
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store i64 %conv, i64* @var_long_long, align 8, !tbaa !11
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ret void
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}
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define dso_local i64 @test_longlong_three(i64 %a) {
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; CHECK-LABEL: test_longlong_three:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis 4, 2, var_long_long@got@tprel@ha
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; CHECK-NEXT: ld 4, var_long_long@got@tprel@l(4)
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; CHECK-NEXT: ldx 5, 4, var_long_long@tls
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; CHECK: stdx {{[0-9]+}}, 4, var_long_long@tls
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entry:
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%0 = load i64, i64* @var_long_long, align 8, !tbaa !11
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%add = add nsw i64 %0, %a
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store i64 %add, i64* @var_long_long, align 8, !tbaa !11
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ret i64 %add
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}
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!llvm.module.flags = !{!0, !1, !2}
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|
||||
!0 = !{i32 1, !"wchar_size", i32 4}
|
||||
!1 = !{i32 7, !"PIC Level", i32 1}
|
||||
!2 = !{i32 7, !"PIE Level", i32 1}
|
||||
!4 = !{!5, !5, i64 0}
|
||||
!5 = !{!"omnipotent char", !6, i64 0}
|
||||
!6 = !{!"Simple C/C++ TBAA"}
|
||||
!7 = !{!8, !8, i64 0}
|
||||
!8 = !{!"short", !5, i64 0}
|
||||
!9 = !{!10, !10, i64 0}
|
||||
!10 = !{!"int", !5, i64 0}
|
||||
!11 = !{!12, !12, i64 0}
|
||||
!12 = !{!"long long", !5, i64 0}
|
||||
Loading…
Reference in New Issue
Block a user