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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 19:52:54 +01:00
Major change to how defs are found when adding dependences (they
are now found as part of the initial walk of the machine code). Also memory load/store instructions can be generated for non-memory LLVM instructions, which wasn't handled before. It is now. llvm-svn: 1199
This commit is contained in:
Vikram S. Adve
parent
149bd3837d
commit
841ffd6a44
@ -446,98 +446,64 @@ static const unsigned int SG_DepOrderArray[][3] = {
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};
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// Add a dependence edge between every pair of machine load/store/call
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// instructions, where at least one is a store or a call.
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// Use latency 1 just to ensure that memory operations are ordered;
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// latency does not otherwise matter (true dependences enforce that).
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//
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void
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SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
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SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
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const TargetMachine& target)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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for (unsigned im=0, NM=memVec.size(); im < NM; im++)
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// Instructions in memNodeVec are in execution order within the basic block,
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// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
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//
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for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
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{
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const Instruction* fromInstr = memVec[im];
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int fromType = (fromInstr->getOpcode() == Instruction::Call
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? SG_CALL_REF
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: (fromInstr->getOpcode() == Instruction::Load
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? SG_LOAD_REF
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: SG_STORE_REF));
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MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
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int fromType = mii.isCall(fromOpCode)? SG_CALL_REF
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: mii.isLoad(fromOpCode)? SG_LOAD_REF
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: SG_STORE_REF;
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for (unsigned jm=im+1; jm < NM; jm++)
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{
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const Instruction* toInstr = memVec[jm];
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int toType = (fromInstr->getOpcode() == Instruction::Call? 2
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: ((fromInstr->getOpcode()==Instruction::Load)? 0:1));
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if (fromType == SG_LOAD_REF && toType == SG_LOAD_REF)
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continue;
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MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
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int toType = mii.isCall(toOpCode)? SG_CALL_REF
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: mii.isLoad(toOpCode)? SG_LOAD_REF
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: SG_STORE_REF;
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unsigned int depOrderType = SG_DepOrderArray[fromType][toType];
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MachineCodeForVMInstr& fromInstrMvec=fromInstr->getMachineInstrVec();
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MachineCodeForVMInstr& toInstrMvec = toInstr->getMachineInstrVec();
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// We have two VM memory instructions, and at least one is a store
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// or a call. Add edges between all machine load/store/call instrs.
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// Use a latency of 1 to ensure that memory operations are ordered;
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// latency does not otherwise matter (true dependences enforce that).
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//
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for (unsigned i=0, N=fromInstrMvec.size(); i < N; i++)
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{
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MachineOpCode fromOpCode = fromInstrMvec[i]->getOpCode();
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if (mii.isLoad(fromOpCode) || mii.isStore(fromOpCode) ||
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mii.isCall(fromOpCode))
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{
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SchedGraphNode* fromNode =
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this->getGraphNodeForInstr(fromInstrMvec[i]);
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assert(fromNode && "No node for memory instr?");
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for (unsigned j=0, M=toInstrMvec.size(); j < M; j++)
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{
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MachineOpCode toOpCode = toInstrMvec[j]->getOpCode();
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if (mii.isLoad(toOpCode) || mii.isStore(toOpCode)
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|| mii.isCall(fromOpCode))
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{
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SchedGraphNode* toNode =
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this->getGraphNodeForInstr(toInstrMvec[j]);
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assert(toNode && "No node for memory instr?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::MemoryDep,
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depOrderType, 1);
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}
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}
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}
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}
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}
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if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
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(void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
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SchedGraphEdge::MemoryDep,
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SG_DepOrderArray[fromType][toType], 1);
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}
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}
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}
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}
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// Add edges from/to CC reg instrs to/from call instrs.
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// Essentially this prevents anything that sets or uses a CC reg from being
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// reordered w.r.t. a call.
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// Use a latency of 0 because we only need to prevent out-of-order issue,
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// like with control dependences.
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//
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void
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SchedGraph::addCallCCEdges(const vector<const Instruction*>& memVec,
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SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
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MachineCodeForBasicBlock& bbMvec,
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const TargetMachine& target)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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vector<SchedGraphNode*> callNodeVec;
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// Find the call machine instructions and put them in a vector.
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// By using memVec, we avoid searching the entire machine code of the BB.
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//
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for (unsigned im=0, NM=memVec.size(); im < NM; im++)
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if (memVec[im]->getOpcode() == Instruction::Call)
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{
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MachineCodeForVMInstr& callMvec=memVec[im]->getMachineInstrVec();
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for (unsigned i=0; i < callMvec.size(); ++i)
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if (mii.isCall(callMvec[i]->getOpCode()))
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callNodeVec.push_back(this->getGraphNodeForInstr(callMvec[i]));
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}
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// Find the call instruction nodes and put them in a vector.
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for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
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if (mii.isCall(memNodeVec[im]->getOpCode()))
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callNodeVec.push_back(memNodeVec[im]);
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// Now add additional edges from/to CC reg instrs to/from call instrs.
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// Essentially this prevents anything that sets or uses a CC reg from being
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// reordered w.r.t. a call.
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// Use a latency of 0 because we only need to prevent out-of-order issue,
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// like with control dependences.
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// Now walk the entire basic block, looking for CC instructions *and*
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// call instructions, and keep track of the order of the instructions.
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// Use the call node vec to quickly find earlier and later call nodes
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// relative to the current CC instruction.
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//
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int lastCallNodeIdx = -1;
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for (unsigned i=0, N=bbMvec.size(); i < N; i++)
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@ -610,81 +576,6 @@ SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
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}
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}
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#undef OLD_SSA_EDGE_CONSTRUCTION
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#ifdef OLD_SSA_EDGE_CONSTRUCTION
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//
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// Delete this code once a few more tests pass.
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//
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inline void
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CreateSSAEdge(SchedGraph* graph,
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MachineInstr* defInstr,
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SchedGraphNode* node,
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const Value* val)
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{
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// this instruction does define value `val'.
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// if there is a node for it in the same graph, add an edge.
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SchedGraphNode* defNode = graph->getGraphNodeForInstr(defInstr);
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if (defNode != NULL && defNode != node)
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(void) new SchedGraphEdge(defNode, node, val);
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}
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void
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SchedGraph::addSSAEdge(SchedGraphNode* destNode,
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const Instruction* defVMInstr,
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const Value* defValue,
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const TargetMachine& target)
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{
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// Phi instructions are the only ones that produce a value but don't get
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// any non-dummy machine instructions. Return here as an optimization.
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//
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if (isa<PHINode>(defVMInstr))
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return;
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// Now add the graph edge for the appropriate machine instruction(s).
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// Note that multiple machine instructions generated for the
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// def VM instruction may modify the register for the def value.
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//
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MachineCodeForVMInstr& defMvec = defVMInstr->getMachineInstrVec();
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const MachineInstrInfo& mii = target.getInstrInfo();
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for (unsigned i=0, N=defMvec.size(); i < N; i++)
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{
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bool edgeAddedForInstr = false;
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// First check the explicit operands
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for (int o=0, N=mii.getNumOperands(defMvec[i]->getOpCode()); o < N; o++)
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{
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const MachineOperand& defOp = defMvec[i]->getOperand(o);
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if (defOp.opIsDef()
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&& (defOp.getOperandType() == MachineOperand::MO_VirtualRegister
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|| defOp.getOperandType() == MachineOperand::MO_CCRegister)
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&& (defOp.getVRegValue() == defValue))
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{
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CreateSSAEdge(this, defMvec[i], destNode, defValue);
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edgeAddedForInstr = true;
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break;
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}
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}
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// Then check the implicit operands
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if (! edgeAddedForInstr)
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{
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for (unsigned o=0, N=defMvec[i]->getNumImplicitRefs(); o < N; ++o)
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if (defMvec[i]->implicitRefIsDefined(o) &&
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defMvec[i]->getImplicitRef(o) == defValue)
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{
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CreateSSAEdge(this, defMvec[i], destNode, defValue);
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edgeAddedForInstr = true;
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break;
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}
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}
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}
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}
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#endif OLD_SSA_EDGE_CONSTRUCTION
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void
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SchedGraph::addSSAEdge(SchedGraphNode* destNode,
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@ -817,11 +708,17 @@ SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
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void
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SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
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SchedGraphNode* node,
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vector<SchedGraphNode*>& memNodeVec,
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RegToRefVecMap& regToRefVecMap,
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ValueToDefVecMap& valueToDefVecMap)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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MachineOpCode opCode = node->getOpCode();
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if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
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memNodeVec.push_back(node);
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// Collect the register references and value defs. for explicit operands
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//
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const MachineInstr& minstr = * node->getMachineInstr();
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@ -835,7 +732,8 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
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{
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int regNum = mop.getMachineRegNum();
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if (regNum != target.getRegInfo().getZeroRegNum())
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regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node, i));
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regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node,
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i));
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continue; // nothing more to do
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}
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@ -851,7 +749,7 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
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const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
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valueToDefVecMap[defInstr].push_back(make_pair(node, i));
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}
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//
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// Collect value defs. for implicit operands. The interface to extract
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// them assumes they must be virtual registers!
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@ -869,7 +767,7 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
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void
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SchedGraph::buildNodesforVMInstr(const TargetMachine& target,
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const Instruction* instr,
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vector<const Instruction*>& memVec,
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vector<SchedGraphNode*>& memNodeVec,
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RegToRefVecMap& regToRefVecMap,
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ValueToDefVecMap& valueToDefVecMap)
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{
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@ -881,16 +779,11 @@ SchedGraph::buildNodesforVMInstr(const TargetMachine& target,
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SchedGraphNode* node = new SchedGraphNode(getNumNodes(),
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instr, mvec[i], target);
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this->noteGraphNodeForInstr(mvec[i], node);
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// Remember all register references and value defs
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findDefUseInfoAtInstr(target, node, regToRefVecMap, valueToDefVecMap);
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findDefUseInfoAtInstr(target, node,
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memNodeVec, regToRefVecMap, valueToDefVecMap);
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}
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// Remember load/store/call instructions to add memory deps later.
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if (instr->getOpcode() == Instruction::Load ||
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instr->getOpcode() == Instruction::Store ||
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instr->getOpcode() == Instruction::Call)
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memVec.push_back(instr);
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}
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@ -908,10 +801,11 @@ SchedGraph::buildGraph(const TargetMachine& target)
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// each Value.
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ValueToDefVecMap valueToDefVecMap;
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// Use this data structure to note all LLVM memory instructions.
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// Use this data structure to note all memory instructions.
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// We use this to add memory dependence edges without a second full walk.
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//
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vector<const Instruction*> memVec;
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// vector<const Instruction*> memVec;
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vector<SchedGraphNode*> memNodeVec;
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// Use this data structure to note any uses or definitions of
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// machine registers so we can add edges for those later without
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@ -941,7 +835,7 @@ SchedGraph::buildGraph(const TargetMachine& target)
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// Build graph nodes for this VM instruction and gather def/use info.
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// Do these together in a single pass over all machine instructions.
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buildNodesforVMInstr(target, instr,
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memVec, regToRefVecMap, valueToDefVecMap);
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memNodeVec, regToRefVecMap, valueToDefVecMap);
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}
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//----------------------------------------------------------------
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@ -967,10 +861,10 @@ SchedGraph::buildGraph(const TargetMachine& target)
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// Then add memory dep edges: store->load, load->store, and store->store.
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// Call instructions are treated as both load and store.
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this->addMemEdges(memVec, target);
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this->addMemEdges(memNodeVec, target);
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// Then add edges between call instructions and CC set/use instructions
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this->addCallCCEdges(memVec, bbMvec, target);
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this->addCallCCEdges(memNodeVec, bbMvec, target);
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// Then add incoming def-use (SSA) edges for each machine instruction.
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for (unsigned i=0, N=bbMvec.size(); i < N; i++)
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@ -22,6 +22,8 @@
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#include "llvm/Support/NonCopyable.h"
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#include "llvm/Support/HashExtras.h"
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#include "llvm/Support/GraphTraits.h"
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#include "llvm/Target/MachineInstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include <hash_map>
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class Value;
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@ -159,6 +161,7 @@ public:
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unsigned int getNodeId () const { return nodeId; }
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const Instruction* getInstr () const { return instr; }
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const MachineInstr* getMachineInstr () const { return minstr; }
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const MachineOpCode getOpCode () const { return minstr->getOpCode();}
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int getLatency () const { return latency; }
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unsigned int getNumInEdges () const { return inEdges.size(); }
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unsigned int getNumOutEdges () const { return outEdges.size(); }
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@ -302,28 +305,29 @@ private:
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void buildNodesforVMInstr (const TargetMachine& target,
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const Instruction* instr,
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vector<const Instruction*>& memVec,
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vector<SchedGraphNode*>& memNodeVec,
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RegToRefVecMap& regToRefVecMap,
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ValueToDefVecMap& valueToDefVecMap);
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void findDefUseInfoAtInstr (const TargetMachine& target,
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SchedGraphNode* node,
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vector<SchedGraphNode*>& memNodeVec,
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RegToRefVecMap& regToRefVecMap,
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ValueToDefVecMap& valueToDefVecMap);
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void addEdgesForInstruction (const MachineInstr& minstr,
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void addEdgesForInstruction(const MachineInstr& minstr,
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const ValueToDefVecMap& valueToDefVecMap,
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const TargetMachine& target);
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void addCDEdges (const TerminatorInst* term,
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const TargetMachine& target);
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void addMemEdges (const vector<const Instruction*>& memVec,
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const TargetMachine& target);
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void addMemEdges (const vector<SchedGraphNode*>& memNodeVec,
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const TargetMachine& target);
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void addCallCCEdges (const vector<const Instruction*>& memVec,
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MachineCodeForBasicBlock& bbMvec,
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const TargetMachine& target);
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void addCallCCEdges (const vector<SchedGraphNode*>& memNodeVec,
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MachineCodeForBasicBlock& bbMvec,
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const TargetMachine& target);
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void addMachineRegEdges (RegToRefVecMap& regToRefVecMap,
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const TargetMachine& target);
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