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[AArch64][NEON] Match (or (and -a b) (and (a+1) b)) => bit select
With this patch vbslq_f32(vnegq_s32(a), b, c) lowers to a BIT instruction. Co-authored-by: Paul Walker <paul.walker@arm.com> Differential Revision: https://reviews.llvm.org/D100304
This commit is contained in:
Bradley Smith
parent
e7b532348e
commit
843db3db21
@ -12582,6 +12582,44 @@ static SDValue tryCombineToBSL(SDNode *N,
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if (N1.getOpcode() != ISD::AND)
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return SDValue();
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// InstCombine does (not (neg a)) => (add a -1).
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// Try: (or (and (neg a) b) (and (add a -1) c)) => (bsl (neg a) b c)
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// Loop over all combinations of AND operands.
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for (int i = 1; i >= 0; --i) {
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for (int j = 1; j >= 0; --j) {
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SDValue O0 = N0->getOperand(i);
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SDValue O1 = N1->getOperand(j);
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SDValue Sub, Add, SubSibling, AddSibling;
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// Find a SUB and an ADD operand, one from each AND.
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if (O0.getOpcode() == ISD::SUB && O1.getOpcode() == ISD::ADD) {
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Sub = O0;
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Add = O1;
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SubSibling = N0->getOperand(1 - i);
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AddSibling = N1->getOperand(1 - j);
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} else if (O0.getOpcode() == ISD::ADD && O1.getOpcode() == ISD::SUB) {
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Add = O0;
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Sub = O1;
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AddSibling = N0->getOperand(1 - i);
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SubSibling = N1->getOperand(1 - j);
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} else
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continue;
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if (!ISD::isBuildVectorAllZeros(Sub.getOperand(0).getNode()))
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continue;
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// Constant ones is always righthand operand of the Add.
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if (!ISD::isBuildVectorAllOnes(Add.getOperand(1).getNode()))
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continue;
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if (Sub.getOperand(1) != Add.getOperand(0))
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continue;
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return DAG.getNode(AArch64ISD::BSP, DL, VT, Sub, SubSibling, AddSibling);
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}
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}
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// (or (and a b) (and (not a) c)) => (bsl a b c)
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// We only have to look for constant vectors here since the general, variable
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// case can be handled in TableGen.
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unsigned Bits = VT.getScalarSizeInBits();
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238
test/CodeGen/AArch64/neon-bitselect.ll
Normal file
238
test/CodeGen/AArch64/neon-bitselect.ll
Normal file
@ -0,0 +1,238 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64"
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; Check that an expanded vbsl(vneg(pre_cond), left, right) lowers to a VBSL
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; during ISEL.
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;
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; Subtly different from a plain vector bit select: operand representing the
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; condition has been negated (-v, not to be confused with bitwise_not(v)).
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; Each vbsl_neg_cond_xxxx tests one of the 16 permutations of the operands.
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define <4 x i32> @vbsl_neg_cond_0000(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_0000:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%left_bits_0 = and <4 x i32> %neg_cond, %left
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%right_bits_0 = and <4 x i32> %min_cond, %right
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%bsl0000 = or <4 x i32> %right_bits_0, %left_bits_0
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ret <4 x i32> %bsl0000
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}
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define <4 x i32> @vbsl_neg_cond_0001(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_0001:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%left_bits_1 = and <4 x i32> %left, %neg_cond
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%right_bits_0 = and <4 x i32> %min_cond, %right
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%bsl0001 = or <4 x i32> %right_bits_0, %left_bits_1
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ret <4 x i32> %bsl0001
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}
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define <4 x i32> @vbsl_neg_cond_0010(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_0010:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%left_bits_0 = and <4 x i32> %neg_cond, %left
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%right_bits_1 = and <4 x i32> %right, %min_cond
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%bsl0010 = or <4 x i32> %right_bits_1, %left_bits_0
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ret <4 x i32> %bsl0010
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}
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define <4 x i32> @vbsl_neg_cond_0011(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_0011:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%left_bits_1 = and <4 x i32> %left, %neg_cond
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%right_bits_1 = and <4 x i32> %right, %min_cond
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%bsl0011 = or <4 x i32> %right_bits_1, %left_bits_1
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ret <4 x i32> %bsl0011
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}
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define <4 x i32> @vbsl_neg_cond_0100(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_0100:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%left_bits_0 = and <4 x i32> %neg_cond, %left
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%right_bits_0 = and <4 x i32> %min_cond, %right
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%bsl0100 = or <4 x i32> %left_bits_0, %right_bits_0
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ret <4 x i32> %bsl0100
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}
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define <4 x i32> @vbsl_neg_cond_0101(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_0101:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%left_bits_0 = and <4 x i32> %neg_cond, %left
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%right_bits_1 = and <4 x i32> %right, %min_cond
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%bsl0101 = or <4 x i32> %left_bits_0, %right_bits_1
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ret <4 x i32> %bsl0101
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}
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define <4 x i32> @vbsl_neg_cond_0110(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_0110:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%left_bits_1 = and <4 x i32> %left, %neg_cond
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%right_bits_0 = and <4 x i32> %min_cond, %right
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%bsl0110 = or <4 x i32> %left_bits_1, %right_bits_0
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ret <4 x i32> %bsl0110
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}
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define <4 x i32> @vbsl_neg_cond_0111(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_0111:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%left_bits_1 = and <4 x i32> %left, %neg_cond
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%right_bits_1 = and <4 x i32> %right, %min_cond
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%bsl0111 = or <4 x i32> %left_bits_1, %right_bits_1
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ret <4 x i32> %bsl0111
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}
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define <4 x i32> @vbsl_neg_cond_1000(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_1000:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left
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%flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right
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%bsl1000 = or <4 x i32> %flip_cond_right_bits_0, %flip_cond_left_bits_0
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ret <4 x i32> %bsl1000
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}
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define <4 x i32> @vbsl_neg_cond_1001(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_1001:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond
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%flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right
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%bsl1001 = or <4 x i32> %flip_cond_right_bits_0, %flip_cond_left_bits_1
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ret <4 x i32> %bsl1001
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}
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define <4 x i32> @vbsl_neg_cond_1010(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_1010:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left
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%flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond
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%bsl1010 = or <4 x i32> %flip_cond_right_bits_1, %flip_cond_left_bits_0
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ret <4 x i32> %bsl1010
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}
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define <4 x i32> @vbsl_neg_cond_1011(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_1011:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond
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%flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond
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%bsl1011 = or <4 x i32> %flip_cond_right_bits_1, %flip_cond_left_bits_1
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ret <4 x i32> %bsl1011
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}
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define <4 x i32> @vbsl_neg_cond_1100(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_1100:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left
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%flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right
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%bsl1100 = or <4 x i32> %flip_cond_left_bits_0, %flip_cond_right_bits_0
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ret <4 x i32> %bsl1100
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}
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define <4 x i32> @vbsl_neg_cond_1101(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_1101:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left
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%flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond
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%bsl1101 = or <4 x i32> %flip_cond_left_bits_0, %flip_cond_right_bits_1
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ret <4 x i32> %bsl1101
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}
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define <4 x i32> @vbsl_neg_cond_1110(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_1110:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond
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%flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right
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%bsl1110 = or <4 x i32> %flip_cond_left_bits_1, %flip_cond_right_bits_0
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ret <4 x i32> %bsl1110
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}
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define <4 x i32> @vbsl_neg_cond_1111(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
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; CHECK-LABEL: vbsl_neg_cond_1111:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg v0.4s, v0.4s
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; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b
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; CHECK-NEXT: ret
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%neg_cond = sub <4 x i32> zeroinitializer, %pre_cond
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%min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>
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%flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond
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%flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond
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%bsl1111 = or <4 x i32> %flip_cond_left_bits_1, %flip_cond_right_bits_1
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ret <4 x i32> %bsl1111
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}
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attributes #0 = { "target-features"="+neon" }
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