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Propagation in TargetLowering. Includes passing a DL
into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
This commit is contained in:
Dale Johannesen
parent
dd2a193a37
commit
84498c427e
@ -904,7 +904,7 @@ public:
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/// FoldSetCC - Constant fold a setcc to true or false.
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SDValue FoldSetCC(MVT VT, SDValue N1,
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SDValue N2, ISD::CondCode Cond);
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SDValue N2, ISD::CondCode Cond, DebugLoc dl);
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/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
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/// use this predicate to simplify operations downstream.
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@ -789,7 +789,7 @@ public:
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/// and cc. If it is unable to simplify it, return a null SDValue.
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SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
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ISD::CondCode Cond, bool foldBooleans,
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DAGCombinerInfo &DCI) const;
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DAGCombinerInfo &DCI, DebugLoc dl) const;
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/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
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/// node is a GlobalAddress + offset.
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@ -207,7 +207,7 @@ namespace {
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SDValue N3, ISD::CondCode CC,
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bool NotExtCompare = false);
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SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
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bool foldBooleans = true);
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DebugLoc DL, bool foldBooleans = true);
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SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
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unsigned HiOp);
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SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
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@ -2911,7 +2911,7 @@ SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
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// Determine if the condition we're dealing with is constant
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SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
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N0, N1, CC, false);
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N0, N1, CC, N->getDebugLoc(), false);
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if (SCC.getNode()) AddToWorkList(SCC.getNode());
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if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
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@ -2937,7 +2937,8 @@ SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
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SDValue DAGCombiner::visitSETCC(SDNode *N) {
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return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
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cast<CondCodeSDNode>(N->getOperand(2))->get());
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cast<CondCodeSDNode>(N->getOperand(2))->get(),
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N->getDebugLoc());
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}
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// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
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@ -4434,7 +4435,8 @@ SDValue DAGCombiner::visitBR_CC(SDNode *N) {
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// Use SimplifySetCC to simplify SETCC's.
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SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
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CondLHS, CondRHS, CC->get(), false);
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CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
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false);
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if (Simp.getNode()) AddToWorkList(Simp.getNode());
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ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
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@ -5686,7 +5688,7 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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// Determine if the condition we're dealing with is constant
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SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
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N0, N1, CC, false);
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N0, N1, CC, DL, false);
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if (SCC.getNode()) AddToWorkList(SCC.getNode());
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ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
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@ -5880,10 +5882,10 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
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SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0,
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SDValue N1, ISD::CondCode Cond,
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bool foldBooleans) {
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DebugLoc DL, bool foldBooleans) {
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TargetLowering::DAGCombinerInfo
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DagCombineInfo(DAG, Level == Unrestricted, false, this);
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return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
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return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
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}
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/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
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@ -5315,12 +5315,12 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
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// this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
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TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
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Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
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LHSLo, RHSLo, LowCC, false, DagCombineInfo);
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LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
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if (!Tmp1.getNode())
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Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
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LHSLo, RHSLo, LowCC);
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Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, CCCode, false, DagCombineInfo);
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LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
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if (!Tmp2.getNode())
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Tmp2 = DAG.getNode(ISD::SETCC, dl,
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TLI.getSetCCResultType(LHSHi.getValueType()),
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@ -5343,7 +5343,7 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
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} else {
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Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, ISD::SETEQ, false,
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DagCombineInfo);
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DagCombineInfo, dl);
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if (!Result.getNode())
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Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, ISD::SETEQ);
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@ -2034,12 +2034,12 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
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TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
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SDValue Tmp1, Tmp2;
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Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
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LHSLo, RHSLo, LowCC, false, DagCombineInfo);
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LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
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if (!Tmp1.getNode())
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Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
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LHSLo, RHSLo, LowCC);
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Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, CCCode, false, DagCombineInfo);
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LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
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if (!Tmp2.getNode())
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Tmp2 = DAG.getNode(ISD::SETCC, dl,
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TLI.getSetCCResultType(LHSHi.getValueType()),
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@ -2063,7 +2063,8 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
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}
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NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, ISD::SETEQ, false, DagCombineInfo);
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LHSHi, RHSHi, ISD::SETEQ, false,
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DagCombineInfo, dl);
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if (!NewLHS.getNode())
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NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, ISD::SETEQ);
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@ -1334,7 +1334,7 @@ SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) {
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}
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SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
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SDValue N2, ISD::CondCode Cond) {
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SDValue N2, ISD::CondCode Cond, DebugLoc dl) {
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// These setcc operations always fold.
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switch (Cond) {
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default: break;
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@ -1387,29 +1387,29 @@ SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
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switch (Cond) {
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default: break;
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case ISD::SETEQ: if (R==APFloat::cmpUnordered)
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return getNode(ISD::UNDEF, VT);
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return getNode(ISD::UNDEF, dl, VT);
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// fall through
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case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT);
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case ISD::SETNE: if (R==APFloat::cmpUnordered)
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return getNode(ISD::UNDEF, VT);
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return getNode(ISD::UNDEF, dl, VT);
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// fall through
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case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
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R==APFloat::cmpLessThan, VT);
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case ISD::SETLT: if (R==APFloat::cmpUnordered)
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return getNode(ISD::UNDEF, VT);
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return getNode(ISD::UNDEF, dl, VT);
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// fall through
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case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT);
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case ISD::SETGT: if (R==APFloat::cmpUnordered)
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return getNode(ISD::UNDEF, VT);
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return getNode(ISD::UNDEF, dl, VT);
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// fall through
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case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT);
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case ISD::SETLE: if (R==APFloat::cmpUnordered)
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return getNode(ISD::UNDEF, VT);
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return getNode(ISD::UNDEF, dl, VT);
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// fall through
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case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
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R==APFloat::cmpEqual, VT);
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case ISD::SETGE: if (R==APFloat::cmpUnordered)
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return getNode(ISD::UNDEF, VT);
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return getNode(ISD::UNDEF, dl, VT);
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// fall through
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case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
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R==APFloat::cmpEqual, VT);
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@ -1427,7 +1427,7 @@ SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
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}
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} else {
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// Ensure that the constant occurs on the RHS.
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return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond));
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return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond));
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}
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}
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@ -2832,12 +2832,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
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SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
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Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
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Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end());
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return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
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return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
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}
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break;
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case ISD::SETCC: {
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// Use FoldSetCC to simplify SETCC's.
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SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get());
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SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL);
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if (Simp.getNode()) return Simp;
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break;
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}
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@ -2854,7 +2854,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
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case ISD::BRCOND:
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if (N2C) {
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if (N2C->getZExtValue()) // Unconditional branch
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return getNode(ISD::BR, MVT::Other, N1, N3);
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return getNode(ISD::BR, DL, MVT::Other, N1, N3);
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else
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return N1; // Never-taken branch
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}
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@ -760,6 +760,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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assert(Op.getValueSizeInBits() == BitWidth &&
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"Mask size mismatches value type size!");
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APInt NewMask = DemandedMask;
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DebugLoc dl = Op.getNode()->getDebugLoc();
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// Don't know anything.
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KnownZero = KnownOne = APInt(BitWidth, 0);
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@ -778,7 +779,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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} else if (DemandedMask == 0) {
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// Not demanding any bits from Op.
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if (Op.getOpcode() != ISD::UNDEF)
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, dl,
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Op.getValueType()));
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return false;
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} else if (Depth == 6) { // Limit search depth.
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return false;
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@ -905,8 +907,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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if ((KnownOne & KnownOne2) == KnownOne) {
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MVT VT = Op.getValueType();
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SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
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ANDC));
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
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Op.getOperand(0), ANDC));
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}
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}
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@ -919,7 +921,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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if (Expanded.isAllOnesValue()) {
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if (Expanded != C->getAPIntValue()) {
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MVT VT = Op.getValueType();
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SDValue New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
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SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
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TLO.DAG.getConstant(Expanded, VT));
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return TLO.CombineTo(Op, New);
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}
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@ -995,7 +997,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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SDValue NewSA =
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TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
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MVT VT = Op.getValueType();
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return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
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return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
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InOp.getOperand(0), NewSA));
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}
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}
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@ -1036,7 +1038,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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SDValue NewSA =
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TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
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return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
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return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
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InOp.getOperand(0), NewSA));
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}
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}
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@ -1059,7 +1061,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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// variable. The low bit of the shift cannot be an input sign bit unless
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// the shift amount is >= the size of the datatype, which is undefined.
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if (DemandedMask == 1)
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, Op.getValueType(),
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
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Op.getOperand(0), Op.getOperand(1)));
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if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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@ -1091,7 +1093,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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// If the input sign bit is known to be zero, or if none of the top bits
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// are demanded, turn this into an unsigned shift right.
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if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
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Op.getOperand(0),
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Op.getOperand(1)));
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} else if (KnownOne.intersects(SignBit)) { // New bits are known one.
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KnownOne |= HighBits;
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@ -1132,7 +1135,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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// If the input sign bit is known zero, convert this into a zero extension.
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if (KnownZero.intersects(InSignBit))
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return TLO.CombineTo(Op,
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TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
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TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
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if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
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KnownOne |= NewBits;
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@ -1152,7 +1155,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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APInt NewBits =
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APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
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if (!NewBits.intersects(NewMask))
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
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Op.getValueType(),
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Op.getOperand(0)));
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@ -1174,8 +1177,9 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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// If none of the top bits are demanded, convert this into an any_extend.
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if (NewBits == 0)
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return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
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Op.getOperand(0)));
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return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
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Op.getValueType(),
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Op.getOperand(0)));
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// Since some of the sign extended bits are demanded, we know that the sign
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// bit is demanded.
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@ -1191,7 +1195,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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// If the sign bit is known zero, convert this to a zero extend.
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if (KnownZero.intersects(InSignBit))
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
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Op.getValueType(),
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Op.getOperand(0)));
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@ -1247,11 +1251,13 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
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// None of the shifted in bits are needed. Add a truncate of the
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// shift input, then shift it.
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SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
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SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
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Op.getValueType(),
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In.getOperand(0));
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
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NewTrunc, In.getOperand(1)));
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
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Op.getValueType(),
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NewTrunc,
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In.getOperand(1)));
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}
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}
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break;
|
||||
@ -1361,7 +1367,7 @@ static bool ValueHasAtMostOneBitSet(SDValue Val, const SelectionDAG &DAG) {
|
||||
SDValue
|
||||
TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
ISD::CondCode Cond, bool foldBooleans,
|
||||
DAGCombinerInfo &DCI) const {
|
||||
DAGCombinerInfo &DCI, DebugLoc dl) const {
|
||||
SelectionDAG &DAG = DCI.DAG;
|
||||
|
||||
// These setcc operations always fold.
|
||||
@ -1376,7 +1382,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
|
||||
const APInt &C1 = N1C->getAPIntValue();
|
||||
if (isa<ConstantSDNode>(N0.getNode())) {
|
||||
return DAG.FoldSetCC(VT, N0, N1, Cond);
|
||||
return DAG.FoldSetCC(VT, N0, N1, Cond, dl);
|
||||
} else {
|
||||
// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
|
||||
// equality comparison, then we're just comparing whether X itself is
|
||||
@ -1397,7 +1403,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
Cond = ISD::SETEQ;
|
||||
}
|
||||
SDValue Zero = DAG.getConstant(0, N0.getValueType());
|
||||
return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
|
||||
return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
|
||||
Zero, Cond);
|
||||
}
|
||||
}
|
||||
@ -1442,16 +1448,17 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
MVT PtrType = Lod->getOperand(1).getValueType();
|
||||
SDValue Ptr = Lod->getBasePtr();
|
||||
if (bestOffset != 0)
|
||||
Ptr = DAG.getNode(ISD::ADD, PtrType, Lod->getBasePtr(),
|
||||
Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
|
||||
DAG.getConstant(bestOffset, PtrType));
|
||||
unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
|
||||
SDValue NewLoad = DAG.getLoad(newVT, Lod->getChain(), Ptr,
|
||||
SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
|
||||
Lod->getSrcValue(),
|
||||
Lod->getSrcValueOffset() + bestOffset,
|
||||
false, NewAlign);
|
||||
return DAG.getSetCC(VT, DAG.getNode(ISD::AND, newVT, NewLoad,
|
||||
return DAG.getSetCC(dl, VT,
|
||||
DAG.getNode(ISD::AND, dl, newVT, NewLoad,
|
||||
DAG.getConstant(bestMask, newVT)),
|
||||
DAG.getConstant(0LL, newVT), Cond);
|
||||
DAG.getConstant(0LL, newVT), Cond);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1492,7 +1499,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
case ISD::SETUGE:
|
||||
case ISD::SETULT:
|
||||
case ISD::SETULE:
|
||||
return DAG.getSetCC(VT, N0.getOperand(0),
|
||||
return DAG.getSetCC(dl, VT, N0.getOperand(0),
|
||||
DAG.getConstant(APInt(C1).trunc(InSize),
|
||||
N0.getOperand(0).getValueType()),
|
||||
Cond);
|
||||
@ -1520,13 +1527,13 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
ZextOp = N0.getOperand(0);
|
||||
} else {
|
||||
APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
|
||||
ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
|
||||
ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
|
||||
DAG.getConstant(Imm, Op0Ty));
|
||||
}
|
||||
if (!DCI.isCalledByLegalizer())
|
||||
DCI.AddToWorklist(ZextOp.getNode());
|
||||
// Otherwise, make this a use of a zext.
|
||||
return DAG.getSetCC(VT, ZextOp,
|
||||
return DAG.getSetCC(dl, VT, ZextOp,
|
||||
DAG.getConstant(C1 & APInt::getLowBitsSet(
|
||||
ExtDstTyBits,
|
||||
ExtSrcTyBits),
|
||||
@ -1545,7 +1552,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
|
||||
CC = ISD::getSetCCInverse(CC,
|
||||
N0.getOperand(0).getValueType().isInteger());
|
||||
return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
|
||||
return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
|
||||
}
|
||||
|
||||
if ((N0.getOpcode() == ISD::XOR ||
|
||||
@ -1568,11 +1575,11 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
assert(N0.getOpcode() == ISD::AND &&
|
||||
N0.getOperand(0).getOpcode() == ISD::XOR);
|
||||
// ((X^1)&1)^1 -> X & 1
|
||||
Val = DAG.getNode(ISD::AND, N0.getValueType(),
|
||||
Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
|
||||
N0.getOperand(0).getOperand(0),
|
||||
N0.getOperand(1));
|
||||
}
|
||||
return DAG.getSetCC(VT, Val, N1,
|
||||
return DAG.getSetCC(dl, VT, Val, N1,
|
||||
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
|
||||
}
|
||||
}
|
||||
@ -1592,15 +1599,17 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
|
||||
if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
|
||||
// X >= C0 --> X > (C0-1)
|
||||
return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()),
|
||||
(Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(C1-1, N1.getValueType()),
|
||||
(Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
|
||||
}
|
||||
|
||||
if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
|
||||
if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
|
||||
// X <= C0 --> X < (C0+1)
|
||||
return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()),
|
||||
(Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(C1+1, N1.getValueType()),
|
||||
(Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
|
||||
}
|
||||
|
||||
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
|
||||
@ -1614,19 +1623,21 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
|
||||
// Canonicalize setgt X, Min --> setne X, Min
|
||||
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
|
||||
return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
|
||||
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
|
||||
// Canonicalize setlt X, Max --> setne X, Max
|
||||
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
|
||||
return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
|
||||
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
|
||||
|
||||
// If we have setult X, 1, turn it into seteq X, 0
|
||||
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
|
||||
return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
|
||||
ISD::SETEQ);
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(MinVal, N0.getValueType()),
|
||||
ISD::SETEQ);
|
||||
// If we have setugt X, Max-1, turn it into seteq X, Max
|
||||
else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
|
||||
return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
|
||||
ISD::SETEQ);
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(MaxVal, N0.getValueType()),
|
||||
ISD::SETEQ);
|
||||
|
||||
// If we have "setcc X, C0", check to see if we can shrink the immediate
|
||||
// by changing cc.
|
||||
@ -1634,7 +1645,8 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
// SETUGT X, SINTMAX -> SETLT X, 0
|
||||
if (Cond == ISD::SETUGT &&
|
||||
C1 == APInt::getSignedMaxValue(OperandBitSize))
|
||||
return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(0, N1.getValueType()),
|
||||
ISD::SETLT);
|
||||
|
||||
// SETULT X, SINTMIN -> SETGT X, -1
|
||||
@ -1643,7 +1655,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
SDValue ConstMinusOne =
|
||||
DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
|
||||
N1.getValueType());
|
||||
return DAG.getSetCC(VT, N0, ConstMinusOne, ISD::SETGT);
|
||||
return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
|
||||
}
|
||||
|
||||
// Fold bit comparisons when we can.
|
||||
@ -1656,7 +1668,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
|
||||
// Perform the xform if the AND RHS is a single bit.
|
||||
if (isPowerOf2_64(AndRHS->getZExtValue())) {
|
||||
return DAG.getNode(ISD::SRL, VT, N0,
|
||||
return DAG.getNode(ISD::SRL, dl, VT, N0,
|
||||
DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
|
||||
ShiftTy));
|
||||
}
|
||||
@ -1664,7 +1676,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
// (X & 8) == 8 --> (X & 8) >> 3
|
||||
// Perform the xform if C1 is a single bit.
|
||||
if (C1.isPowerOf2()) {
|
||||
return DAG.getNode(ISD::SRL, VT, N0,
|
||||
return DAG.getNode(ISD::SRL, dl, VT, N0,
|
||||
DAG.getConstant(C1.logBase2(), ShiftTy));
|
||||
}
|
||||
}
|
||||
@ -1672,12 +1684,12 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
}
|
||||
} else if (isa<ConstantSDNode>(N0.getNode())) {
|
||||
// Ensure that the constant occurs on the RHS.
|
||||
return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
|
||||
return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
|
||||
}
|
||||
|
||||
if (isa<ConstantFPSDNode>(N0.getNode())) {
|
||||
// Constant fold or commute setcc.
|
||||
SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond);
|
||||
SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
|
||||
if (O.getNode()) return O;
|
||||
} else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
|
||||
// If the RHS of an FP comparison is a constant, simplify it away in
|
||||
@ -1700,7 +1712,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
// have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
|
||||
// materialize 0.0.
|
||||
if (Cond == ISD::SETO || Cond == ISD::SETUO)
|
||||
return DAG.getSetCC(VT, N0, N0, Cond);
|
||||
return DAG.getSetCC(dl, VT, N0, N0, Cond);
|
||||
}
|
||||
|
||||
if (N0 == N1) {
|
||||
@ -1716,7 +1728,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
// if it is not already.
|
||||
ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
|
||||
if (NewCond != Cond)
|
||||
return DAG.getSetCC(VT, N0, N1, NewCond);
|
||||
return DAG.getSetCC(dl, VT, N0, N1, NewCond);
|
||||
}
|
||||
|
||||
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
|
||||
@ -1726,15 +1738,17 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
// Simplify (X+Y) == (X+Z) --> Y == Z
|
||||
if (N0.getOpcode() == N1.getOpcode()) {
|
||||
if (N0.getOperand(0) == N1.getOperand(0))
|
||||
return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
|
||||
return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
|
||||
if (N0.getOperand(1) == N1.getOperand(1))
|
||||
return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
|
||||
return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
|
||||
if (DAG.isCommutativeBinOp(N0.getOpcode())) {
|
||||
// If X op Y == Y op X, try other combinations.
|
||||
if (N0.getOperand(0) == N1.getOperand(1))
|
||||
return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
|
||||
return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
|
||||
Cond);
|
||||
if (N0.getOperand(1) == N1.getOperand(0))
|
||||
return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
|
||||
return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
|
||||
Cond);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1742,7 +1756,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
|
||||
// Turn (X+C1) == C2 --> X == C2-C1
|
||||
if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
|
||||
return DAG.getSetCC(VT, N0.getOperand(0),
|
||||
return DAG.getSetCC(dl, VT, N0.getOperand(0),
|
||||
DAG.getConstant(RHSC->getAPIntValue()-
|
||||
LHSR->getAPIntValue(),
|
||||
N0.getValueType()), Cond);
|
||||
@ -1754,7 +1768,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
// performing the inversion.
|
||||
if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
|
||||
return
|
||||
DAG.getSetCC(VT, N0.getOperand(0),
|
||||
DAG.getSetCC(dl, VT, N0.getOperand(0),
|
||||
DAG.getConstant(LHSR->getAPIntValue() ^
|
||||
RHSC->getAPIntValue(),
|
||||
N0.getValueType()),
|
||||
@ -1765,7 +1779,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
|
||||
if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
|
||||
return
|
||||
DAG.getSetCC(VT, N0.getOperand(1),
|
||||
DAG.getSetCC(dl, VT, N0.getOperand(1),
|
||||
DAG.getConstant(SUBC->getAPIntValue() -
|
||||
RHSC->getAPIntValue(),
|
||||
N0.getValueType()),
|
||||
@ -1776,21 +1790,21 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
|
||||
// Simplify (X+Z) == X --> Z == 0
|
||||
if (N0.getOperand(0) == N1)
|
||||
return DAG.getSetCC(VT, N0.getOperand(1),
|
||||
return DAG.getSetCC(dl, VT, N0.getOperand(1),
|
||||
DAG.getConstant(0, N0.getValueType()), Cond);
|
||||
if (N0.getOperand(1) == N1) {
|
||||
if (DAG.isCommutativeBinOp(N0.getOpcode()))
|
||||
return DAG.getSetCC(VT, N0.getOperand(0),
|
||||
return DAG.getSetCC(dl, VT, N0.getOperand(0),
|
||||
DAG.getConstant(0, N0.getValueType()), Cond);
|
||||
else if (N0.getNode()->hasOneUse()) {
|
||||
assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
|
||||
// (Z-X) == X --> Z == X<<1
|
||||
SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(),
|
||||
SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
|
||||
N1,
|
||||
DAG.getConstant(1, getShiftAmountTy()));
|
||||
if (!DCI.isCalledByLegalizer())
|
||||
DCI.AddToWorklist(SH.getNode());
|
||||
return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
|
||||
return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1799,20 +1813,20 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
N1.getOpcode() == ISD::XOR) {
|
||||
// Simplify X == (X+Z) --> Z == 0
|
||||
if (N1.getOperand(0) == N0) {
|
||||
return DAG.getSetCC(VT, N1.getOperand(1),
|
||||
return DAG.getSetCC(dl, VT, N1.getOperand(1),
|
||||
DAG.getConstant(0, N1.getValueType()), Cond);
|
||||
} else if (N1.getOperand(1) == N0) {
|
||||
if (DAG.isCommutativeBinOp(N1.getOpcode())) {
|
||||
return DAG.getSetCC(VT, N1.getOperand(0),
|
||||
return DAG.getSetCC(dl, VT, N1.getOperand(0),
|
||||
DAG.getConstant(0, N1.getValueType()), Cond);
|
||||
} else if (N1.getNode()->hasOneUse()) {
|
||||
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
|
||||
// X == (Z-X) --> X<<1 == Z
|
||||
SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
|
||||
SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
|
||||
DAG.getConstant(1, getShiftAmountTy()));
|
||||
if (!DCI.isCalledByLegalizer())
|
||||
DCI.AddToWorklist(SH.getNode());
|
||||
return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
|
||||
return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1823,7 +1837,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
if (ValueHasAtMostOneBitSet(N1, DAG)) {
|
||||
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
|
||||
SDValue Zero = DAG.getConstant(0, N1.getValueType());
|
||||
return DAG.getSetCC(VT, N0, Zero, Cond);
|
||||
return DAG.getSetCC(dl, VT, N0, Zero, Cond);
|
||||
}
|
||||
}
|
||||
if (N1.getOpcode() == ISD::AND)
|
||||
@ -1831,7 +1845,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
if (ValueHasAtMostOneBitSet(N0, DAG)) {
|
||||
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
|
||||
SDValue Zero = DAG.getConstant(0, N0.getValueType());
|
||||
return DAG.getSetCC(VT, N1, Zero, Cond);
|
||||
return DAG.getSetCC(dl, VT, N1, Zero, Cond);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1842,46 +1856,46 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
|
||||
switch (Cond) {
|
||||
default: assert(0 && "Unknown integer setcc!");
|
||||
case ISD::SETEQ: // X == Y -> ~(X^Y)
|
||||
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
|
||||
N0 = DAG.getNOT(DebugLoc::getUnknownLoc(), Temp, MVT::i1);
|
||||
Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
|
||||
N0 = DAG.getNOT(dl, Temp, MVT::i1);
|
||||
if (!DCI.isCalledByLegalizer())
|
||||
DCI.AddToWorklist(Temp.getNode());
|
||||
break;
|
||||
case ISD::SETNE: // X != Y --> (X^Y)
|
||||
N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
|
||||
N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
|
||||
break;
|
||||
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
|
||||
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
|
||||
Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1);
|
||||
Temp = DAG.getNOT(dl, N0, MVT::i1);
|
||||
N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
|
||||
if (!DCI.isCalledByLegalizer())
|
||||
DCI.AddToWorklist(Temp.getNode());
|
||||
break;
|
||||
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
|
||||
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
|
||||
Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1);
|
||||
N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
|
||||
Temp = DAG.getNOT(dl, N1, MVT::i1);
|
||||
N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
|
||||
if (!DCI.isCalledByLegalizer())
|
||||
DCI.AddToWorklist(Temp.getNode());
|
||||
break;
|
||||
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
|
||||
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
|
||||
Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1);
|
||||
N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
|
||||
Temp = DAG.getNOT(dl, N0, MVT::i1);
|
||||
N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
|
||||
if (!DCI.isCalledByLegalizer())
|
||||
DCI.AddToWorklist(Temp.getNode());
|
||||
break;
|
||||
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
|
||||
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
|
||||
Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1);
|
||||
N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
|
||||
Temp = DAG.getNOT(dl, N1, MVT::i1);
|
||||
N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
|
||||
break;
|
||||
}
|
||||
if (VT != MVT::i1) {
|
||||
if (!DCI.isCalledByLegalizer())
|
||||
DCI.AddToWorklist(N0.getNode());
|
||||
// FIXME: If running after legalize, we probably can't do this.
|
||||
N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
|
||||
N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
|
||||
}
|
||||
return N0;
|
||||
}
|
||||
@ -2396,6 +2410,7 @@ static ms magic(const APInt& d) {
|
||||
SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
|
||||
std::vector<SDNode*>* Created) const {
|
||||
MVT VT = N->getValueType(0);
|
||||
DebugLoc dl= N->getDebugLoc();
|
||||
|
||||
// Check to see if we can do this.
|
||||
// FIXME: We should be more aggressive here.
|
||||
@ -2409,40 +2424,40 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
|
||||
// FIXME: We should support doing a MUL in a wider type
|
||||
SDValue Q;
|
||||
if (isOperationLegalOrCustom(ISD::MULHS, VT))
|
||||
Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
|
||||
Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
|
||||
DAG.getConstant(magics.m, VT));
|
||||
else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
|
||||
Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
|
||||
Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
|
||||
N->getOperand(0),
|
||||
DAG.getConstant(magics.m, VT)).getNode(), 1);
|
||||
else
|
||||
return SDValue(); // No mulhs or equvialent
|
||||
// If d > 0 and m < 0, add the numerator
|
||||
if (d.isStrictlyPositive() && magics.m.isNegative()) {
|
||||
Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
|
||||
Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
|
||||
if (Created)
|
||||
Created->push_back(Q.getNode());
|
||||
}
|
||||
// If d < 0 and m > 0, subtract the numerator.
|
||||
if (d.isNegative() && magics.m.isStrictlyPositive()) {
|
||||
Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
|
||||
Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
|
||||
if (Created)
|
||||
Created->push_back(Q.getNode());
|
||||
}
|
||||
// Shift right algebraic if shift value is nonzero
|
||||
if (magics.s > 0) {
|
||||
Q = DAG.getNode(ISD::SRA, VT, Q,
|
||||
Q = DAG.getNode(ISD::SRA, dl, VT, Q,
|
||||
DAG.getConstant(magics.s, getShiftAmountTy()));
|
||||
if (Created)
|
||||
Created->push_back(Q.getNode());
|
||||
}
|
||||
// Extract the sign bit and add it to the quotient
|
||||
SDValue T =
|
||||
DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
|
||||
DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
|
||||
getShiftAmountTy()));
|
||||
if (Created)
|
||||
Created->push_back(T.getNode());
|
||||
return DAG.getNode(ISD::ADD, VT, Q, T);
|
||||
return DAG.getNode(ISD::ADD, dl, VT, Q, T);
|
||||
}
|
||||
|
||||
/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
|
||||
@ -2452,6 +2467,7 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
|
||||
SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
|
||||
std::vector<SDNode*>* Created) const {
|
||||
MVT VT = N->getValueType(0);
|
||||
DebugLoc dl = N->getDebugLoc();
|
||||
|
||||
// Check to see if we can do this.
|
||||
// FIXME: We should be more aggressive here.
|
||||
@ -2467,10 +2483,10 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
|
||||
// FIXME: We should support doing a MUL in a wider type
|
||||
SDValue Q;
|
||||
if (isOperationLegalOrCustom(ISD::MULHU, VT))
|
||||
Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
|
||||
Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
|
||||
DAG.getConstant(magics.m, VT));
|
||||
else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
|
||||
Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
|
||||
Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
|
||||
N->getOperand(0),
|
||||
DAG.getConstant(magics.m, VT)).getNode(), 1);
|
||||
else
|
||||
@ -2481,20 +2497,20 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
|
||||
if (magics.a == 0) {
|
||||
assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
|
||||
"We shouldn't generate an undefined shift!");
|
||||
return DAG.getNode(ISD::SRL, VT, Q,
|
||||
return DAG.getNode(ISD::SRL, dl, VT, Q,
|
||||
DAG.getConstant(magics.s, getShiftAmountTy()));
|
||||
} else {
|
||||
SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
|
||||
SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
|
||||
if (Created)
|
||||
Created->push_back(NPQ.getNode());
|
||||
NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
|
||||
NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
|
||||
DAG.getConstant(1, getShiftAmountTy()));
|
||||
if (Created)
|
||||
Created->push_back(NPQ.getNode());
|
||||
NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
|
||||
NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
|
||||
if (Created)
|
||||
Created->push_back(NPQ.getNode());
|
||||
return DAG.getNode(ISD::SRL, VT, NPQ,
|
||||
return DAG.getNode(ISD::SRL, dl, VT, NPQ,
|
||||
DAG.getConstant(magics.s-1, getShiftAmountTy()));
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user