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[DAG] Move basic USUBSAT pattern matches from X86 to DAGCombine
Begin transitioning the X86 vector code to recognise sub(umax(a,b) ,b) or sub(a,umin(a,b)) USUBSAT patterns to make it more generic and available to all targets. This initial patch just moves the basic umin/umax patterns to DAG, removing some vector-only checks on the way - these are some of the patterns that the legalizer will try to expand back to so we can be reasonably relaxed about matching these pre-legalization. We can handle the trunc(sub(..))) variants as well, which helps with patterns where we were promoting to a wider type to detect overflow/saturation. The remaining x86 code requires some cleanup first - some of it isn't actually tested etc. I also need to resurrect D25987. Differential Revision: https://reviews.llvm.org/D96413
This commit is contained in:
Simon Pilgrim
parent
2f03b95c01
commit
8450c87080
@ -549,6 +549,7 @@ namespace {
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SDValue N2, SDValue N3, ISD::CondCode CC);
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SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
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const SDLoc &DL);
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SDValue foldSubToUSubSat(EVT DstVT, SDNode *N);
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SDValue unfoldMaskedMerge(SDNode *N);
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SDValue unfoldExtremeBitClearingToShifts(SDNode *N);
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SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
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@ -3125,6 +3126,64 @@ SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
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return SDValue();
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}
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// Try to find umax(a,b) - b or a - umin(a,b) patterns that may be converted to
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// usubsat(a,b), optionally as a truncated type.
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SDValue DAGCombiner::foldSubToUSubSat(EVT DstVT, SDNode *N) {
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if (N->getOpcode() != ISD::SUB ||
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!(!LegalOperations || hasOperation(ISD::USUBSAT, DstVT)))
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return SDValue();
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EVT SubVT = N->getValueType(0);
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SDValue Op0 = N->getOperand(0);
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SDValue Op1 = N->getOperand(1);
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assert(DstVT.getScalarSizeInBits() <= SubVT.getScalarSizeInBits() &&
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"Illegal truncation");
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auto TruncatedUSUBSAT = [&](SDValue LHS, SDValue RHS) {
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SDLoc DL(N);
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if (DstVT == SubVT)
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return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS);
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// If the LHS is zero-extended then we can perform the USUBSAT as DstVT by
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// clamping RHS.
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APInt UpperBits = APInt::getBitsSetFrom(SubVT.getScalarSizeInBits(),
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DstVT.getScalarSizeInBits());
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if (!DAG.MaskedValueIsZero(LHS, UpperBits))
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return SDValue();
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SDValue SatLimit =
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DAG.getConstant(APInt::getLowBitsSet(SubVT.getScalarSizeInBits(),
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DstVT.getScalarSizeInBits()),
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DL, SubVT);
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RHS = DAG.getNode(ISD::UMIN, DL, SubVT, RHS, SatLimit);
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RHS = DAG.getZExtOrTrunc(RHS, DL, DstVT);
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LHS = DAG.getZExtOrTrunc(LHS, DL, DstVT);
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return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS);
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};
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// Try to find umax(a,b) - b or a - umin(a,b) patterns
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// they may be converted to usubsat(a,b).
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if (Op0.getOpcode() == ISD::UMAX) {
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SDValue MaxLHS = Op0.getOperand(0);
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SDValue MaxRHS = Op0.getOperand(1);
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if (MaxLHS == Op1)
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return TruncatedUSUBSAT(MaxRHS, Op1);
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if (MaxRHS == Op1)
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return TruncatedUSUBSAT(MaxLHS, Op1);
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}
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if (Op1.getOpcode() == ISD::UMIN) {
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SDValue MinLHS = Op1.getOperand(0);
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SDValue MinRHS = Op1.getOperand(1);
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if (MinLHS == Op0)
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return TruncatedUSUBSAT(Op0, MinRHS);
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if (MinRHS == Op0)
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return TruncatedUSUBSAT(Op0, MinLHS);
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}
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return SDValue();
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}
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// Since it may not be valid to emit a fold to zero for vector initializers
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// check if we can before folding.
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static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT,
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@ -3343,6 +3402,9 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
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if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N)))
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return V;
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if (SDValue V = foldSubToUSubSat(VT, N))
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return V;
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// (x - y) - 1 -> add (xor y, -1), x
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if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && isOneOrOneSplat(N1)) {
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SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
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@ -11816,6 +11878,9 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
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}
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}
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if (SDValue V = foldSubToUSubSat(VT, N0.getNode()))
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return V;
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// Attempt to pre-truncate BUILD_VECTOR sources.
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if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations &&
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TLI.isTruncateFree(SrcVT.getScalarType(), VT.getScalarType()) &&
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@ -49148,32 +49148,9 @@ static SDValue combineSubToSubus(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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SDValue SubusLHS, SubusRHS;
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// Try to find umax(a,b) - b or a - umin(a,b) patterns
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// they may be converted to subus(a,b).
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// TODO: Need to add IR canonicalization for this code.
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if (Op0.getOpcode() == ISD::UMAX) {
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SubusRHS = Op1;
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SDValue MaxLHS = Op0.getOperand(0);
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SDValue MaxRHS = Op0.getOperand(1);
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if (MaxLHS == Op1)
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SubusLHS = MaxRHS;
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else if (MaxRHS == Op1)
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SubusLHS = MaxLHS;
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else
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return SDValue();
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} else if (Op1.getOpcode() == ISD::UMIN) {
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SubusLHS = Op0;
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SDValue MinLHS = Op1.getOperand(0);
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SDValue MinRHS = Op1.getOperand(1);
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if (MinLHS == Op0)
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SubusRHS = MinRHS;
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else if (MinRHS == Op0)
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SubusRHS = MinLHS;
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else
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return SDValue();
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} else if (Op1.getOpcode() == ISD::TRUNCATE &&
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Op1.getOperand(0).getOpcode() == ISD::UMIN &&
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(EltVT == MVT::i8 || EltVT == MVT::i16)) {
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if (Op1.getOpcode() == ISD::TRUNCATE &&
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Op1.getOperand(0).getOpcode() == ISD::UMIN &&
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(EltVT == MVT::i8 || EltVT == MVT::i16)) {
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// Special case where the UMIN has been truncated. Try to push the truncate
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// further up. This is similar to the i32/i64 special processing.
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SubusLHS = Op0;
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@ -30,11 +30,9 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
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define i16 @func16(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: func16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w1, #0xffff
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; CHECK-NEXT: and w9, w0, #0xffff
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; CHECK-NEXT: cmp w9, w8
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; CHECK-NEXT: csel w9, w9, w8, hi
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; CHECK-NEXT: sub w0, w9, w8
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: subs w8, w8, w1, uxth
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; CHECK-NEXT: csel w0, wzr, w8, lo
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y);
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ret i16 %tmp;
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@ -43,11 +41,9 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
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define i8 @func8(i8 %x, i8 %y) nounwind {
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; CHECK-LABEL: func8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w1, #0xff
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; CHECK-NEXT: and w9, w0, #0xff
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; CHECK-NEXT: cmp w9, w8
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; CHECK-NEXT: csel w9, w9, w8, hi
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; CHECK-NEXT: sub w0, w9, w8
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; CHECK-NEXT: and w8, w0, #0xff
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; CHECK-NEXT: subs w8, w8, w1, uxtb
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; CHECK-NEXT: csel w0, wzr, w8, lo
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; CHECK-NEXT: ret
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%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y);
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ret i8 %tmp;
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@ -58,9 +54,8 @@ define i4 @func3(i4 %x, i4 %y) nounwind {
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w1, #0xf
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; CHECK-NEXT: and w9, w0, #0xf
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; CHECK-NEXT: cmp w9, w8
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; CHECK-NEXT: csel w9, w9, w8, hi
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; CHECK-NEXT: sub w0, w9, w8
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; CHECK-NEXT: subs w8, w9, w8
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; CHECK-NEXT: csel w0, wzr, w8, lo
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; CHECK-NEXT: ret
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%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y);
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ret i4 %tmp;
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@ -33,12 +33,10 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
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define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
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; CHECK-LABEL: func16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul w9, w1, w2
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: and w9, w9, #0xffff
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: csel w8, w8, w9, hi
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; CHECK-NEXT: sub w0, w8, w9
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; CHECK-NEXT: mul w9, w1, w2
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; CHECK-NEXT: subs w8, w8, w9, uxth
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; CHECK-NEXT: csel w0, wzr, w8, lo
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; CHECK-NEXT: ret
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%a = mul i16 %y, %z
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%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %a)
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@ -48,12 +46,10 @@ define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
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define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
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; CHECK-LABEL: func8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul w9, w1, w2
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; CHECK-NEXT: and w8, w0, #0xff
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; CHECK-NEXT: and w9, w9, #0xff
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: csel w8, w8, w9, hi
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; CHECK-NEXT: sub w0, w8, w9
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; CHECK-NEXT: mul w9, w1, w2
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; CHECK-NEXT: subs w8, w8, w9, uxtb
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; CHECK-NEXT: csel w0, wzr, w8, lo
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; CHECK-NEXT: ret
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%a = mul i8 %y, %z
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%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %a)
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@ -66,9 +62,8 @@ define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
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; CHECK-NEXT: mul w9, w1, w2
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; CHECK-NEXT: and w8, w0, #0xf
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; CHECK-NEXT: and w9, w9, #0xf
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: csel w8, w8, w9, hi
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; CHECK-NEXT: sub w0, w8, w9
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; CHECK-NEXT: subs w8, w8, w9
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; CHECK-NEXT: csel w0, wzr, w8, lo
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; CHECK-NEXT: ret
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%a = mul i4 %y, %z
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%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a)
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@ -125,17 +125,17 @@ define <3 x i16> @v_usubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: s_mov_b32 s4, 0xffff
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; GFX6-NEXT: v_and_b32_e32 v7, s4, v3
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; GFX6-NEXT: v_and_b32_e32 v6, s4, v3
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; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
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; GFX6-NEXT: v_and_b32_e32 v8, s4, v4
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; GFX6-NEXT: v_and_b32_e32 v7, s4, v4
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; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
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; GFX6-NEXT: v_max_u32_e32 v1, v1, v8
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; GFX6-NEXT: v_max_u32_e32 v0, v0, v7
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; GFX6-NEXT: v_and_b32_e32 v6, s4, v5
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; GFX6-NEXT: v_max_u32_e32 v1, v1, v7
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; GFX6-NEXT: v_max_u32_e32 v0, v0, v6
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; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
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; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
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; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
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; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
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; GFX6-NEXT: v_max_u32_e32 v2, v2, v6
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; GFX6-NEXT: v_max_u32_e32 v2, v2, v5
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; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v2, v5
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; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
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; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
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@ -93,29 +93,26 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
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define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
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; CHECK-T1-LABEL: func16:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: cmp r0, r1
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; CHECK-T1-NEXT: bhi .LBB2_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: .LBB2_2:
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; CHECK-T1-NEXT: subs r0, r0, r1
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; CHECK-T1-NEXT: bhs .LBB2_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: movs r0, #0
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; CHECK-T1-NEXT: .LBB2_2:
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; CHECK-T1-NEXT: uxth r0, r0
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: func16:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: cmp r0, r1
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; CHECK-T2-NEXT: it ls
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; CHECK-T2-NEXT: movls r0, r1
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; CHECK-T2-NEXT: subs r0, r0, r1
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; CHECK-T2-NEXT: it lo
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; CHECK-T2-NEXT: movlo r0, #0
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; CHECK-T2-NEXT: uxth r0, r0
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func16:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: cmp r0, r1
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; CHECK-ARM-NEXT: movls r0, r1
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; CHECK-ARM-NEXT: sub r0, r0, r1
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; CHECK-ARM-NEXT: subs r0, r0, r1
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; CHECK-ARM-NEXT: movlo r0, #0
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; CHECK-ARM-NEXT: uxth r0, r0
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; CHECK-ARM-NEXT: bx lr
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%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y)
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@ -125,29 +122,26 @@ define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
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define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
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; CHECK-T1-LABEL: func8:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: cmp r0, r1
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; CHECK-T1-NEXT: bhi .LBB3_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: .LBB3_2:
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; CHECK-T1-NEXT: subs r0, r0, r1
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; CHECK-T1-NEXT: bhs .LBB3_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: movs r0, #0
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; CHECK-T1-NEXT: .LBB3_2:
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; CHECK-T1-NEXT: uxtb r0, r0
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: func8:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: cmp r0, r1
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; CHECK-T2-NEXT: it ls
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; CHECK-T2-NEXT: movls r0, r1
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; CHECK-T2-NEXT: subs r0, r0, r1
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; CHECK-T2-NEXT: it lo
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; CHECK-T2-NEXT: movlo r0, #0
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; CHECK-T2-NEXT: uxtb r0, r0
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func8:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: cmp r0, r1
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; CHECK-ARM-NEXT: movls r0, r1
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; CHECK-ARM-NEXT: sub r0, r0, r1
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; CHECK-ARM-NEXT: subs r0, r0, r1
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; CHECK-ARM-NEXT: movlo r0, #0
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; CHECK-ARM-NEXT: uxtb r0, r0
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; CHECK-ARM-NEXT: bx lr
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%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y)
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@ -157,30 +151,27 @@ define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
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define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
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; CHECK-T1-LABEL: func3:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: cmp r0, r1
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; CHECK-T1-NEXT: bhi .LBB4_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: .LBB4_2:
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; CHECK-T1-NEXT: subs r1, r0, r1
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; CHECK-T1-NEXT: bhs .LBB4_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: movs r1, #0
|
||||
; CHECK-T1-NEXT: .LBB4_2:
|
||||
; CHECK-T1-NEXT: movs r0, #15
|
||||
; CHECK-T1-NEXT: ands r0, r1
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2-LABEL: func3:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: cmp r0, r1
|
||||
; CHECK-T2-NEXT: it ls
|
||||
; CHECK-T2-NEXT: movls r0, r1
|
||||
; CHECK-T2-NEXT: subs r0, r0, r1
|
||||
; CHECK-T2-NEXT: it lo
|
||||
; CHECK-T2-NEXT: movlo r0, #0
|
||||
; CHECK-T2-NEXT: and r0, r0, #15
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func3:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: cmp r0, r1
|
||||
; CHECK-ARM-NEXT: movls r0, r1
|
||||
; CHECK-ARM-NEXT: sub r0, r0, r1
|
||||
; CHECK-ARM-NEXT: subs r0, r0, r1
|
||||
; CHECK-ARM-NEXT: movlo r0, #0
|
||||
; CHECK-ARM-NEXT: and r0, r0, #15
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y)
|
||||
|
||||
@ -1407,26 +1407,26 @@ define <8 x i16> @psubus_8i32_max(<8 x i16> %x, <8 x i32> %y) nounwind {
|
||||
;
|
||||
; SSSE3-LABEL: psubus_8i32_max:
|
||||
; SSSE3: # %bb.0: # %vector.ph
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
|
||||
; SSSE3-NEXT: movdqa %xmm2, %xmm5
|
||||
; SSSE3-NEXT: pxor %xmm4, %xmm5
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm6 = [2147549183,2147549183,2147549183,2147549183]
|
||||
; SSSE3-NEXT: movdqa %xmm6, %xmm7
|
||||
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm7
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [65535,65535,65535,65535]
|
||||
; SSSE3-NEXT: pand %xmm7, %xmm2
|
||||
; SSSE3-NEXT: pandn %xmm5, %xmm7
|
||||
; SSSE3-NEXT: por %xmm2, %xmm7
|
||||
; SSSE3-NEXT: pshufb %xmm3, %xmm7
|
||||
; SSSE3-NEXT: pxor %xmm1, %xmm4
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648]
|
||||
; SSSE3-NEXT: movdqa %xmm2, %xmm4
|
||||
; SSSE3-NEXT: pxor %xmm3, %xmm4
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [2147549183,2147549183,2147549183,2147549183]
|
||||
; SSSE3-NEXT: movdqa %xmm5, %xmm6
|
||||
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm6
|
||||
; SSSE3-NEXT: pand %xmm6, %xmm1
|
||||
; SSSE3-NEXT: pandn %xmm5, %xmm6
|
||||
; SSSE3-NEXT: por %xmm1, %xmm6
|
||||
; SSSE3-NEXT: pshufb %xmm3, %xmm6
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm7[0]
|
||||
; SSSE3-NEXT: psubusw %xmm6, %xmm0
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [65535,65535,65535,65535]
|
||||
; SSSE3-NEXT: pand %xmm6, %xmm2
|
||||
; SSSE3-NEXT: pandn %xmm4, %xmm6
|
||||
; SSSE3-NEXT: por %xmm2, %xmm6
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
|
||||
; SSSE3-NEXT: pshufb %xmm2, %xmm6
|
||||
; SSSE3-NEXT: pxor %xmm1, %xmm3
|
||||
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm5
|
||||
; SSSE3-NEXT: pand %xmm5, %xmm1
|
||||
; SSSE3-NEXT: pandn %xmm4, %xmm5
|
||||
; SSSE3-NEXT: por %xmm1, %xmm5
|
||||
; SSSE3-NEXT: pshufb %xmm2, %xmm5
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0]
|
||||
; SSSE3-NEXT: psubusw %xmm5, %xmm0
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: psubus_8i32_max:
|
||||
@ -1671,25 +1671,25 @@ define <8 x i16> @psubus_8i64_max(<8 x i16> %x, <8 x i64> %y) nounwind {
|
||||
;
|
||||
; AVX1-LABEL: psubus_8i64_max:
|
||||
; AVX1: # %bb.0: # %vector.ph
|
||||
; AVX1-NEXT: vmovapd {{.*#+}} xmm3 = [65535,65535]
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808]
|
||||
; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm6
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm7 = [9223372036854841343,9223372036854841343]
|
||||
; AVX1-NEXT: vpcmpgtq %xmm6, %xmm7, %xmm6
|
||||
; AVX1-NEXT: vblendvpd %xmm6, %xmm4, %xmm3, %xmm4
|
||||
; AVX1-NEXT: vpxor %xmm5, %xmm2, %xmm6
|
||||
; AVX1-NEXT: vpcmpgtq %xmm6, %xmm7, %xmm6
|
||||
; AVX1-NEXT: vblendvpd %xmm6, %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpackusdw %xmm4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
|
||||
; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm6
|
||||
; AVX1-NEXT: vpcmpgtq %xmm6, %xmm7, %xmm6
|
||||
; AVX1-NEXT: vblendvpd %xmm6, %xmm4, %xmm3, %xmm4
|
||||
; AVX1-NEXT: vpxor %xmm5, %xmm1, %xmm5
|
||||
; AVX1-NEXT: vpcmpgtq %xmm5, %xmm7, %xmm5
|
||||
; AVX1-NEXT: vblendvpd %xmm5, %xmm1, %xmm3, %xmm1
|
||||
; AVX1-NEXT: vpackusdw %xmm4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808]
|
||||
; AVX1-NEXT: vpxor %xmm4, %xmm3, %xmm5
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [9223372036854841343,9223372036854841343]
|
||||
; AVX1-NEXT: vpcmpgtq %xmm5, %xmm6, %xmm5
|
||||
; AVX1-NEXT: vmovapd {{.*#+}} xmm7 = [65535,65535]
|
||||
; AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm7, %xmm3
|
||||
; AVX1-NEXT: vpxor %xmm4, %xmm2, %xmm5
|
||||
; AVX1-NEXT: vpcmpgtq %xmm5, %xmm6, %xmm5
|
||||
; AVX1-NEXT: vblendvpd %xmm5, %xmm2, %xmm7, %xmm2
|
||||
; AVX1-NEXT: vpackusdw %xmm3, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
|
||||
; AVX1-NEXT: vpxor %xmm4, %xmm3, %xmm5
|
||||
; AVX1-NEXT: vpcmpgtq %xmm5, %xmm6, %xmm5
|
||||
; AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm7, %xmm3
|
||||
; AVX1-NEXT: vpxor %xmm4, %xmm1, %xmm4
|
||||
; AVX1-NEXT: vpcmpgtq %xmm4, %xmm6, %xmm4
|
||||
; AVX1-NEXT: vblendvpd %xmm4, %xmm1, %xmm7, %xmm1
|
||||
; AVX1-NEXT: vpackusdw %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubusw %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vzeroupper
|
||||
@ -1733,119 +1733,119 @@ define <16 x i16> @psubus_16i32_max(<16 x i16> %x, <16 x i32> %y) nounwind {
|
||||
; SSE2-LABEL: psubus_16i32_max:
|
||||
; SSE2: # %bb.0: # %vector.ph
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [2147483648,2147483648,2147483648,2147483648]
|
||||
; SSE2-NEXT: movdqa %xmm5, %xmm8
|
||||
; SSE2-NEXT: movdqa %xmm3, %xmm8
|
||||
; SSE2-NEXT: pxor %xmm9, %xmm8
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [2147549183,2147549183,2147549183,2147549183]
|
||||
; SSE2-NEXT: movdqa %xmm7, %xmm6
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [2147549183,2147549183,2147549183,2147549183]
|
||||
; SSE2-NEXT: movdqa %xmm10, %xmm6
|
||||
; SSE2-NEXT: pcmpgtd %xmm8, %xmm6
|
||||
; SSE2-NEXT: pcmpeqd %xmm8, %xmm8
|
||||
; SSE2-NEXT: pand %xmm6, %xmm5
|
||||
; SSE2-NEXT: pxor %xmm8, %xmm6
|
||||
; SSE2-NEXT: por %xmm5, %xmm6
|
||||
; SSE2-NEXT: pslld $16, %xmm6
|
||||
; SSE2-NEXT: psrad $16, %xmm6
|
||||
; SSE2-NEXT: movdqa %xmm4, %xmm10
|
||||
; SSE2-NEXT: pxor %xmm9, %xmm10
|
||||
; SSE2-NEXT: movdqa %xmm7, %xmm5
|
||||
; SSE2-NEXT: pcmpgtd %xmm10, %xmm5
|
||||
; SSE2-NEXT: pand %xmm5, %xmm4
|
||||
; SSE2-NEXT: pxor %xmm8, %xmm5
|
||||
; SSE2-NEXT: por %xmm4, %xmm5
|
||||
; SSE2-NEXT: pslld $16, %xmm5
|
||||
; SSE2-NEXT: psrad $16, %xmm5
|
||||
; SSE2-NEXT: packssdw %xmm6, %xmm5
|
||||
; SSE2-NEXT: movdqa %xmm3, %xmm4
|
||||
; SSE2-NEXT: pxor %xmm9, %xmm4
|
||||
; SSE2-NEXT: movdqa %xmm7, %xmm6
|
||||
; SSE2-NEXT: pcmpgtd %xmm4, %xmm6
|
||||
; SSE2-NEXT: pand %xmm6, %xmm3
|
||||
; SSE2-NEXT: pxor %xmm8, %xmm6
|
||||
; SSE2-NEXT: por %xmm3, %xmm6
|
||||
; SSE2-NEXT: pslld $16, %xmm6
|
||||
; SSE2-NEXT: psrad $16, %xmm6
|
||||
; SSE2-NEXT: pxor %xmm2, %xmm9
|
||||
; SSE2-NEXT: pcmpgtd %xmm9, %xmm7
|
||||
; SSE2-NEXT: pxor %xmm7, %xmm8
|
||||
; SSE2-NEXT: pand %xmm2, %xmm7
|
||||
; SSE2-NEXT: por %xmm8, %xmm7
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm3
|
||||
; SSE2-NEXT: pxor %xmm9, %xmm3
|
||||
; SSE2-NEXT: movdqa %xmm10, %xmm7
|
||||
; SSE2-NEXT: pcmpgtd %xmm3, %xmm7
|
||||
; SSE2-NEXT: pand %xmm7, %xmm2
|
||||
; SSE2-NEXT: pxor %xmm8, %xmm7
|
||||
; SSE2-NEXT: por %xmm2, %xmm7
|
||||
; SSE2-NEXT: pslld $16, %xmm7
|
||||
; SSE2-NEXT: psrad $16, %xmm7
|
||||
; SSE2-NEXT: packssdw %xmm6, %xmm7
|
||||
; SSE2-NEXT: psubusw %xmm7, %xmm0
|
||||
; SSE2-NEXT: psubusw %xmm5, %xmm1
|
||||
; SSE2-NEXT: movdqa %xmm5, %xmm2
|
||||
; SSE2-NEXT: pxor %xmm9, %xmm2
|
||||
; SSE2-NEXT: movdqa %xmm10, %xmm3
|
||||
; SSE2-NEXT: pcmpgtd %xmm2, %xmm3
|
||||
; SSE2-NEXT: pand %xmm3, %xmm5
|
||||
; SSE2-NEXT: pxor %xmm8, %xmm3
|
||||
; SSE2-NEXT: por %xmm5, %xmm3
|
||||
; SSE2-NEXT: pslld $16, %xmm3
|
||||
; SSE2-NEXT: psrad $16, %xmm3
|
||||
; SSE2-NEXT: pxor %xmm4, %xmm9
|
||||
; SSE2-NEXT: pcmpgtd %xmm9, %xmm10
|
||||
; SSE2-NEXT: pxor %xmm10, %xmm8
|
||||
; SSE2-NEXT: pand %xmm4, %xmm10
|
||||
; SSE2-NEXT: por %xmm8, %xmm10
|
||||
; SSE2-NEXT: pslld $16, %xmm10
|
||||
; SSE2-NEXT: psrad $16, %xmm10
|
||||
; SSE2-NEXT: packssdw %xmm3, %xmm10
|
||||
; SSE2-NEXT: psubusw %xmm10, %xmm1
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: psubus_16i32_max:
|
||||
; SSSE3: # %bb.0: # %vector.ph
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm9 = [2147483648,2147483648,2147483648,2147483648]
|
||||
; SSSE3-NEXT: movdqa %xmm5, %xmm8
|
||||
; SSSE3-NEXT: movdqa %xmm3, %xmm8
|
||||
; SSSE3-NEXT: pxor %xmm9, %xmm8
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm7 = [2147549183,2147549183,2147549183,2147549183]
|
||||
; SSSE3-NEXT: movdqa %xmm7, %xmm6
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm10 = [2147549183,2147549183,2147549183,2147549183]
|
||||
; SSSE3-NEXT: movdqa %xmm10, %xmm6
|
||||
; SSSE3-NEXT: pcmpgtd %xmm8, %xmm6
|
||||
; SSSE3-NEXT: pcmpeqd %xmm8, %xmm8
|
||||
; SSSE3-NEXT: pand %xmm6, %xmm5
|
||||
; SSSE3-NEXT: pxor %xmm8, %xmm6
|
||||
; SSSE3-NEXT: por %xmm5, %xmm6
|
||||
; SSSE3-NEXT: pslld $16, %xmm6
|
||||
; SSSE3-NEXT: psrad $16, %xmm6
|
||||
; SSSE3-NEXT: movdqa %xmm4, %xmm10
|
||||
; SSSE3-NEXT: pxor %xmm9, %xmm10
|
||||
; SSSE3-NEXT: movdqa %xmm7, %xmm5
|
||||
; SSSE3-NEXT: pcmpgtd %xmm10, %xmm5
|
||||
; SSSE3-NEXT: pand %xmm5, %xmm4
|
||||
; SSSE3-NEXT: pxor %xmm8, %xmm5
|
||||
; SSSE3-NEXT: por %xmm4, %xmm5
|
||||
; SSSE3-NEXT: pslld $16, %xmm5
|
||||
; SSSE3-NEXT: psrad $16, %xmm5
|
||||
; SSSE3-NEXT: packssdw %xmm6, %xmm5
|
||||
; SSSE3-NEXT: movdqa %xmm3, %xmm4
|
||||
; SSSE3-NEXT: pxor %xmm9, %xmm4
|
||||
; SSSE3-NEXT: movdqa %xmm7, %xmm6
|
||||
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm6
|
||||
; SSSE3-NEXT: pand %xmm6, %xmm3
|
||||
; SSSE3-NEXT: pxor %xmm8, %xmm6
|
||||
; SSSE3-NEXT: por %xmm3, %xmm6
|
||||
; SSSE3-NEXT: pslld $16, %xmm6
|
||||
; SSSE3-NEXT: psrad $16, %xmm6
|
||||
; SSSE3-NEXT: pxor %xmm2, %xmm9
|
||||
; SSSE3-NEXT: pcmpgtd %xmm9, %xmm7
|
||||
; SSSE3-NEXT: pxor %xmm7, %xmm8
|
||||
; SSSE3-NEXT: pand %xmm2, %xmm7
|
||||
; SSSE3-NEXT: por %xmm8, %xmm7
|
||||
; SSSE3-NEXT: movdqa %xmm2, %xmm3
|
||||
; SSSE3-NEXT: pxor %xmm9, %xmm3
|
||||
; SSSE3-NEXT: movdqa %xmm10, %xmm7
|
||||
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm7
|
||||
; SSSE3-NEXT: pand %xmm7, %xmm2
|
||||
; SSSE3-NEXT: pxor %xmm8, %xmm7
|
||||
; SSSE3-NEXT: por %xmm2, %xmm7
|
||||
; SSSE3-NEXT: pslld $16, %xmm7
|
||||
; SSSE3-NEXT: psrad $16, %xmm7
|
||||
; SSSE3-NEXT: packssdw %xmm6, %xmm7
|
||||
; SSSE3-NEXT: psubusw %xmm7, %xmm0
|
||||
; SSSE3-NEXT: psubusw %xmm5, %xmm1
|
||||
; SSSE3-NEXT: movdqa %xmm5, %xmm2
|
||||
; SSSE3-NEXT: pxor %xmm9, %xmm2
|
||||
; SSSE3-NEXT: movdqa %xmm10, %xmm3
|
||||
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm3
|
||||
; SSSE3-NEXT: pand %xmm3, %xmm5
|
||||
; SSSE3-NEXT: pxor %xmm8, %xmm3
|
||||
; SSSE3-NEXT: por %xmm5, %xmm3
|
||||
; SSSE3-NEXT: pslld $16, %xmm3
|
||||
; SSSE3-NEXT: psrad $16, %xmm3
|
||||
; SSSE3-NEXT: pxor %xmm4, %xmm9
|
||||
; SSSE3-NEXT: pcmpgtd %xmm9, %xmm10
|
||||
; SSSE3-NEXT: pxor %xmm10, %xmm8
|
||||
; SSSE3-NEXT: pand %xmm4, %xmm10
|
||||
; SSSE3-NEXT: por %xmm8, %xmm10
|
||||
; SSSE3-NEXT: pslld $16, %xmm10
|
||||
; SSSE3-NEXT: psrad $16, %xmm10
|
||||
; SSSE3-NEXT: packssdw %xmm3, %xmm10
|
||||
; SSSE3-NEXT: psubusw %xmm10, %xmm1
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: psubus_16i32_max:
|
||||
; SSE41: # %bb.0: # %vector.ph
|
||||
; SSE41-NEXT: movdqa {{.*#+}} xmm6 = [65535,65535,65535,65535]
|
||||
; SSE41-NEXT: pminud %xmm6, %xmm5
|
||||
; SSE41-NEXT: pminud %xmm6, %xmm4
|
||||
; SSE41-NEXT: packusdw %xmm5, %xmm4
|
||||
; SSE41-NEXT: pminud %xmm6, %xmm3
|
||||
; SSE41-NEXT: pminud %xmm6, %xmm2
|
||||
; SSE41-NEXT: packusdw %xmm3, %xmm2
|
||||
; SSE41-NEXT: psubusw %xmm2, %xmm0
|
||||
; SSE41-NEXT: pminud %xmm6, %xmm5
|
||||
; SSE41-NEXT: pminud %xmm6, %xmm4
|
||||
; SSE41-NEXT: packusdw %xmm5, %xmm4
|
||||
; SSE41-NEXT: psubusw %xmm4, %xmm1
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: psubus_16i32_max:
|
||||
; AVX1: # %bb.0: # %vector.ph
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [65535,65535,65535,65535]
|
||||
; AVX1-NEXT: vpminud %xmm4, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpminud %xmm4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpackusdw %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [65535,65535,65535,65535]
|
||||
; AVX1-NEXT: vpminud %xmm4, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpminud %xmm4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpackusdw %xmm3, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
|
||||
; AVX1-NEXT: vpsubusw %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
|
||||
; AVX1-NEXT: vpminud %xmm4, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpminud %xmm4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpackusdw %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsubusw %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
@ -1902,26 +1902,26 @@ define <8 x i16> @psubus_i16_i32_max_swapped(<8 x i16> %x, <8 x i32> %y) nounwin
|
||||
;
|
||||
; SSSE3-LABEL: psubus_i16_i32_max_swapped:
|
||||
; SSSE3: # %bb.0: # %vector.ph
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
|
||||
; SSSE3-NEXT: movdqa %xmm2, %xmm5
|
||||
; SSSE3-NEXT: pxor %xmm4, %xmm5
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm6 = [2147549183,2147549183,2147549183,2147549183]
|
||||
; SSSE3-NEXT: movdqa %xmm6, %xmm7
|
||||
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm7
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [65535,65535,65535,65535]
|
||||
; SSSE3-NEXT: pand %xmm7, %xmm2
|
||||
; SSSE3-NEXT: pandn %xmm5, %xmm7
|
||||
; SSSE3-NEXT: por %xmm2, %xmm7
|
||||
; SSSE3-NEXT: pshufb %xmm3, %xmm7
|
||||
; SSSE3-NEXT: pxor %xmm1, %xmm4
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648]
|
||||
; SSSE3-NEXT: movdqa %xmm2, %xmm4
|
||||
; SSSE3-NEXT: pxor %xmm3, %xmm4
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [2147549183,2147549183,2147549183,2147549183]
|
||||
; SSSE3-NEXT: movdqa %xmm5, %xmm6
|
||||
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm6
|
||||
; SSSE3-NEXT: pand %xmm6, %xmm1
|
||||
; SSSE3-NEXT: pandn %xmm5, %xmm6
|
||||
; SSSE3-NEXT: por %xmm1, %xmm6
|
||||
; SSSE3-NEXT: pshufb %xmm3, %xmm6
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm7[0]
|
||||
; SSSE3-NEXT: psubusw %xmm6, %xmm0
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [65535,65535,65535,65535]
|
||||
; SSSE3-NEXT: pand %xmm6, %xmm2
|
||||
; SSSE3-NEXT: pandn %xmm4, %xmm6
|
||||
; SSSE3-NEXT: por %xmm2, %xmm6
|
||||
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
|
||||
; SSSE3-NEXT: pshufb %xmm2, %xmm6
|
||||
; SSSE3-NEXT: pxor %xmm1, %xmm3
|
||||
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm5
|
||||
; SSSE3-NEXT: pand %xmm5, %xmm1
|
||||
; SSSE3-NEXT: pandn %xmm4, %xmm5
|
||||
; SSSE3-NEXT: por %xmm1, %xmm5
|
||||
; SSSE3-NEXT: pshufb %xmm2, %xmm5
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0]
|
||||
; SSSE3-NEXT: psubusw %xmm5, %xmm0
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: psubus_i16_i32_max_swapped:
|
||||
|
||||
@ -97,26 +97,20 @@ define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
|
||||
define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
|
||||
; X86-LABEL: func3:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: pushl %ebx
|
||||
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
|
||||
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
|
||||
; X86-NEXT: movzbl %cl, %edx
|
||||
; X86-NEXT: movzbl %al, %ebx
|
||||
; X86-NEXT: cmpb %al, %cl
|
||||
; X86-NEXT: cmoval %edx, %ebx
|
||||
; X86-NEXT: subb %al, %bl
|
||||
; X86-NEXT: movzbl %bl, %eax
|
||||
; X86-NEXT: xorl %ecx, %ecx
|
||||
; X86-NEXT: subb {{[0-9]+}}(%esp), %al
|
||||
; X86-NEXT: movzbl %al, %eax
|
||||
; X86-NEXT: cmovbl %ecx, %eax
|
||||
; X86-NEXT: andl $15, %eax
|
||||
; X86-NEXT: popl %ebx
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: func3:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: cmpb %sil, %dil
|
||||
; X64-NEXT: movl %esi, %eax
|
||||
; X64-NEXT: cmoval %edi, %eax
|
||||
; X64-NEXT: subb %sil, %al
|
||||
; X64-NEXT: movzbl %al, %eax
|
||||
; X64-NEXT: xorl %ecx, %ecx
|
||||
; X64-NEXT: subb %sil, %dil
|
||||
; X64-NEXT: movzbl %dil, %eax
|
||||
; X64-NEXT: cmovbl %ecx, %eax
|
||||
; X64-NEXT: andl $15, %eax
|
||||
; X64-NEXT: retq
|
||||
%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user