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[RISCV][NFC] Define and use the new CA instruction format
The RISC-V ISA manual was updated on 2018-11-07 (commit 00557c3) to define a new compressed instruction format, RVC format CA (no actual instruction encodings were changed). This patch updates the RISC-V backend to define the new format, and to use it in the relevant instructions. Differential Revision: https://reviews.llvm.org/D54302 Patch by Luís Marques. llvm-svn: 347043
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@ -45,11 +45,12 @@ def InstFormatCSS : InstFormat<10>;
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def InstFormatCIW : InstFormat<11>;
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def InstFormatCL : InstFormat<12>;
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def InstFormatCS : InstFormat<13>;
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def InstFormatCB : InstFormat<14>;
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def InstFormatCJ : InstFormat<15>;
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def InstFormatOther : InstFormat<16>;
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def InstFormatCA : InstFormat<14>;
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def InstFormatCB : InstFormat<15>;
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def InstFormatCJ : InstFormat<16>;
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def InstFormatOther : InstFormat<17>;
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// The following opcode names and match those given in Table 19.1 in the
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// The following opcode names match those given in Table 19.1 in the
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// RISC-V User-level ISA specification ("RISC-V base opcode map").
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class RISCVOpcode<bits<7> val> {
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bits<7> Value = val;
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@ -118,6 +118,19 @@ class RVInst16CS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
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let Inst{1-0} = opcode;
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}
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class RVInst16CA<bits<6> funct6, bits<2> funct2, bits<2> opcode, dag outs,
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dag ins, string opcodestr, string argstr>
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: RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCA> {
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bits<3> rs2;
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bits<3> rs1;
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let Inst{15-10} = funct6;
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let Inst{9-7} = rs1;
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let Inst{6-5} = funct2;
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let Inst{4-2} = rs2;
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let Inst{1-0} = opcode;
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}
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class RVInst16CB<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCB> {
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@ -258,16 +258,13 @@ class Shift_right<bits<2> funct2, string OpcodeStr, RegisterClass cls,
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class CS_ALU<bits<2> funct2, string OpcodeStr, RegisterClass cls,
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bit RV64only>
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: RVInst16CS<0b100, 0b01, (outs cls:$rd_wb), (ins cls:$rd, cls:$rs2),
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class CS_ALU<bits<6> funct6, bits<2> funct2, string OpcodeStr,
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RegisterClass cls>
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: RVInst16CA<funct6, funct2, 0b01, (outs cls:$rd_wb), (ins cls:$rd, cls:$rs2),
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OpcodeStr, "$rd, $rs2"> {
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bits<3> rd;
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let Constraints = "$rd = $rd_wb";
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let Inst{12} = RV64only;
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let Inst{11-10} = 0b11;
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let Inst{9-7} = rd;
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let Inst{6-5} = funct2;
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}
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//===----------------------------------------------------------------------===//
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@ -411,14 +408,14 @@ def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb), (ins GPRC:$rs1, simm6:
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let Inst{6-2} = imm{4-0};
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}
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def C_SUB : CS_ALU<0b00, "c.sub", GPRC, 0>;
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def C_XOR : CS_ALU<0b01, "c.xor", GPRC, 0>;
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def C_OR : CS_ALU<0b10, "c.or" , GPRC, 0>;
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def C_AND : CS_ALU<0b11, "c.and", GPRC, 0>;
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def C_SUB : CS_ALU<0b100011, 0b00, "c.sub", GPRC>;
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def C_XOR : CS_ALU<0b100011, 0b01, "c.xor", GPRC>;
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def C_OR : CS_ALU<0b100011, 0b10, "c.or" , GPRC>;
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def C_AND : CS_ALU<0b100011, 0b11, "c.and", GPRC>;
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let Predicates = [HasStdExtC, IsRV64] in {
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def C_SUBW : CS_ALU<0b00, "c.subw", GPRC, 1>;
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def C_ADDW : CS_ALU<0b01, "c.addw", GPRC, 1>;
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def C_SUBW : CS_ALU<0b100111, 0b00, "c.subw", GPRC>;
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def C_ADDW : CS_ALU<0b100111, 0b01, "c.addw", GPRC>;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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@ -39,9 +39,10 @@ enum {
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InstFormatCIW = 11,
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InstFormatCL = 12,
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InstFormatCS = 13,
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InstFormatCB = 14,
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InstFormatCJ = 15,
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InstFormatOther = 16,
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InstFormatCA = 14,
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InstFormatCB = 15,
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InstFormatCJ = 16,
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InstFormatOther = 17,
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InstFormatMask = 31
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};
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