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Thumb1 had two patterns for the same load-from-constant-pool instruction.
Canonicalize on tLDRpci and remove tLDRcp. llvm-svn: 121920
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@ -615,7 +615,6 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF,
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break;
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case ARM::tLDRpci:
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case ARM::tLDRcp:
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Bits = 8;
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Scale = 4; // +(offset_8*4)
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break;
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@ -2187,7 +2187,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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SDValue Pred = getAL(CurDAG);
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SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
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SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
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ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
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ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
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Ops, 4);
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} else {
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SDValue Ops[] = {
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@ -710,19 +710,6 @@ def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
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let Inst{7-0} = addr;
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}
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// Special LDR for loads from non-pc-relative constpools.
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let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
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isReMaterializable = 1 in
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def tLDRcp : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
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"ldr", "\t$Rt, $addr", []>,
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T1LdStSP<{1,?,?}> {
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// A6.2 & A8.6.57 T2
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bits<3> Rt;
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bits<8> addr;
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let Inst{10-8} = Rt;
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let Inst{7-0} = addr;
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}
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// A8.6.194 & A8.6.192
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defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
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t_addrmode_is4, AddrModeT1_4,
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@ -63,7 +63,7 @@ void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
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Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
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unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
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.addReg(DestReg, getDefRegState(true), SubIdx)
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.addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
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}
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@ -10,7 +10,7 @@ define void @test1() {
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define void @test2() {
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; CHECK: test2:
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; CHECK: ldr r0, LCPI
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; CHECK: ldr.n r0, LCPI
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; CHECK: add sp, r0
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; CHECK: subs r4, r7, #4
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; CHECK: mov sp, r4
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@ -20,9 +20,9 @@ define void @test2() {
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define i32 @test3() {
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; CHECK: test3:
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; CHECK: ldr r2, LCPI
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; CHECK: ldr.n r2, LCPI
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; CHECK: add sp, r2
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; CHECK: ldr r1, LCPI
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; CHECK: ldr.n r1, LCPI
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; CHECK: add r1, sp
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; CHECK: subs r4, r7, #4
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; CHECK: mov sp, r4
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