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[ARM] Add new system registers to ARMv8-M Baseline/Mainline
llvm-svn: 257884
This commit is contained in:
Bradley Smith
parent
c60b26bd62
commit
84c89d1ac3
@ -3444,6 +3444,9 @@ static inline int getMClassRegisterSYSmValueMask(StringRef RegString) {
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.Case("basepri_max", 0x12)
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.Case("faultmask", 0x13)
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.Case("control", 0x14)
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.Case("msplim", 0x0a)
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.Case("psplim", 0x0b)
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.Case("sp", 0x18)
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.Default(-1);
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}
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@ -3473,11 +3476,27 @@ static int getMClassRegisterMask(StringRef Reg, StringRef Flags, bool IsRead,
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if (!Subtarget->hasV7Ops() && SYSmvalue >= 0x11 && SYSmvalue <= 0x13)
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return -1;
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if (Subtarget->has8MSecExt() && Flags.lower() == "ns") {
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Flags = "";
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SYSmvalue |= 0x80;
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}
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if (!Subtarget->has8MSecExt() &&
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(SYSmvalue == 0xa || SYSmvalue == 0xb || SYSmvalue > 0x14))
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return -1;
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if (!Subtarget->hasV8MMainlineOps() &&
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(SYSmvalue == 0x8a || SYSmvalue == 0x8b || SYSmvalue == 0x91 ||
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SYSmvalue == 0x93))
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return -1;
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// If it was a read then we won't be expecting flags and so at this point
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// we can return the mask.
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if (IsRead) {
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assert (Flags.empty() && "Unexpected flags for reading M class register.");
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return SYSmvalue;
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if (Flags.empty())
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return SYSmvalue;
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else
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return -1;
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}
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// We know we are now handling a write so need to get the mask for the flags.
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@ -3636,7 +3655,13 @@ SDNode *ARMDAGToDAGISel::SelectReadRegister(SDNode *N){
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// is an acceptable value, so check that a mask can be constructed from the
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// string.
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if (Subtarget->isMClass()) {
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int SYSmValue = getMClassRegisterMask(SpecialReg, "", true, Subtarget);
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StringRef Flags = "", Reg = SpecialReg;
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if (Reg.endswith("_ns")) {
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Flags = "ns";
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Reg = Reg.drop_back(3);
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}
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int SYSmValue = getMClassRegisterMask(Reg, Flags, true, Subtarget);
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if (SYSmValue == -1)
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return nullptr;
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@ -3730,10 +3755,10 @@ SDNode *ARMDAGToDAGISel::SelectWriteRegister(SDNode *N){
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return CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
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}
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SmallVector<StringRef, 5> Fields;
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StringRef(SpecialReg).split(Fields, '_', 1, false);
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std::string Reg = Fields[0].str();
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StringRef Flags = Fields.size() == 2 ? Fields[1] : "";
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std::pair<StringRef, StringRef> Fields;
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Fields = StringRef(SpecialReg).rsplit('_');
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std::string Reg = Fields.first.str();
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StringRef Flags = Fields.second;
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// If the target was M Class then need to validate the special register value
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// and retrieve the mask for use in the instruction node.
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@ -272,6 +272,12 @@ class ARMAsmParser : public MCTargetAsmParser {
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bool hasV8MBaseline() const {
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return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
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}
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bool hasV8MMainline() const {
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return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
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}
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bool has8MSecExt() const {
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return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
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}
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bool hasARM() const {
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return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
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}
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@ -3972,6 +3978,18 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
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.Case("basepri_max", 0x812)
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.Case("faultmask", 0x813)
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.Case("control", 0x814)
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.Case("msplim", 0x80a)
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.Case("psplim", 0x80b)
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.Case("msp_ns", 0x888)
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.Case("psp_ns", 0x889)
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.Case("msplim_ns", 0x88a)
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.Case("psplim_ns", 0x88b)
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.Case("primask_ns", 0x890)
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.Case("basepri_ns", 0x891)
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.Case("basepri_max_ns", 0x892)
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.Case("faultmask_ns", 0x893)
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.Case("control_ns", 0x894)
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.Case("sp_ns", 0x898)
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.Default(~0U);
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if (FlagsVal == ~0U)
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@ -3986,6 +4004,14 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
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// basepri, basepri_max and faultmask only valid for V7m.
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return MatchOperand_NoMatch;
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if (!has8MSecExt() && (FlagsVal == 0x80a || FlagsVal == 0x80b ||
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(FlagsVal > 0x814 && FlagsVal < 0xc00)))
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return MatchOperand_NoMatch;
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if (!hasV8MMainline() && (FlagsVal == 0x88a || FlagsVal == 0x88b ||
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(FlagsVal > 0x890 && FlagsVal <= 0x893)))
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return MatchOperand_NoMatch;
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Parser.Lex(); // Eat identifier token.
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Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
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return MatchOperand_Success;
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@ -4096,6 +4096,24 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
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// Values basepri, basepri_max and faultmask are only valid for v7m.
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return MCDisassembler::Fail;
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break;
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case 0x8a: // msplim_ns
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case 0x8b: // psplim_ns
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case 0x91: // basepri_ns
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case 0x92: // basepri_max_ns
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case 0x93: // faultmask_ns
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if (!(FeatureBits[ARM::HasV8MMainlineOps]))
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return MCDisassembler::Fail;
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// fall through
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case 10: // msplim
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case 11: // psplim
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case 0x88: // msp_ns
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case 0x89: // psp_ns
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case 0x90: // primask_ns
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case 0x94: // control_ns
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case 0x98: // sp_ns
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if (!(FeatureBits[ARM::Feature8MSecExt]))
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return MCDisassembler::Fail;
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break;
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default:
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return MCDisassembler::Fail;
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}
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@ -901,6 +901,42 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
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case 20:
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O << "control";
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return;
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case 10:
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O << "msplim";
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return;
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case 11:
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O << "psplim";
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return;
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case 0x88:
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O << "msp_ns";
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return;
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case 0x89:
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O << "psp_ns";
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return;
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case 0x8a:
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O << "msplim_ns";
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return;
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case 0x8b:
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O << "psplim_ns";
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return;
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case 0x90:
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O << "primask_ns";
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return;
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case 0x91:
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O << "basepri_ns";
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return;
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case 0x92:
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O << "basepri_max_ns";
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return;
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case 0x93:
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O << "faultmask_ns";
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return;
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case 0x94:
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O << "control_ns";
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return;
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case 0x98:
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O << "sp_ns";
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return;
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}
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}
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142
test/CodeGen/ARM/special-reg-v8m-base.ll
Normal file
142
test/CodeGen/ARM/special-reg-v8m-base.ll
Normal file
@ -0,0 +1,142 @@
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; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=V7M
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; RUN: llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s
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; V7M: LLVM ERROR: Invalid register name "sp_ns".
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define i32 @read_mclass_registers() nounwind {
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entry:
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; CHECK-LABEL: read_mclass_registers:
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; CHECK: mrs r0, apsr
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; CHECK: mrs r1, iapsr
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; CHECK: mrs r1, eapsr
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; CHECK: mrs r1, xpsr
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; CHECK: mrs r1, ipsr
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; CHECK: mrs r1, epsr
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; CHECK: mrs r1, iepsr
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; CHECK: mrs r1, msp
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; CHECK: mrs r1, psp
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; CHECK: mrs r1, primask
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; CHECK: mrs r1, control
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; CHECK: mrs r1, msplim
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; CHECK: mrs r1, psplim
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; CHECK: mrs r1, msp_ns
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; CHECK: mrs r1, psp_ns
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; CHECK: mrs r1, primask_ns
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; CHECK: mrs r1, control_ns
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; CHECK: mrs r1, sp_ns
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%0 = call i32 @llvm.read_register.i32(metadata !0)
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%1 = call i32 @llvm.read_register.i32(metadata !4)
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%add1 = add i32 %1, %0
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%2 = call i32 @llvm.read_register.i32(metadata !8)
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%add2 = add i32 %add1, %2
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%3 = call i32 @llvm.read_register.i32(metadata !12)
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%add3 = add i32 %add2, %3
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%4 = call i32 @llvm.read_register.i32(metadata !16)
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%add4 = add i32 %add3, %4
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%5 = call i32 @llvm.read_register.i32(metadata !17)
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%add5 = add i32 %add4, %5
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%6 = call i32 @llvm.read_register.i32(metadata !18)
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%add6 = add i32 %add5, %6
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%7 = call i32 @llvm.read_register.i32(metadata !19)
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%add7 = add i32 %add6, %7
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%8 = call i32 @llvm.read_register.i32(metadata !20)
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%add8 = add i32 %add7, %8
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%9 = call i32 @llvm.read_register.i32(metadata !21)
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%add9 = add i32 %add8, %9
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%10 = call i32 @llvm.read_register.i32(metadata !25)
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%add10 = add i32 %add9, %10
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%11 = call i32 @llvm.read_register.i32(metadata !26)
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%add11 = add i32 %add10, %11
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%12 = call i32 @llvm.read_register.i32(metadata !27)
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%add12 = add i32 %add11, %12
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%13 = call i32 @llvm.read_register.i32(metadata !28)
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%add13 = add i32 %add12, %13
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%14 = call i32 @llvm.read_register.i32(metadata !29)
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%add14 = add i32 %add13, %14
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%15 = call i32 @llvm.read_register.i32(metadata !32)
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%add15 = add i32 %add14, %15
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%16 = call i32 @llvm.read_register.i32(metadata !35)
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%add16 = add i32 %add15, %16
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%17 = call i32 @llvm.read_register.i32(metadata !36)
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%add17 = add i32 %add16, %17
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ret i32 %add10
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}
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define void @write_mclass_registers(i32 %x) nounwind {
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entry:
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; CHECK-LABEL: write_mclass_registers:
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; CHECK: msr apsr, r0
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; CHECK: msr apsr, r0
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; CHECK: msr iapsr, r0
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; CHECK: msr iapsr, r0
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; CHECK: msr eapsr, r0
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; CHECK: msr eapsr, r0
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; CHECK: msr xpsr, r0
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; CHECK: msr xpsr, r0
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; CHECK: msr ipsr, r0
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; CHECK: msr epsr, r0
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; CHECK: msr iepsr, r0
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; CHECK: msr msp, r0
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; CHECK: msr psp, r0
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; CHECK: msr primask, r0
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; CHECK: msr control, r0
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; CHECK: msr msplim, r0
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; CHECK: msr psplim, r0
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; CHECK: msr msp_ns, r0
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; CHECK: msr psp_ns, r0
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; CHECK: msr primask_ns, r0
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; CHECK: msr control_ns, r0
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; CHECK: msr sp_ns, r0
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call void @llvm.write_register.i32(metadata !0, i32 %x)
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call void @llvm.write_register.i32(metadata !1, i32 %x)
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call void @llvm.write_register.i32(metadata !4, i32 %x)
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call void @llvm.write_register.i32(metadata !5, i32 %x)
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call void @llvm.write_register.i32(metadata !8, i32 %x)
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call void @llvm.write_register.i32(metadata !9, i32 %x)
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call void @llvm.write_register.i32(metadata !12, i32 %x)
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call void @llvm.write_register.i32(metadata !13, i32 %x)
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call void @llvm.write_register.i32(metadata !16, i32 %x)
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call void @llvm.write_register.i32(metadata !17, i32 %x)
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call void @llvm.write_register.i32(metadata !18, i32 %x)
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call void @llvm.write_register.i32(metadata !19, i32 %x)
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call void @llvm.write_register.i32(metadata !20, i32 %x)
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call void @llvm.write_register.i32(metadata !21, i32 %x)
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call void @llvm.write_register.i32(metadata !25, i32 %x)
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call void @llvm.write_register.i32(metadata !26, i32 %x)
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call void @llvm.write_register.i32(metadata !27, i32 %x)
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call void @llvm.write_register.i32(metadata !28, i32 %x)
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call void @llvm.write_register.i32(metadata !29, i32 %x)
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call void @llvm.write_register.i32(metadata !32, i32 %x)
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call void @llvm.write_register.i32(metadata !35, i32 %x)
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call void @llvm.write_register.i32(metadata !36, i32 %x)
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ret void
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}
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declare i32 @llvm.read_register.i32(metadata) nounwind
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declare void @llvm.write_register.i32(metadata, i32) nounwind
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!0 = !{!"apsr"}
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!1 = !{!"apsr_nzcvq"}
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!4 = !{!"iapsr"}
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!5 = !{!"iapsr_nzcvq"}
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!8 = !{!"eapsr"}
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!9 = !{!"eapsr_nzcvq"}
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!12 = !{!"xpsr"}
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!13 = !{!"xpsr_nzcvq"}
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!16 = !{!"ipsr"}
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!17 = !{!"epsr"}
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!18 = !{!"iepsr"}
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!19 = !{!"msp"}
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!20 = !{!"psp"}
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!21 = !{!"primask"}
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!25 = !{!"control"}
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!26 = !{!"msplim"}
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!27 = !{!"psplim"}
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!28 = !{!"msp_ns"}
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!29 = !{!"psp_ns"}
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!32 = !{!"primask_ns"}
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!35 = !{!"control_ns"}
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!36 = !{!"sp_ns"}
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214
test/CodeGen/ARM/special-reg-v8m-main.ll
Normal file
214
test/CodeGen/ARM/special-reg-v8m-main.ll
Normal file
@ -0,0 +1,214 @@
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; RUN: not llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s --check-prefix=BASELINE
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; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -mattr=+dsp 2>&1 | FileCheck %s --check-prefix=MAINLINE
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; BASELINE: LLVM ERROR: Invalid register name "basepri_max_ns".
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define i32 @read_mclass_registers() nounwind {
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entry:
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; MAINLINE-LABEL: read_mclass_registers:
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; MAINLINE: mrs r0, apsr
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; MAINLINE: mrs r1, iapsr
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; MAINLINE: mrs r1, eapsr
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; MAINLINE: mrs r1, xpsr
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; MAINLINE: mrs r1, ipsr
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; MAINLINE: mrs r1, epsr
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; MAINLINE: mrs r1, iepsr
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; MAINLINE: mrs r1, msp
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; MAINLINE: mrs r1, psp
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; MAINLINE: mrs r1, primask
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; MAINLINE: mrs r1, basepri
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; MAINLINE: mrs r1, basepri_max
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; MAINLINE: mrs r1, faultmask
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; MAINLINE: mrs r1, control
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; MAINLINE: mrs r1, msplim
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; MAINLINE: mrs r1, psplim
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; MAINLINE: mrs r1, msp_ns
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; MAINLINE: mrs r1, psp_ns
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; MAINLINE: mrs r1, msplim_ns
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; MAINLINE: mrs r1, psplim_ns
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; MAINLINE: mrs r1, primask_ns
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; MAINLINE: mrs r1, basepri_ns
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; MAINLINE: mrs r1, faultmask_ns
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; MAINLINE: mrs r1, control_ns
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; MAINLINE: mrs r1, sp_ns
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; MAINLINE: mrs r1, basepri_max_ns
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%0 = call i32 @llvm.read_register.i32(metadata !0)
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%1 = call i32 @llvm.read_register.i32(metadata !4)
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%add1 = add i32 %1, %0
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%2 = call i32 @llvm.read_register.i32(metadata !8)
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%add2 = add i32 %add1, %2
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%3 = call i32 @llvm.read_register.i32(metadata !12)
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%add3 = add i32 %add2, %3
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%4 = call i32 @llvm.read_register.i32(metadata !16)
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%add4 = add i32 %add3, %4
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%5 = call i32 @llvm.read_register.i32(metadata !17)
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%add5 = add i32 %add4, %5
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%6 = call i32 @llvm.read_register.i32(metadata !18)
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%add6 = add i32 %add5, %6
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%7 = call i32 @llvm.read_register.i32(metadata !19)
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%add7 = add i32 %add6, %7
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%8 = call i32 @llvm.read_register.i32(metadata !20)
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%add8 = add i32 %add7, %8
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%9 = call i32 @llvm.read_register.i32(metadata !21)
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%add9 = add i32 %add8, %9
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%10 = call i32 @llvm.read_register.i32(metadata !22)
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%add10 = add i32 %add9, %10
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%11 = call i32 @llvm.read_register.i32(metadata !23)
|
||||
%add11 = add i32 %add10, %11
|
||||
%12 = call i32 @llvm.read_register.i32(metadata !24)
|
||||
%add12 = add i32 %add11, %12
|
||||
%13 = call i32 @llvm.read_register.i32(metadata !25)
|
||||
%add13 = add i32 %add12, %13
|
||||
%14 = call i32 @llvm.read_register.i32(metadata !26)
|
||||
%add14 = add i32 %add13, %14
|
||||
%15 = call i32 @llvm.read_register.i32(metadata !27)
|
||||
%add15 = add i32 %add14, %15
|
||||
%16 = call i32 @llvm.read_register.i32(metadata !28)
|
||||
%add16 = add i32 %add15, %16
|
||||
%17 = call i32 @llvm.read_register.i32(metadata !29)
|
||||
%add17 = add i32 %add16, %17
|
||||
%18 = call i32 @llvm.read_register.i32(metadata !30)
|
||||
%add18 = add i32 %add17, %18
|
||||
%19 = call i32 @llvm.read_register.i32(metadata !31)
|
||||
%add19 = add i32 %add18, %19
|
||||
%20 = call i32 @llvm.read_register.i32(metadata !32)
|
||||
%add20 = add i32 %add19, %20
|
||||
%21 = call i32 @llvm.read_register.i32(metadata !33)
|
||||
%add21 = add i32 %add20, %21
|
||||
%22 = call i32 @llvm.read_register.i32(metadata !34)
|
||||
%add22 = add i32 %add21, %22
|
||||
%23 = call i32 @llvm.read_register.i32(metadata !35)
|
||||
%add23 = add i32 %add22, %23
|
||||
%24 = call i32 @llvm.read_register.i32(metadata !36)
|
||||
%add24 = add i32 %add23, %24
|
||||
%25 = call i32 @llvm.read_register.i32(metadata !37)
|
||||
%add25 = add i32 %add24, %25
|
||||
ret i32 %add25
|
||||
}
|
||||
|
||||
define void @write_mclass_registers(i32 %x) nounwind {
|
||||
entry:
|
||||
; MAINLINE-LABEL: write_mclass_registers:
|
||||
; MAINLINE: msr apsr_nzcvqg, r0
|
||||
; MAINLINE: msr apsr_nzcvq, r0
|
||||
; MAINLINE: msr apsr_g, r0
|
||||
; MAINLINE: msr apsr_nzcvqg, r0
|
||||
; MAINLINE: msr iapsr_nzcvqg, r0
|
||||
; MAINLINE: msr iapsr_nzcvq, r0
|
||||
; MAINLINE: msr iapsr_g, r0
|
||||
; MAINLINE: msr iapsr_nzcvqg, r0
|
||||
; MAINLINE: msr eapsr_nzcvqg, r0
|
||||
; MAINLINE: msr eapsr_nzcvq, r0
|
||||
; MAINLINE: msr eapsr_g, r0
|
||||
; MAINLINE: msr eapsr_nzcvqg, r0
|
||||
; MAINLINE: msr xpsr_nzcvqg, r0
|
||||
; MAINLINE: msr xpsr_nzcvq, r0
|
||||
; MAINLINE: msr xpsr_g, r0
|
||||
; MAINLINE: msr xpsr_nzcvqg, r0
|
||||
; MAINLINE: msr ipsr, r0
|
||||
; MAINLINE: msr epsr, r0
|
||||
; MAINLINE: msr iepsr, r0
|
||||
; MAINLINE: msr msp, r0
|
||||
; MAINLINE: msr psp, r0
|
||||
; MAINLINE: msr primask, r0
|
||||
; MAINLINE: msr basepri, r0
|
||||
; MAINLINE: msr basepri_max, r0
|
||||
; MAINLINE: msr faultmask, r0
|
||||
; MAINLINE: msr control, r0
|
||||
; MAINLINE: msr msplim, r0
|
||||
; MAINLINE: msr psplim, r0
|
||||
; MAINLINE: msr msp_ns, r0
|
||||
; MAINLINE: msr psp_ns, r0
|
||||
; MAINLINE: msr msplim_ns, r0
|
||||
; MAINLINE: msr psplim_ns, r0
|
||||
; MAINLINE: msr primask_ns, r0
|
||||
; MAINLINE: msr basepri_ns, r0
|
||||
; MAINLINE: msr faultmask_ns, r0
|
||||
; MAINLINE: msr control_ns, r0
|
||||
; MAINLINE: msr sp_ns, r0
|
||||
; MAINLINE: msr basepri_max_ns, r0
|
||||
|
||||
call void @llvm.write_register.i32(metadata !0, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !1, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !2, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !3, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !4, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !5, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !6, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !7, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !8, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !9, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !10, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !11, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !12, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !13, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !14, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !15, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !16, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !17, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !18, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !19, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !20, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !21, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !22, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !23, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !24, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !25, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !26, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !27, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !28, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !29, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !30, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !31, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !32, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !33, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !34, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !35, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !36, i32 %x)
|
||||
call void @llvm.write_register.i32(metadata !37, i32 %x)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.read_register.i32(metadata) nounwind
|
||||
declare void @llvm.write_register.i32(metadata, i32) nounwind
|
||||
|
||||
!0 = !{!"apsr"}
|
||||
!1 = !{!"apsr_nzcvq"}
|
||||
!2 = !{!"apsr_g"}
|
||||
!3 = !{!"apsr_nzcvqg"}
|
||||
!4 = !{!"iapsr"}
|
||||
!5 = !{!"iapsr_nzcvq"}
|
||||
!6 = !{!"iapsr_g"}
|
||||
!7 = !{!"iapsr_nzcvqg"}
|
||||
!8 = !{!"eapsr"}
|
||||
!9 = !{!"eapsr_nzcvq"}
|
||||
!10 = !{!"eapsr_g"}
|
||||
!11 = !{!"eapsr_nzcvqg"}
|
||||
!12 = !{!"xpsr"}
|
||||
!13 = !{!"xpsr_nzcvq"}
|
||||
!14 = !{!"xpsr_g"}
|
||||
!15 = !{!"xpsr_nzcvqg"}
|
||||
!16 = !{!"ipsr"}
|
||||
!17 = !{!"epsr"}
|
||||
!18 = !{!"iepsr"}
|
||||
!19 = !{!"msp"}
|
||||
!20 = !{!"psp"}
|
||||
!21 = !{!"primask"}
|
||||
!22 = !{!"basepri"}
|
||||
!23 = !{!"basepri_max"}
|
||||
!24 = !{!"faultmask"}
|
||||
!25 = !{!"control"}
|
||||
!26 = !{!"msplim"}
|
||||
!27 = !{!"psplim"}
|
||||
!28 = !{!"msp_ns"}
|
||||
!29 = !{!"psp_ns"}
|
||||
!30 = !{!"msplim_ns"}
|
||||
!31 = !{!"psplim_ns"}
|
||||
!32 = !{!"primask_ns"}
|
||||
!33 = !{!"basepri_ns"}
|
||||
!34 = !{!"faultmask_ns"}
|
||||
!35 = !{!"control_ns"}
|
||||
!36 = !{!"sp_ns"}
|
||||
!37 = !{!"basepri_max_ns"}
|
||||
|
||||
@ -163,6 +163,42 @@ vlldm r5
|
||||
// CHECK-MAINLINE: vlstm r10 @ encoding: [0x2a,0xec,0x00,0x0a]
|
||||
vlstm r10
|
||||
|
||||
// New SYSm's
|
||||
|
||||
MRS r1, MSP_NS
|
||||
// CHECK: mrs r1, msp_ns @ encoding: [0xef,0xf3,0x88,0x81]
|
||||
MSR PSP_NS, r2
|
||||
// CHECK: msr psp_ns, r2 @ encoding: [0x82,0xf3,0x89,0x88]
|
||||
MRS r3, PRIMASK_NS
|
||||
// CHECK: mrs r3, primask_ns @ encoding: [0xef,0xf3,0x90,0x83]
|
||||
MSR CONTROL_NS, r4
|
||||
// CHECK: msr control_ns, r4 @ encoding: [0x84,0xf3,0x94,0x88]
|
||||
MRS r5, SP_NS
|
||||
// CHECK: mrs r5, sp_ns @ encoding: [0xef,0xf3,0x98,0x85]
|
||||
MRS r6,MSPLIM
|
||||
// CHECK: mrs r6, msplim @ encoding: [0xef,0xf3,0x0a,0x86]
|
||||
MRS r7,PSPLIM
|
||||
// CHECK: mrs r7, psplim @ encoding: [0xef,0xf3,0x0b,0x87]
|
||||
MSR MSPLIM,r8
|
||||
// CHECK: msr msplim, r8 @ encoding: [0x88,0xf3,0x0a,0x88]
|
||||
MSR PSPLIM,r9
|
||||
// CHECK: msr psplim, r9 @ encoding: [0x89,0xf3,0x0b,0x88]
|
||||
|
||||
MRS r10, MSPLIM_NS
|
||||
// CHECK-MAINLINE: mrs r10, msplim_ns @ encoding: [0xef,0xf3,0x8a,0x8a]
|
||||
// UNDEF-BASELINE: error: invalid operand for instruction
|
||||
MSR PSPLIM_NS, r11
|
||||
// CHECK-MAINLINE: msr psplim_ns, r11 @ encoding: [0x8b,0xf3,0x8b,0x88]
|
||||
// UNDEF-BASELINE: error: invalid operand for instruction
|
||||
MRS r12, BASEPRI_NS
|
||||
// CHECK-MAINLINE: mrs r12, basepri_ns @ encoding: [0xef,0xf3,0x91,0x8c]
|
||||
// UNDEF-BASELINE: error: invalid operand for instruction
|
||||
MRS r12, BASEPRI_MAX_NS
|
||||
// CHECK-MAINLINE: mrs r12, basepri_max_ns @ encoding: [0xef,0xf3,0x92,0x8c]
|
||||
// UNDEF-BASELINE: error: invalid operand for instruction
|
||||
MSR FAULTMASK_NS, r14
|
||||
// CHECK-MAINLINE: msr faultmask_ns, lr @ encoding: [0x8e,0xf3,0x93,0x88]
|
||||
// UNDEF-BASELINE: error: invalid operand for instruction
|
||||
|
||||
// Invalid operand tests
|
||||
// UNDEF: error: invalid operand for instruction
|
||||
|
||||
25
test/MC/Disassembler/ARM/thumb2-v8m.txt
Normal file
25
test/MC/Disassembler/ARM/thumb2-v8m.txt
Normal file
@ -0,0 +1,25 @@
|
||||
# RUN: llvm-mc -triple=thumbv8m.base -disassemble < %s 2>%t | FileCheck %s
|
||||
# RUN: FileCheck < %t %s --check-prefix=CHECK-STDERR
|
||||
# RUN: llvm-mc -triple=thumbv8m.main -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MAINLINE
|
||||
|
||||
0xef 0xf3 0x0a 0x83
|
||||
# CHECK: mrs r3, msplim
|
||||
0xef 0xf3 0x0b 0x84
|
||||
# CHECK: mrs r4, psplim
|
||||
0x8b 0xf3 0x0a 0x88
|
||||
# CHECK: msr msplim, r11
|
||||
0x8c 0xf3 0x0b 0x88
|
||||
# CHECK: msr psplim, r12
|
||||
|
||||
0xef 0xf3 0x90 0x86
|
||||
# CHECK: mrs r6, primask_ns
|
||||
0x88 0xf3 0x98 0x88
|
||||
# CHECK: msr sp_ns, r8
|
||||
|
||||
0xef 0xf3 0x8a 0x85
|
||||
# CHECK-STDERR: warning: invalid instruction encoding
|
||||
# CHECK-MAINLINE: mrs r5, msplim_ns
|
||||
0x87 0xf3 0x93 0x88
|
||||
# CHECK-STDERR: warning: invalid instruction encoding
|
||||
# CHECK-MAINLINE: msr faultmask_ns, r7
|
||||
|
||||
Loading…
Reference in New Issue
Block a user