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[ARM] Add MVE vector compare instructions.
Summary: These take a pair of vector register to compare, and a comparison type (written in the form of an Arm condition suffix); they output a vector of booleans in the VPR register, where predication can conveniently use them. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62676 llvm-svn: 364027
This commit is contained in:
Simon Tatham
parent
a2428a85c5
commit
84e2268946
@ -62,6 +62,8 @@ def pred_restricted_i_asmoperand : AsmOperandClass {
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let RenderMethod = "addITCondCodeOperands";
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let PredicateMethod = "isITCondCodeRestrictedI";
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let ParserMethod = "parseITCondCode";
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let DiagnosticString = "condition code for sign-independent integer "#
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"comparison must be EQ or NE";
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}
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// VPT/VCMP restricted predicate for signed types
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@ -70,6 +72,8 @@ def pred_restricted_s_asmoperand : AsmOperandClass {
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let RenderMethod = "addITCondCodeOperands";
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let PredicateMethod = "isITCondCodeRestrictedS";
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let ParserMethod = "parseITCondCode";
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let DiagnosticString = "condition code for signed integer "#
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"comparison must be EQ, NE, LT, GT, LE or GE";
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}
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// VPT/VCMP restricted predicate for unsigned types
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@ -78,6 +82,8 @@ def pred_restricted_u_asmoperand : AsmOperandClass {
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let RenderMethod = "addITCondCodeOperands";
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let PredicateMethod = "isITCondCodeRestrictedU";
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let ParserMethod = "parseITCondCode";
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let DiagnosticString = "condition code for unsigned integer "#
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"comparison must be EQ, NE, HS or HI";
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}
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// VPT/VCMP restricted predicate for floating point
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@ -86,30 +92,34 @@ def pred_restricted_fp_asmoperand : AsmOperandClass {
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let RenderMethod = "addITCondCodeOperands";
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let PredicateMethod = "isITCondCodeRestrictedFP";
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let ParserMethod = "parseITCondCode";
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let DiagnosticString = "condition code for floating-point "#
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"comparison must be EQ, NE, LT, GT, LE or GE";
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}
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def pred_basic_i : Operand<i32> {
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class VCMPPredicateOperand : Operand<i32>;
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def pred_basic_i : VCMPPredicateOperand {
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let PrintMethod = "printMandatoryRestrictedPredicateOperand";
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let ParserMatchClass = pred_restricted_i_asmoperand;
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let DecoderMethod = "DecodeRestrictedIPredicateOperand";
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let EncoderMethod = "getRestrictedCondCodeOpValue";
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}
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def pred_basic_u : Operand<i32> {
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def pred_basic_u : VCMPPredicateOperand {
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let PrintMethod = "printMandatoryRestrictedPredicateOperand";
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let ParserMatchClass = pred_restricted_u_asmoperand;
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let DecoderMethod = "DecodeRestrictedUPredicateOperand";
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let EncoderMethod = "getRestrictedCondCodeOpValue";
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}
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def pred_basic_s : Operand<i32> {
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def pred_basic_s : VCMPPredicateOperand {
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let PrintMethod = "printMandatoryRestrictedPredicateOperand";
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let ParserMatchClass = pred_restricted_s_asmoperand;
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let DecoderMethod = "DecodeRestrictedSPredicateOperand";
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let EncoderMethod = "getRestrictedCondCodeOpValue";
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}
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def pred_basic_fp : Operand<i32> {
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def pred_basic_fp : VCMPPredicateOperand {
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let PrintMethod = "printMandatoryRestrictedPredicateOperand";
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let ParserMatchClass = pred_restricted_fp_asmoperand;
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let DecoderMethod = "DecodeRestrictedFPPredicateOperand";
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@ -2253,6 +2263,147 @@ def MVE_VMINNMAf16 : MVE_VMAXMINNMA<"vminnma", "f16", 0b1, 0b1>;
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// end of MVE Floating Point instructions
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// start of MVE compares
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class MVE_VCMPqq<string suffix, bit bit_28, bits<2> bits_21_20,
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VCMPPredicateOperand predtype, list<dag> pattern=[]>
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: MVE_p<(outs VCCR:$P0), (ins MQPR:$Qn, MQPR:$Qm, predtype:$fc),
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NoItinerary, "vcmp", suffix, "$fc, $Qn, $Qm", vpred_n, "", pattern> {
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// Base class for comparing two vector registers
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bits<3> fc;
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bits<4> Qn;
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bits<4> Qm;
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let Inst{28} = bit_28;
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let Inst{25-22} = 0b1000;
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let Inst{21-20} = bits_21_20;
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let Inst{19-17} = Qn{2-0};
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let Inst{16-13} = 0b1000;
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let Inst{12} = fc{2};
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let Inst{11-8} = 0b1111;
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let Inst{7} = fc{0};
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let Inst{6} = 0b0;
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let Inst{5} = Qm{3};
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let Inst{4} = 0b0;
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let Inst{3-1} = Qm{2-0};
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let Inst{0} = fc{1};
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let Constraints = "";
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// We need a custom decoder method for these instructions because of
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// the output VCCR operand, which isn't encoded in the instruction
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// bits anywhere (there is only one choice for it) but has to be
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// included in the MC operands so that codegen will be able to track
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// its data flow between instructions, spill/reload it when
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// necessary, etc. There seems to be no way to get the Tablegen
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// decoder to emit an operand that isn't affected by any instruction
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// bit.
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let DecoderMethod = "DecodeMVEVCMP<false," # predtype.DecoderMethod # ">";
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}
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class MVE_VCMPqqf<string suffix, bit size>
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: MVE_VCMPqq<suffix, size, 0b11, pred_basic_fp> {
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let Predicates = [HasMVEFloat];
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}
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class MVE_VCMPqqi<string suffix, bits<2> size>
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: MVE_VCMPqq<suffix, 0b1, size, pred_basic_i> {
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let Inst{12} = 0b0;
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let Inst{0} = 0b0;
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}
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class MVE_VCMPqqu<string suffix, bits<2> size>
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: MVE_VCMPqq<suffix, 0b1, size, pred_basic_u> {
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let Inst{12} = 0b0;
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let Inst{0} = 0b1;
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}
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class MVE_VCMPqqs<string suffix, bits<2> size>
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: MVE_VCMPqq<suffix, 0b1, size, pred_basic_s> {
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let Inst{12} = 0b1;
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}
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def MVE_VCMPf32 : MVE_VCMPqqf<"f32", 0b0>;
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def MVE_VCMPf16 : MVE_VCMPqqf<"f16", 0b1>;
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def MVE_VCMPi8 : MVE_VCMPqqi<"i8", 0b00>;
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def MVE_VCMPi16 : MVE_VCMPqqi<"i16", 0b01>;
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def MVE_VCMPi32 : MVE_VCMPqqi<"i32", 0b10>;
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def MVE_VCMPu8 : MVE_VCMPqqu<"u8", 0b00>;
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def MVE_VCMPu16 : MVE_VCMPqqu<"u16", 0b01>;
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def MVE_VCMPu32 : MVE_VCMPqqu<"u32", 0b10>;
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def MVE_VCMPs8 : MVE_VCMPqqs<"s8", 0b00>;
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def MVE_VCMPs16 : MVE_VCMPqqs<"s16", 0b01>;
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def MVE_VCMPs32 : MVE_VCMPqqs<"s32", 0b10>;
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class MVE_VCMPqr<string suffix, bit bit_28, bits<2> bits_21_20,
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VCMPPredicateOperand predtype, list<dag> pattern=[]>
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: MVE_p<(outs VCCR:$P0), (ins MQPR:$Qn, GPRwithZR:$Rm, predtype:$fc),
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NoItinerary, "vcmp", suffix, "$fc, $Qn, $Rm", vpred_n, "", pattern> {
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// Base class for comparing a vector register with a scalar
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bits<3> fc;
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bits<4> Qn;
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bits<4> Rm;
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let Inst{28} = bit_28;
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let Inst{25-22} = 0b1000;
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let Inst{21-20} = bits_21_20;
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let Inst{19-17} = Qn{2-0};
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let Inst{16-13} = 0b1000;
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let Inst{12} = fc{2};
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let Inst{11-8} = 0b1111;
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let Inst{7} = fc{0};
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let Inst{6} = 0b1;
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let Inst{5} = fc{1};
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let Inst{4} = 0b0;
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let Inst{3-0} = Rm{3-0};
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let Constraints = "";
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// Custom decoder method, for the same reason as MVE_VCMPqq
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let DecoderMethod = "DecodeMVEVCMP<true," # predtype.DecoderMethod # ">";
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}
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class MVE_VCMPqrf<string suffix, bit size>
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: MVE_VCMPqr<suffix, size, 0b11, pred_basic_fp> {
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let Predicates = [HasMVEFloat];
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}
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class MVE_VCMPqri<string suffix, bits<2> size>
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: MVE_VCMPqr<suffix, 0b1, size, pred_basic_i> {
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let Inst{12} = 0b0;
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let Inst{5} = 0b0;
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}
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class MVE_VCMPqru<string suffix, bits<2> size>
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: MVE_VCMPqr<suffix, 0b1, size, pred_basic_u> {
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let Inst{12} = 0b0;
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let Inst{5} = 0b1;
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}
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class MVE_VCMPqrs<string suffix, bits<2> size>
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: MVE_VCMPqr<suffix, 0b1, size, pred_basic_s> {
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let Inst{12} = 0b1;
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}
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def MVE_VCMPf32r : MVE_VCMPqrf<"f32", 0b0>;
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def MVE_VCMPf16r : MVE_VCMPqrf<"f16", 0b1>;
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def MVE_VCMPi8r : MVE_VCMPqri<"i8", 0b00>;
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def MVE_VCMPi16r : MVE_VCMPqri<"i16", 0b01>;
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def MVE_VCMPi32r : MVE_VCMPqri<"i32", 0b10>;
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def MVE_VCMPu8r : MVE_VCMPqru<"u8", 0b00>;
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def MVE_VCMPu16r : MVE_VCMPqru<"u16", 0b01>;
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def MVE_VCMPu32r : MVE_VCMPqru<"u32", 0b10>;
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def MVE_VCMPs8r : MVE_VCMPqrs<"s8", 0b00>;
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def MVE_VCMPs16r : MVE_VCMPqrs<"s16", 0b01>;
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def MVE_VCMPs32r : MVE_VCMPqrs<"s32", 0b10>;
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// end of MVE compares
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class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
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: MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
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bits<3> fc;
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@ -6568,6 +6568,7 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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// scalar predication operand we do not add the vector one and leave until
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// now to fix it up.
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if (CanAcceptVPTPredicationCode && Mnemonic != "vmov" &&
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!Mnemonic.startswith("vcmp") &&
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!(Mnemonic.startswith("vcvt") && Mnemonic != "vcvta" &&
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Mnemonic != "vcvtn" && Mnemonic != "vcvtp" && Mnemonic != "vcvtm")) {
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SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
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@ -6683,12 +6684,12 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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Operands.insert(Operands.begin(),
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ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
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}
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// For vmov instructions, as mentioned earlier, we did not add the vector
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// For vmov and vcmp, as mentioned earlier, we did not add the vector
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// predication code, since these may contain operands that require
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// special parsing. So now we have to see if they require vector
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// predication and replace the scalar one with the vector predication
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// operand if that is the case.
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else if (Mnemonic == "vmov" ||
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else if (Mnemonic == "vmov" || Mnemonic.startswith("vcmp") ||
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(Mnemonic.startswith("vcvt") && !Mnemonic.startswith("vcvta") &&
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!Mnemonic.startswith("vcvtn") && !Mnemonic.startswith("vcvtp") &&
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!Mnemonic.startswith("vcvtm"))) {
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@ -509,6 +509,11 @@ static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
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const void *Decoder);
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static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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template<bool scalar, OperandDecoder predicate_decoder>
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static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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@ -6183,3 +6188,41 @@ static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Addr
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return S;
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}
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template<bool scalar, OperandDecoder predicate_decoder>
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static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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Inst.addOperand(MCOperand::createReg(ARM::VPR));
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unsigned Qn = fieldFromInstruction(Insn, 17, 3);
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if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
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return MCDisassembler::Fail;
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unsigned fc;
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if (scalar) {
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fc = fieldFromInstruction(Insn, 12, 1) << 2 |
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fieldFromInstruction(Insn, 7, 1) |
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fieldFromInstruction(Insn, 5, 1) << 1;
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unsigned Rm = fieldFromInstruction(Insn, 0, 4);
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if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
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return MCDisassembler::Fail;
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} else {
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fc = fieldFromInstruction(Insn, 12, 1) << 2 |
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fieldFromInstruction(Insn, 7, 1) |
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fieldFromInstruction(Insn, 0, 1) << 1;
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unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
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fieldFromInstruction(Insn, 1, 3);
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if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
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return MCDisassembler::Fail;
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}
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if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(ARMVCC::None));
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Inst.addOperand(MCOperand::createReg(0));
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Inst.addOperand(MCOperand::createImm(0));
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return S;
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}
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299
test/MC/ARM/mve-vcmp.s
Normal file
299
test/MC/ARM/mve-vcmp.s
Normal file
@ -0,0 +1,299 @@
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# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2>%t \
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# RUN: | FileCheck --check-prefix=CHECK-NOFP %s
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# RUN: FileCheck --check-prefix=ERROR-NOFP < %t %s
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# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
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# RUN: | FileCheck --check-prefix=CHECK %s
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# RUN: FileCheck --check-prefix=ERROR < %t %s
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# CHECK: vcmp.f16 eq, q0, q4 @ encoding: [0x31,0xfe,0x08,0x0f]
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# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
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# CHECK-NOFP-NOT: vcmp.f16 eq, q0, q4 @ encoding: [0x31,0xfe,0x08,0x0f]
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vcmp.f16 eq, q0, q4
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# CHECK: vcmp.f16 ne, q2, q7 @ encoding: [0x35,0xfe,0x8e,0x0f]
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# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
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# CHECK-NOFP-NOT: vcmp.f16 ne, q2, q7 @ encoding: [0x35,0xfe,0x8e,0x0f]
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vcmp.f16 ne, q2, q7
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# CHECK: vcmp.f16 ge, q0, q0 @ encoding: [0x31,0xfe,0x00,0x1f]
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# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
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# CHECK-NOFP-NOT: vcmp.f16 ge, q0, q0 @ encoding: [0x31,0xfe,0x00,0x1f]
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vcmp.f16 ge, q0, q0
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# CHECK: vcmp.f16 lt, q0, q1 @ encoding: [0x31,0xfe,0x82,0x1f]
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# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
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# CHECK-NOFP-NOT: vcmp.f16 lt, q0, q1 @ encoding: [0x31,0xfe,0x82,0x1f]
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vcmp.f16 lt, q0, q1
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# CHECK: vcmp.f16 gt, q1, q4 @ encoding: [0x33,0xfe,0x09,0x1f]
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# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
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# CHECK-NOFP-NOT: vcmp.f16 gt, q1, q4 @ encoding: [0x33,0xfe,0x09,0x1f]
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vcmp.f16 gt, q1, q4
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# CHECK: vcmp.f16 le, q2, q6 @ encoding: [0x35,0xfe,0x8d,0x1f]
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# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
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# CHECK-NOFP-NOT: vcmp.f16 le, q2, q6 @ encoding: [0x35,0xfe,0x8d,0x1f]
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vcmp.f16 le, q2, q6
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# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE
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vcmp.f16 hi, q2, q6
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# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE
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vcmp.f16 hs, q2, q6
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# CHECK: vcmp.f32 eq, q2, q5 @ encoding: [0x35,0xee,0x0a,0x0f]
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# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
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# CHECK-NOFP-NOT: vcmp.f32 eq, q2, q5 @ encoding: [0x35,0xee,0x0a,0x0f]
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vcmp.f32 eq, q2, q5
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# CHECK: vcmp.f32 ne, q3, q4 @ encoding: [0x37,0xee,0x88,0x0f]
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# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
|
||||
# CHECK-NOFP-NOT: vcmp.f32 ne, q3, q4 @ encoding: [0x37,0xee,0x88,0x0f]
|
||||
vcmp.f32 ne, q3, q4
|
||||
|
||||
# CHECK: vcmp.f32 ge, q0, q7 @ encoding: [0x31,0xee,0x0e,0x1f]
|
||||
# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
|
||||
# CHECK-NOFP-NOT: vcmp.f32 ge, q0, q7 @ encoding: [0x31,0xee,0x0e,0x1f]
|
||||
vcmp.f32 ge, q0, q7
|
||||
|
||||
# CHECK: vcmp.f32 lt, q5, q2 @ encoding: [0x3b,0xee,0x84,0x1f]
|
||||
# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
|
||||
# CHECK-NOFP-NOT: vcmp.f32 lt, q5, q2 @ encoding: [0x3b,0xee,0x84,0x1f]
|
||||
vcmp.f32 lt, q5, q2
|
||||
|
||||
# CHECK: vcmp.f32 gt, q2, q7 @ encoding: [0x35,0xee,0x0f,0x1f]
|
||||
# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
|
||||
# CHECK-NOFP-NOT: vcmp.f32 gt, q2, q7 @ encoding: [0x35,0xee,0x0f,0x1f]
|
||||
vcmp.f32 gt, q2, q7
|
||||
|
||||
# CHECK: vcmp.f32 le, q2, q4 @ encoding: [0x35,0xee,0x89,0x1f]
|
||||
# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
|
||||
# CHECK-NOFP-NOT: vcmp.f32 le, q2, q4 @ encoding: [0x35,0xee,0x89,0x1f]
|
||||
vcmp.f32 le, q2, q4
|
||||
|
||||
# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE
|
||||
vcmp.f32 hi, q2, q6
|
||||
|
||||
# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE
|
||||
vcmp.f32 hs, q2, q6
|
||||
|
||||
# CHECK: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
|
||||
# CHECK-NOFP: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
|
||||
vcmp.i8 eq, q4, q6
|
||||
|
||||
# CHECK: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
|
||||
# CHECK-NOFP: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
|
||||
vcmp.i8 ne, q2, q2
|
||||
|
||||
# ERROR: [[@LINE+1]]:9: {{error|note}}: condition code for sign-independent integer comparison must be EQ or NE
|
||||
vcmp.i8 hs, q2, q6
|
||||
|
||||
# ERROR: [[@LINE+1]]:9: {{error|note}}: condition code for sign-independent integer comparison must be EQ or NE
|
||||
vcmp.i8 le, q2, q6
|
||||
|
||||
# CHECK: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
|
||||
# CHECK-NOFP: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
|
||||
vcmp.s8 eq, q4, q6
|
||||
|
||||
# CHECK: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
|
||||
# CHECK-NOFP: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
|
||||
vcmp.s8 ne, q2, q2
|
||||
|
||||
# CHECK: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
|
||||
# CHECK-NOFP: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
|
||||
vcmp.u8 eq, q4, q6
|
||||
|
||||
# CHECK: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
|
||||
# CHECK-NOFP: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
|
||||
vcmp.u8 ne, q2, q2
|
||||
|
||||
# CHECK: vcmp.s8 ge, q0, q0 @ encoding: [0x01,0xfe,0x00,0x1f]
|
||||
# CHECK-NOFP: vcmp.s8 ge, q0, q0 @ encoding: [0x01,0xfe,0x00,0x1f]
|
||||
vcmp.s8 ge, q0, q0
|
||||
|
||||
# CHECK: vcmp.s8 lt, q2, q7 @ encoding: [0x05,0xfe,0x8e,0x1f]
|
||||
# CHECK-NOFP: vcmp.s8 lt, q2, q7 @ encoding: [0x05,0xfe,0x8e,0x1f]
|
||||
vcmp.s8 lt, q2, q7
|
||||
|
||||
# CHECK: vcmp.s8 gt, q4, q3 @ encoding: [0x09,0xfe,0x07,0x1f]
|
||||
# CHECK-NOFP: vcmp.s8 gt, q4, q3 @ encoding: [0x09,0xfe,0x07,0x1f]
|
||||
vcmp.s8 gt, q4, q3
|
||||
|
||||
# CHECK: vcmp.s8 le, q7, q3 @ encoding: [0x0f,0xfe,0x87,0x1f]
|
||||
# CHECK-NOFP: vcmp.s8 le, q7, q3 @ encoding: [0x0f,0xfe,0x87,0x1f]
|
||||
vcmp.s8 le, q7, q3
|
||||
|
||||
# ERROR: [[@LINE+1]]:9: {{error|note}}: condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE
|
||||
vcmp.s8 hs, q2, q6
|
||||
|
||||
# CHECK: vcmp.u8 hi, q1, q4 @ encoding: [0x03,0xfe,0x89,0x0f]
|
||||
# CHECK-NOFP: vcmp.u8 hi, q1, q4 @ encoding: [0x03,0xfe,0x89,0x0f]
|
||||
vcmp.u8 hi, q1, q4
|
||||
|
||||
# CHECK: vcmp.u8 cs, q1, q4 @ encoding: [0x03,0xfe,0x09,0x0f]
|
||||
# CHECK-NOFP: vcmp.u8 cs, q1, q4 @ encoding: [0x03,0xfe,0x09,0x0f]
|
||||
vcmp.u8 cs, q1, q4
|
||||
|
||||
# ERROR: [[@LINE+1]]:9: {{error|note}}: condition code for unsigned integer comparison must be EQ, NE, HS or HI
|
||||
vcmp.u8 gt, q2, q6
|
||||
|
||||
# ERROR: [[@LINE+1]]:9: {{error|note}}: condition code for unsigned integer comparison must be EQ, NE, HS or HI
|
||||
vcmp.u8 lo, q2, q6
|
||||
|
||||
# CHECK: vcmp.i16 eq, q4, q7 @ encoding: [0x19,0xfe,0x0e,0x0f]
|
||||
# CHECK-NOFP: vcmp.i16 eq, q4, q7 @ encoding: [0x19,0xfe,0x0e,0x0f]
|
||||
vcmp.i16 eq, q4, q7
|
||||
|
||||
# CHECK: vcmp.i16 ne, q2, q1 @ encoding: [0x15,0xfe,0x82,0x0f]
|
||||
# CHECK-NOFP: vcmp.i16 ne, q2, q1 @ encoding: [0x15,0xfe,0x82,0x0f]
|
||||
vcmp.i16 ne, q2, q1
|
||||
|
||||
# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for sign-independent integer comparison must be EQ or NE
|
||||
vcmp.i16 hi, q2, q6
|
||||
|
||||
# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for sign-independent integer comparison must be EQ or NE
|
||||
vcmp.i16 lt, q2, q6
|
||||
|
||||
# CHECK: vcmp.s16 ge, q1, q7 @ encoding: [0x13,0xfe,0x0e,0x1f]
|
||||
# CHECK-NOFP: vcmp.s16 ge, q1, q7 @ encoding: [0x13,0xfe,0x0e,0x1f]
|
||||
vcmp.s16 ge, q1, q7
|
||||
|
||||
# CHECK: vcmp.s16 lt, q0, q1 @ encoding: [0x11,0xfe,0x82,0x1f]
|
||||
# CHECK-NOFP: vcmp.s16 lt, q0, q1 @ encoding: [0x11,0xfe,0x82,0x1f]
|
||||
vcmp.s16 lt, q0, q1
|
||||
|
||||
# CHECK: vcmp.s16 gt, q1, q7 @ encoding: [0x13,0xfe,0x0f,0x1f]
|
||||
# CHECK-NOFP: vcmp.s16 gt, q1, q7 @ encoding: [0x13,0xfe,0x0f,0x1f]
|
||||
vcmp.s16 gt, q1, q7
|
||||
|
||||
# CHECK: vcmp.s16 le, q2, q1 @ encoding: [0x15,0xfe,0x83,0x1f]
|
||||
# CHECK-NOFP: vcmp.s16 le, q2, q1 @ encoding: [0x15,0xfe,0x83,0x1f]
|
||||
vcmp.s16 le, q2, q1
|
||||
|
||||
# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE
|
||||
vcmp.s16 hi, q2, q6
|
||||
|
||||
# CHECK: vcmp.u16 hi, q1, q4 @ encoding: [0x13,0xfe,0x89,0x0f]
|
||||
# CHECK-NOFP: vcmp.u16 hi, q1, q4 @ encoding: [0x13,0xfe,0x89,0x0f]
|
||||
vcmp.u16 hi, q1, q4
|
||||
|
||||
# CHECK: vcmp.u16 cs, q1, q4 @ encoding: [0x13,0xfe,0x09,0x0f]
|
||||
# CHECK-NOFP: vcmp.u16 cs, q1, q4 @ encoding: [0x13,0xfe,0x09,0x0f]
|
||||
vcmp.u16 cs, q1, q4
|
||||
|
||||
# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for unsigned integer comparison must be EQ, NE, HS or HI
|
||||
vcmp.u16 ge, q2, q6
|
||||
|
||||
# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for unsigned integer comparison must be EQ, NE, HS or HI
|
||||
vcmp.u16 ls, q2, q6
|
||||
|
||||
# CHECK: vcmp.i32 eq, q2, q7 @ encoding: [0x25,0xfe,0x0e,0x0f]
|
||||
# CHECK-NOFP: vcmp.i32 eq, q2, q7 @ encoding: [0x25,0xfe,0x0e,0x0f]
|
||||
vcmp.i32 eq, q2, q7
|
||||
|
||||
# CHECK: vcmp.i32 ne, q2, q4 @ encoding: [0x25,0xfe,0x88,0x0f]
|
||||
# CHECK-NOFP: vcmp.i32 ne, q2, q4 @ encoding: [0x25,0xfe,0x88,0x0f]
|
||||
vcmp.i32 ne, q2, q4
|
||||
|
||||
# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for sign-independent integer comparison must be EQ or NE
|
||||
vcmp.i32 lo, q2, q6
|
||||
|
||||
# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for sign-independent integer comparison must be EQ or NE
|
||||
vcmp.i32 ge, q2, q6
|
||||
|
||||
# CHECK: vcmp.s32 ge, q5, q5 @ encoding: [0x2b,0xfe,0x0a,0x1f]
|
||||
# CHECK-NOFP: vcmp.s32 ge, q5, q5 @ encoding: [0x2b,0xfe,0x0a,0x1f]
|
||||
vcmp.s32 ge, q5, q5
|
||||
|
||||
# CHECK: vcmp.s32 lt, q2, q2 @ encoding: [0x25,0xfe,0x84,0x1f]
|
||||
# CHECK-NOFP: vcmp.s32 lt, q2, q2 @ encoding: [0x25,0xfe,0x84,0x1f]
|
||||
vcmp.s32 lt, q2, q2
|
||||
|
||||
# CHECK: vcmp.s32 gt, q0, q1 @ encoding: [0x21,0xfe,0x03,0x1f]
|
||||
# CHECK-NOFP: vcmp.s32 gt, q0, q1 @ encoding: [0x21,0xfe,0x03,0x1f]
|
||||
vcmp.s32 gt, q0, q1
|
||||
|
||||
# CHECK: vcmp.s32 le, q5, q4 @ encoding: [0x2b,0xfe,0x89,0x1f]
|
||||
# CHECK-NOFP: vcmp.s32 le, q5, q4 @ encoding: [0x2b,0xfe,0x89,0x1f]
|
||||
vcmp.s32 le, q5, q4
|
||||
|
||||
# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE
|
||||
vcmp.s32 ls, q2, q6
|
||||
|
||||
# CHECK: vcmp.u32 hi, q1, q4 @ encoding: [0x23,0xfe,0x89,0x0f]
|
||||
# CHECK-NOFP: vcmp.u32 hi, q1, q4 @ encoding: [0x23,0xfe,0x89,0x0f]
|
||||
vcmp.u32 hi, q1, q4
|
||||
|
||||
# CHECK: vcmp.u32 cs, q1, q4 @ encoding: [0x23,0xfe,0x09,0x0f]
|
||||
# CHECK-NOFP: vcmp.u32 cs, q1, q4 @ encoding: [0x23,0xfe,0x09,0x0f]
|
||||
vcmp.u32 cs, q1, q4
|
||||
|
||||
# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for unsigned integer comparison must be EQ, NE, HS or HI
|
||||
vcmp.u32 vs, q2, q6
|
||||
|
||||
# ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for unsigned integer comparison must be EQ, NE, HS or HI
|
||||
vcmp.u32 mi, q2, q6
|
||||
|
||||
# CHECK: vcmp.f16 gt, q4, zr @ encoding: [0x39,0xfe,0x6f,0x1f]
|
||||
# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
|
||||
# CHECK-NOFP-NOT: vcmp.f16 gt, q4, zr @ encoding: [0x39,0xfe,0x6f,0x1f]
|
||||
vcmp.f16 gt, q4, zr
|
||||
|
||||
# CHECK: vcmp.f16 eq, q4, r12 @ encoding: [0x39,0xfe,0x4c,0x0f]
|
||||
# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
|
||||
# CHECK-NOFP-NOT: vcmp.f16 eq, q4, r12 @ encoding: [0x39,0xfe,0x4c,0x0f]
|
||||
vcmp.f16 eq, q4, r12
|
||||
|
||||
# CHECK: vcmp.f32 ne, q3, r0 @ encoding: [0x37,0xee,0xc0,0x0f]
|
||||
# ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
|
||||
# CHECK-NOFP-NOT: vcmp.f32 ne, q3, r0 @ encoding: [0x37,0xee,0xc0,0x0f]
|
||||
vcmp.f32 ne, q3, r0
|
||||
|
||||
# CHECK: vcmp.i8 eq, q1, r0 @ encoding: [0x03,0xfe,0x40,0x0f]
|
||||
# CHECK-NOFP: vcmp.i8 eq, q1, r0 @ encoding: [0x03,0xfe,0x40,0x0f]
|
||||
vcmp.i8 eq, q1, r0
|
||||
|
||||
# CHECK: vcmp.s8 le, q1, r0 @ encoding: [0x03,0xfe,0xe0,0x1f]
|
||||
# CHECK-NOFP: vcmp.s8 le, q1, r0 @ encoding: [0x03,0xfe,0xe0,0x1f]
|
||||
vcmp.s8 le, q1, r0
|
||||
|
||||
# CHECK: vcmp.u8 cs, q1, r0 @ encoding: [0x03,0xfe,0x60,0x0f]
|
||||
# CHECK-NOFP: vcmp.u8 cs, q1, r0 @ encoding: [0x03,0xfe,0x60,0x0f]
|
||||
vcmp.u8 cs, q1, r0
|
||||
|
||||
# CHECK: vcmp.i16 eq, q5, r10 @ encoding: [0x1b,0xfe,0x4a,0x0f]
|
||||
# CHECK-NOFP: vcmp.i16 eq, q5, r10 @ encoding: [0x1b,0xfe,0x4a,0x0f]
|
||||
vcmp.i16 eq, q5, r10
|
||||
|
||||
# CHECK: vcmp.i32 eq, q1, r4 @ encoding: [0x23,0xfe,0x44,0x0f]
|
||||
# CHECK-NOFP: vcmp.i32 eq, q1, r4 @ encoding: [0x23,0xfe,0x44,0x0f]
|
||||
vcmp.i32 eq, q1, r4
|
||||
|
||||
vpste
|
||||
vcmpt.i8 eq, q0, r0
|
||||
vcmpe.i16 ne, q0, r0
|
||||
# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
|
||||
# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
|
||||
# CHECK: vcmpt.i8 eq, q0, r0 @ encoding: [0x01,0xfe,0x40,0x0f]
|
||||
# CHECK-NOFP: vcmpt.i8 eq, q0, r0 @ encoding: [0x01,0xfe,0x40,0x0f]
|
||||
# CHECK: vcmpe.i16 ne, q0, r0 @ encoding: [0x11,0xfe,0xc0,0x0f]
|
||||
# CHECK-NOFP: vcmpe.i16 ne, q0, r0 @ encoding: [0x11,0xfe,0xc0,0x0f]
|
||||
|
||||
# Ensure the scalar FP instructions VCMP and VCMPE are still correctly
|
||||
# distinguished, in spite of VCMPE sometimes being a VPT-suffixed
|
||||
# version of VCMP with identical encoding.
|
||||
vcmp.f16 s0,s1
|
||||
vcmpe.f16 s0,s1
|
||||
# CHECK: vcmp.f16 s0, s1 @ encoding: [0xb4,0xee,0x60,0x09]
|
||||
# CHECK: vcmpe.f16 s0, s1 @ encoding: [0xb4,0xee,0xe0,0x09]
|
||||
# CHECK-NOFP-NOT: vcmp.f16 s0, s1 @ encoding: [0xb4,0xee,0x60,0x09]
|
||||
# CHECK-NOFP-NOT: vcmpe.f16 s0, s1 @ encoding: [0xb4,0xee,0xe0,0x09]
|
||||
|
||||
itt eq
|
||||
vcmpeq.f32 s0, s1
|
||||
vcmpeeq.f32 s0, s1
|
||||
# CHECK: itt eq @ encoding: [0x04,0xbf]
|
||||
# CHECK: vcmpeq.f32 s0, s1 @ encoding: [0xb4,0xee,0x60,0x0a]
|
||||
# CHECK-NOFP-NOT: vcmpeq.f32 s0, s1 @ encoding: [0xb4,0xee,0x60,0x0a]
|
||||
# CHECK: vcmpeeq.f32 s0, s1 @ encoding: [0xb4,0xee,0xe0,0x0a]
|
||||
# CHECK-NOFP-NOT: vcmpeeq.f32 s0, s1 @ encoding: [0xb4,0xee,0xe0,0x0a]
|
||||
179
test/MC/Disassembler/ARM/mve-vcmp.txt
Normal file
179
test/MC/Disassembler/ARM/mve-vcmp.txt
Normal file
@ -0,0 +1,179 @@
|
||||
# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
|
||||
# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
|
||||
# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
|
||||
|
||||
# CHECK: vcmp.f16 eq, q0, q4 @ encoding: [0x31,0xfe,0x08,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x31,0xfe,0x08,0x0f]
|
||||
|
||||
# CHECK: vcmp.f16 ne, q2, q7 @ encoding: [0x35,0xfe,0x8e,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x35,0xfe,0x8e,0x0f]
|
||||
|
||||
# CHECK: vcmp.f16 ge, q0, q0 @ encoding: [0x31,0xfe,0x00,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x31,0xfe,0x00,0x1f]
|
||||
|
||||
# CHECK: vcmp.f16 lt, q0, q1 @ encoding: [0x31,0xfe,0x82,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x31,0xfe,0x82,0x1f]
|
||||
|
||||
# CHECK: vcmp.f16 gt, q1, q4 @ encoding: [0x33,0xfe,0x09,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x33,0xfe,0x09,0x1f]
|
||||
|
||||
# CHECK: vcmp.f16 le, q2, q6 @ encoding: [0x35,0xfe,0x8d,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x35,0xfe,0x8d,0x1f]
|
||||
|
||||
# CHECK: vcmp.f32 eq, q2, q5 @ encoding: [0x35,0xee,0x0a,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x35,0xee,0x0a,0x0f]
|
||||
|
||||
# CHECK: vcmp.f32 ne, q3, q4 @ encoding: [0x37,0xee,0x88,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x37,0xee,0x88,0x0f]
|
||||
|
||||
# CHECK: vcmp.f32 ge, q0, q7 @ encoding: [0x31,0xee,0x0e,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x31,0xee,0x0e,0x1f]
|
||||
|
||||
# CHECK: vcmp.f32 lt, q5, q2 @ encoding: [0x3b,0xee,0x84,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x3b,0xee,0x84,0x1f]
|
||||
|
||||
# CHECK: vcmp.f32 gt, q2, q7 @ encoding: [0x35,0xee,0x0f,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x35,0xee,0x0f,0x1f]
|
||||
|
||||
# CHECK: vcmp.f32 le, q2, q4 @ encoding: [0x35,0xee,0x89,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x35,0xee,0x89,0x1f]
|
||||
|
||||
# CHECK: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x09,0xfe,0x0c,0x0f]
|
||||
|
||||
# CHECK: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x05,0xfe,0x84,0x0f]
|
||||
|
||||
# CHECK: vcmp.s8 ge, q0, q0 @ encoding: [0x01,0xfe,0x00,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x01,0xfe,0x00,0x1f]
|
||||
|
||||
# CHECK: vcmp.s8 lt, q2, q7 @ encoding: [0x05,0xfe,0x8e,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x05,0xfe,0x8e,0x1f]
|
||||
|
||||
# CHECK: vcmp.s8 gt, q4, q3 @ encoding: [0x09,0xfe,0x07,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x09,0xfe,0x07,0x1f]
|
||||
|
||||
# CHECK: vcmp.s8 le, q7, q3 @ encoding: [0x0f,0xfe,0x87,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x0f,0xfe,0x87,0x1f]
|
||||
|
||||
# CHECK: vcmp.u8 hi, q1, q4 @ encoding: [0x03,0xfe,0x89,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x03,0xfe,0x89,0x0f]
|
||||
|
||||
# CHECK: vcmp.u8 cs, q1, q4 @ encoding: [0x03,0xfe,0x09,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x03,0xfe,0x09,0x0f]
|
||||
|
||||
# CHECK: vcmp.i16 eq, q4, q7 @ encoding: [0x19,0xfe,0x0e,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x19,0xfe,0x0e,0x0f]
|
||||
|
||||
# CHECK: vcmp.i16 ne, q2, q1 @ encoding: [0x15,0xfe,0x82,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x15,0xfe,0x82,0x0f]
|
||||
|
||||
# CHECK: vcmp.s16 ge, q1, q7 @ encoding: [0x13,0xfe,0x0e,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x13,0xfe,0x0e,0x1f]
|
||||
|
||||
# CHECK: vcmp.s16 lt, q0, q1 @ encoding: [0x11,0xfe,0x82,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x11,0xfe,0x82,0x1f]
|
||||
|
||||
# CHECK: vcmp.s16 gt, q1, q7 @ encoding: [0x13,0xfe,0x0f,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x13,0xfe,0x0f,0x1f]
|
||||
|
||||
# CHECK: vcmp.s16 le, q2, q1 @ encoding: [0x15,0xfe,0x83,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x15,0xfe,0x83,0x1f]
|
||||
|
||||
# CHECK: vcmp.u16 hi, q1, q4 @ encoding: [0x13,0xfe,0x89,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x13,0xfe,0x89,0x0f]
|
||||
|
||||
# CHECK: vcmp.u16 cs, q1, q4 @ encoding: [0x13,0xfe,0x09,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x13,0xfe,0x09,0x0f]
|
||||
|
||||
# CHECK: vcmp.i32 eq, q2, q7 @ encoding: [0x25,0xfe,0x0e,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x25,0xfe,0x0e,0x0f]
|
||||
|
||||
# CHECK: vcmp.i32 ne, q2, q4 @ encoding: [0x25,0xfe,0x88,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x25,0xfe,0x88,0x0f]
|
||||
|
||||
# CHECK: vcmp.s32 ge, q5, q5 @ encoding: [0x2b,0xfe,0x0a,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x2b,0xfe,0x0a,0x1f]
|
||||
|
||||
# CHECK: vcmp.s32 lt, q2, q2 @ encoding: [0x25,0xfe,0x84,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x25,0xfe,0x84,0x1f]
|
||||
|
||||
# CHECK: vcmp.s32 gt, q0, q1 @ encoding: [0x21,0xfe,0x03,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x21,0xfe,0x03,0x1f]
|
||||
|
||||
# CHECK: vcmp.s32 le, q5, q4 @ encoding: [0x2b,0xfe,0x89,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x2b,0xfe,0x89,0x1f]
|
||||
|
||||
# CHECK: vcmp.u32 hi, q1, q4 @ encoding: [0x23,0xfe,0x89,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x23,0xfe,0x89,0x0f]
|
||||
|
||||
# CHECK: vcmp.u32 cs, q1, q4 @ encoding: [0x23,0xfe,0x09,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x23,0xfe,0x09,0x0f]
|
||||
|
||||
# CHECK: vcmp.f16 gt, q4, zr @ encoding: [0x39,0xfe,0x6f,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x39,0xfe,0x6f,0x1f]
|
||||
|
||||
# CHECK: vcmp.f16 eq, q4, r12 @ encoding: [0x39,0xfe,0x4c,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x39,0xfe,0x4c,0x0f]
|
||||
|
||||
# CHECK: vcmp.f32 ne, q3, r0 @ encoding: [0x37,0xee,0xc0,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x37,0xee,0xc0,0x0f]
|
||||
|
||||
# CHECK: vcmp.i8 eq, q1, r0 @ encoding: [0x03,0xfe,0x40,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x03,0xfe,0x40,0x0f]
|
||||
|
||||
# CHECK: vcmp.s8 le, q1, r0 @ encoding: [0x03,0xfe,0xe0,0x1f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x03,0xfe,0xe0,0x1f]
|
||||
|
||||
# CHECK: vcmp.u8 cs, q1, r0 @ encoding: [0x03,0xfe,0x60,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x03,0xfe,0x60,0x0f]
|
||||
|
||||
# CHECK: vcmp.i16 eq, q5, r10 @ encoding: [0x1b,0xfe,0x4a,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x1b,0xfe,0x4a,0x0f]
|
||||
|
||||
# CHECK: vcmp.i32 eq, q1, r4 @ encoding: [0x23,0xfe,0x44,0x0f]
|
||||
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
|
||||
[0x23,0xfe,0x44,0x0f]
|
||||
Loading…
Reference in New Issue
Block a user